From 75d66dc335f3aaa85e92f790b708f70088db1ba4 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 29 Jun 2020 12:52:28 -0700 Subject: [PATCH 01/22] fix sources.txt, run_ase.sh --- hw/opae/README | 1 + hw/opae/run_ase.sh | 5 ++++- hw/opae/sources.txt | 1 + hw/rtl/VX_alu_unit.v | 13 +++++-------- hw/rtl/VX_define.vh | 4 ++++ hw/rtl/libs/VX_fair_arbiter.v | 8 +++----- 6 files changed, 18 insertions(+), 14 deletions(-) diff --git a/hw/opae/README b/hw/opae/README index fc164bfc..86e6f862 100644 --- a/hw/opae/README +++ b/hw/opae/README @@ -62,6 +62,7 @@ make ase # tests ./run_ase.sh build_ase_1c ../../driver/tests/basic/basic ./run_ase.sh build_ase_1c ../../driver/tests/demo/demo +./run_ase.sh build_ase_1c ../../benchmarks/opencl/vecadd/vecadd # modify "vsim_run.tcl" to dump VCD trace vcd file vortex.vcd diff --git a/hw/opae/run_ase.sh b/hw/opae/run_ase.sh index 9a0fbf64..9e3b5d6c 100755 --- a/hw/opae/run_ase.sh +++ b/hw/opae/run_ase.sh @@ -7,6 +7,9 @@ BUILD_DIR=$1 PROGRAM=$(basename "$2") PROGRAM_DIR=`dirname $2` +POCL_RT_PATH=$SCRIPT_DIR/../../benchmarks/opencl/runtime/lib +VORTEX_DRV_PATH=$SCRIPT_DIR/../../driver/opae/ase + # Export ASE_WORKDIR variable export ASE_WORKDIR=$SCRIPT_DIR/$BUILD_DIR/work @@ -33,5 +36,5 @@ done # run application pushd $PROGRAM_DIR echo " [DBG] running ./$PROGRAM $*" -ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$LD_LIBRARY_PATH ./$PROGRAM $* +ASE_LOG=0 LD_LIBRARY_PATH=$POCL_RT_PATH:$VORTEX_DRV_PATH:$LD_LIBRARY_PATH ./$PROGRAM $* popd \ No newline at end of file diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 6058a31a..0263e558 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -67,6 +67,7 @@ QI:vortex_afu.qsf ../rtl/libs/VX_priority_encoder.v ../rtl/libs/VX_generic_queue.v ../rtl/libs/VX_indexable_queue.v +../rtl/libs/VX_fair_arbiter.v ../rtl/libs/VX_fixed_arbiter.v ../rtl/libs/VX_rr_arbiter.v ../rtl/libs/VX_countones.v diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index ccc9b1ab..b0d0c20f 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -13,9 +13,6 @@ module VX_alu_unit ( output reg [31:0] alu_result, output reg alu_stall ); - localparam DIV_PIPELINE_LEN = 18; - localparam MUL_PIPELINE_LEN = 1; - wire[31:0] div_result_unsigned; wire[31:0] div_result_signed; @@ -37,11 +34,11 @@ module VX_alu_unit ( `ALU_DIV, `ALU_DIVU, `ALU_REM, - `ALU_REMU: inst_delay = DIV_PIPELINE_LEN; + `ALU_REMU: inst_delay = `DIV_LATENCY; `ALU_MUL, `ALU_MULH, `ALU_MULHSU, - `ALU_MULHU: inst_delay = MUL_PIPELINE_LEN; + `ALU_MULHU: inst_delay = `MUL_LATENCY; default: inst_delay = 0; endcase end @@ -91,7 +88,7 @@ module VX_alu_unit ( .WIDTHD(32), .NSIGNED(0), .DSIGNED(0), - .PIPELINE(DIV_PIPELINE_LEN) + .PIPELINE(`DIV_LATENCY) ) udiv ( .clk(clk), .reset(reset), @@ -106,7 +103,7 @@ module VX_alu_unit ( .WIDTHD(32), .NSIGNED(1), .DSIGNED(1), - .PIPELINE(DIV_PIPELINE_LEN) + .PIPELINE(`DIV_LATENCY) ) sdiv ( .clk(clk), .reset(reset), @@ -124,7 +121,7 @@ module VX_alu_unit ( .WIDTHB(33), .WIDTHP(64), .SIGNED(1), - .PIPELINE(MUL_PIPELINE_LEN) + .PIPELINE(`MUL_LATENCY) ) multiplier ( .clk(clk), .reset(reset), diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index b36c1751..510d55ca 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -72,6 +72,10 @@ `define CSR_WIDTH 12 +`define DIV_LATENCY 16 + +`define MUL_LATENCY 1 + /////////////////////////////////////////////////////////////////////////////// `define BYTE_EN_NO 3'h7 diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.v index ca32a5fc..5ac5749e 100644 --- a/hw/rtl/libs/VX_fair_arbiter.v +++ b/hw/rtl/libs/VX_fair_arbiter.v @@ -11,7 +11,6 @@ module VX_fair_arbiter #( output wire grant_valid ); - if (N == 1) begin `UNUSED_VAR (clk) @@ -20,8 +19,7 @@ module VX_fair_arbiter #( assign grant_onehot = requests; assign grant_valid = requests[0]; - end else begin - + end else begin reg [N-1:0] requests_use; wire [N-1:0] update_value; @@ -48,7 +46,7 @@ module VX_fair_arbiter #( reg [N-1:0] grant_onehot_r; - VX_priority_encoder # ( + VX_priority_encoder #( .N(N) ) priority_encoder ( .data_in (requests_use), @@ -61,7 +59,7 @@ module VX_fair_arbiter #( grant_onehot_r[grant_index] = 1; end assign grant_onehot = grant_onehot_r; - assign late_value = ((refill_original ^ requests) & ~refill_original); + assign late_value = ((refill_original ^ requests) & ~refill_original); assign update_value = (requests_use & ~grant_onehot_r) | late_value; end From f66c2513095f353d0e523b7c4e01bc6630ee2f6b Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 29 Jun 2020 15:09:14 -0700 Subject: [PATCH 02/22] minor update --- hw/rtl/VX_define.vh | 4 ++-- hw/syn/quartus/.gitignore | 5 ++++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 510d55ca..3ddc4dff 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -72,9 +72,9 @@ `define CSR_WIDTH 12 -`define DIV_LATENCY 16 +`define DIV_LATENCY 18 -`define MUL_LATENCY 1 +`define MUL_LATENCY 2 /////////////////////////////////////////////////////////////////////////////// diff --git a/hw/syn/quartus/.gitignore b/hw/syn/quartus/.gitignore index fedeee42..eac68fed 100644 --- a/hw/syn/quartus/.gitignore +++ b/hw/syn/quartus/.gitignore @@ -8,4 +8,7 @@ !/vortex/Makefile /pipeline/* -!/pipeline/Makefile \ No newline at end of file +!/pipeline/Makefile + +/core/* +!/core/Makefile From b8e8cab1eec10cc14ca97f789354df1fc2ad4b78 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Mon, 29 Jun 2020 23:00:34 -0700 Subject: [PATCH 03/22] Added CSR IO req/rsp V0.1 --- hw/rtl/VX_back_end.v | 27 ++++++++++++- hw/rtl/VX_cluster.v | 15 +++++++- hw/rtl/VX_core.v | 42 +++++++++++++++++++- hw/rtl/VX_csr_arbiter.v | 64 +++++++++++++++++++++++++++++++ hw/rtl/VX_csr_pipe.v | 6 +-- hw/rtl/VX_gpr_stage.v | 6 ++- hw/rtl/VX_pipeline.v | 8 +++- hw/rtl/interfaces/VX_csr_req_if.v | 5 ++- hw/rtl/interfaces/VX_wb_if.v | 5 ++- 9 files changed, 167 insertions(+), 11 deletions(-) create mode 100644 hw/rtl/VX_csr_arbiter.v diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index 34990009..c9f45d04 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -9,6 +9,10 @@ module VX_back_end #( input wire clk, input wire reset, + // IO CSR + VX_csr_req_if io_csr_req, + VX_wb_if io_csr_rsp, + input wire schedule_delay, VX_cache_core_req_if dcache_req_if, @@ -31,6 +35,7 @@ module VX_back_end #( wire no_slot_mem; wire no_slot_exec; + // LSU input + output VX_lsu_req_if lsu_req_if(); VX_wb_if mem_wb_if(); @@ -99,15 +104,33 @@ module VX_back_end #( .warp_ctl_if (warp_ctl_if) ); + VX_csr_req_if issued_csr_req(); + + VX_wb_if csr_pipe_rsp(); + + VX_csr_arbiter csr_arbiter ( + .clk (clk), + .reset (reset), + .csr_pipe_stall(stall_gpr_csr), + .core_csr_req (csr_req_if), + .io_csr_req (io_csr_req), + .issued_csr_req(issued_csr_req), + + .csr_pipe_rsp (csr_pipe_rsp), + .csr_wb_if (csr_wb_if), + .csr_io_rsp (io_csr_rsp) + + ); + VX_csr_pipe #( .CORE_ID(CORE_ID) ) csr_pipe ( .clk (clk), .reset (reset), .no_slot_csr (no_slot_csr), - .csr_req_if (csr_req_if), + .csr_req_if (issued_csr_req), .writeback_if (writeback_if), - .csr_wb_if (csr_wb_if), + .csr_wb_if (csr_pipe_rsp), .stall_gpr_csr (stall_gpr_csr) ); diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index d9539660..f2ebe770 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -174,6 +174,19 @@ module VX_cluster #( .io_rsp_tag (per_core_io_rsp_tag [i]), .io_rsp_ready (per_core_io_rsp_ready [i]), + + + .csr_io_req_valid (1'b0), // Valid CSR IO Request + `UNUSED_PIN(csr_io_req_ready), // Core is ready to accept Request + `UNUSED_PIN(csr_io_req_cid), // CORE_ID of the intended request + `UNUSED_PIN(csr_io_req_addr), // ADDRESS of request + `UNUSED_PIN(csr_io_req_rw), // Read=0, Write=1 + `UNUSED_PIN(csr_io_req_data), // Data to write + + `UNUSED_PIN(csr_io_rsp_valid), // Core IO Response valid + `UNUSED_PIN(csr_io_rsp_data), // Core IO Response data + + .busy (per_core_busy [i]), .ebreak (per_core_ebreak [i]) ); @@ -537,4 +550,4 @@ module VX_cluster #( end -endmodule \ No newline at end of file +endmodule diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 33ae9635..fb176c5b 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -70,12 +70,47 @@ module VX_core #( input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, + // IO CSR Request + input wire csr_io_req_valid, + input wire[`NC_BITS-1:0] csr_io_req_cid, + input wire[11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire[31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // IO CSR Response + output wire csr_io_rsp_valid, + output wire[31:0] csr_io_rsp_data, + // Status output wire busy, output wire ebreak ); - // Dcache Interfaces + // IO CSR request + VX_csr_req_if io_csr_req(); + wire temp_io_csr_req_valid = csr_io_req_valid & (csr_io_req_cid == CORE_ID[`NC_BITS-1:0]); + assign io_csr_req.valid = {`NUM_THREADS{temp_io_csr_req_valid}}; + assign io_csr_req.is_csr = 1'b1; + assign io_csr_req.csr_address = csr_io_req_addr; + assign io_csr_req.alu_op = csr_io_req_rw ? `ALU_CSR_RW : `ALU_CSR_RS; + assign io_csr_req.csr_mask = csr_io_req_rw ? csr_io_req_data : 32'b0; + + + + VX_wb_if io_csr_rsp(); + assign csr_io_req_ready = io_csr_rsp.is_io; + assign csr_io_rsp_valid = io_csr_rsp.valid[0]; + assign csr_io_rsp_data = io_csr_rsp.data[0]; +`IGNORE_WARNINGS_BEGIN + wire [4:0] unused_rd = io_csr_rsp.rd; + wire [1:0] unused_wb = io_csr_rsp.wb; + wire [31:0] unused_curr_PC = io_csr_rsp.curr_PC; +`IGNORE_WARNINGS_END + + + + // Dcache Interfaces VX_cache_dram_req_if #( .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), @@ -178,6 +213,11 @@ module VX_core #( .clk(clk), .reset(reset), + + // IO CSR + .io_csr_req (io_csr_req), + .io_csr_rsp (io_csr_rsp), + // Dcache core request .dcache_req_valid (core_dcache_req_if.core_req_valid), .dcache_req_rw (core_dcache_req_if.core_req_rw), diff --git a/hw/rtl/VX_csr_arbiter.v b/hw/rtl/VX_csr_arbiter.v new file mode 100644 index 00000000..214d4ebd --- /dev/null +++ b/hw/rtl/VX_csr_arbiter.v @@ -0,0 +1,64 @@ +`include "VX_define.vh" + +module VX_csr_arbiter ( + input wire clk, + input wire reset, + input wire csr_pipe_stall, + + VX_csr_req_if core_csr_req, + VX_csr_req_if io_csr_req, + + VX_csr_req_if issued_csr_req, + + VX_wb_if csr_pipe_rsp, + VX_wb_if csr_wb_if, + VX_wb_if csr_io_rsp + +); + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + + wire pick_core = (|core_csr_req.valid); + + // Which request to pick + assign issued_csr_req.is_io = !pick_core; + + // Mux between core and io + assign issued_csr_req.valid = pick_core ? core_csr_req.valid : io_csr_req.valid; + assign issued_csr_req.is_csr = pick_core ? core_csr_req.is_csr : io_csr_req.is_csr; + assign issued_csr_req.alu_op = pick_core ? core_csr_req.alu_op : io_csr_req.alu_op; + assign issued_csr_req.csr_address = pick_core ? core_csr_req.csr_address : io_csr_req.csr_address; + assign issued_csr_req.csr_mask = pick_core ? core_csr_req.csr_mask : io_csr_req.csr_mask; + + // Core arguments + assign issued_csr_req.warp_num = core_csr_req.warp_num; + assign issued_csr_req.rd = core_csr_req.rd; + assign issued_csr_req.wb = core_csr_req.wb; + + + + // Core Writeback + + assign csr_wb_if.valid = csr_pipe_rsp.valid & {`NUM_THREADS{~csr_pipe_rsp.is_io}}; + assign csr_wb_if.data = csr_pipe_rsp.data; + assign csr_wb_if.warp_num = csr_pipe_rsp.warp_num; + assign csr_wb_if.rd = csr_pipe_rsp.rd; + assign csr_wb_if.wb = csr_pipe_rsp.wb; + assign csr_wb_if.curr_PC = csr_pipe_rsp.curr_PC; + assign csr_wb_if.is_io = 1'b0; + + // CSR IO WB + + assign csr_io_rsp.valid = csr_pipe_rsp.valid & {`NUM_THREADS{csr_pipe_rsp.is_io}}; + assign csr_io_rsp.data = csr_pipe_rsp.data; + assign csr_io_rsp.warp_num = csr_pipe_rsp.warp_num; + assign csr_io_rsp.rd = csr_pipe_rsp.rd; + assign csr_io_rsp.wb = csr_pipe_rsp.wb; + assign csr_io_rsp.curr_PC = csr_pipe_rsp.curr_PC; + assign csr_io_rsp.is_io = !(csr_pipe_stall || pick_core); + + + +endmodule diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index c3ad37d3..dd80a811 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -55,14 +55,14 @@ module VX_csr_pipe #( end VX_generic_register #( - .N(32 + 32 + 12 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS) + .N(32 + 32 + 12 + 1 + 1 + 2 + 5 + (`NW_BITS-1+1) + `NUM_THREADS) ) csr_reg_s2 ( .clk (clk), .reset(reset), .stall(no_slot_csr), .flush(1'b0), - .in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_read_data , csr_updated_data }), - .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_read_data_s2, csr_updated_data_s2}) + .in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_req_if.is_io, csr_read_data , csr_updated_data }), + .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_wb_if.is_io , csr_read_data_s2, csr_updated_data_s2}) ); assign csr_wb_if.valid = valid_s2; diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 67c52a52..5c7c628d 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -30,6 +30,9 @@ module VX_gpr_stage ( wire is_jal = bckE_req_if.is_jal; `DEBUG_END + + assign csr_req_if.is_io = 1'b0; // GPR only issues csr requests coming from core + VX_gpr_read_if gpr_read_if(); assign gpr_read_if.rs1 = bckE_req_if.rs1; assign gpr_read_if.rs2 = bckE_req_if.rs2; @@ -171,6 +174,7 @@ module VX_gpr_stage ( .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask }) ); + `else // 341 @@ -220,4 +224,4 @@ module VX_gpr_stage ( `endif -endmodule : VX_gpr_stage \ No newline at end of file +endmodule : VX_gpr_stage diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 2a5271c9..1424e06c 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -12,6 +12,10 @@ module VX_pipeline #( input wire clk, input wire reset, + // IO CSR + VX_csr_req_if io_csr_req, + VX_wb_if io_csr_rsp, + // Dcache core request output wire [`NUM_THREADS-1:0] dcache_req_valid, output wire [`NUM_THREADS-1:0] dcache_req_rw, @@ -134,6 +138,8 @@ module VX_pipeline #( .clk (clk), .reset (reset), + .io_csr_req (io_csr_req), + .io_csr_rsp (io_csr_rsp), .schedule_delay (schedule_delay), .warp_ctl_if (warp_ctl_if), .bckE_req_if (bckE_req_if), @@ -191,4 +197,4 @@ module VX_pipeline #( end `endif -endmodule \ No newline at end of file +endmodule diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index 60f5f2c2..902f3833 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -15,6 +15,9 @@ interface VX_csr_req_if (); wire csr_immed; wire [31:0] csr_mask; +`IGNORE_WARNINGS_BEGIN + wire is_io; +`IGNORE_WARNINGS_END endinterface -`endif \ No newline at end of file +`endif diff --git a/hw/rtl/interfaces/VX_wb_if.v b/hw/rtl/interfaces/VX_wb_if.v index 0d17e4c4..c9e57085 100644 --- a/hw/rtl/interfaces/VX_wb_if.v +++ b/hw/rtl/interfaces/VX_wb_if.v @@ -12,6 +12,9 @@ interface VX_wb_if (); wire [1:0] wb; wire [31:0] curr_PC; +`IGNORE_WARNINGS_BEGIN + wire is_io; +`IGNORE_WARNINGS_END endinterface -`endif \ No newline at end of file +`endif From 2de61b59827b6fba10e1737203b2458570094b2e Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 30 Jun 2020 00:08:23 -0700 Subject: [PATCH 04/22] get device caps from CSRs --- driver/common/vx_utils.cpp | 32 +---- driver/include/vortex.h | 10 +- driver/opae/scope.cpp | 36 ++--- driver/opae/vortex.cpp | 230 +++++++++++++++++++++++--------- driver/rtlsim/vortex.cpp | 61 +++++++-- driver/simx/vortex.cpp | 61 +++++++-- driver/stub/vortex.cpp | 4 + driver/tests/basic/basic.cpp | 11 +- driver/tests/demo/demo.cpp | 15 ++- hw/opae/vortex_afu.json | 27 ++-- hw/opae/vortex_afu.sv | 249 ++++++++++++++++++++++------------- hw/rtl/VX_config.vh | 46 ++++--- hw/rtl/VX_csr_data.v | 27 ++-- 13 files changed, 534 insertions(+), 275 deletions(-) diff --git a/driver/common/vx_utils.cpp b/driver/common/vx_utils.cpp index d4fcf518..d7b8f829 100644 --- a/driver/common/vx_utils.cpp +++ b/driver/common/vx_utils.cpp @@ -4,31 +4,6 @@ #include #include -extern int vx_dev_caps(int caps_id) { - switch (caps_id) { - case VX_CAPS_VERSION: - return 0; - case VX_CAPS_MAX_CORES: - return NUM_CORES; - case VX_CAPS_MAX_WARPS: - return NUM_WARPS; - case VX_CAPS_MAX_THREADS: - return NUM_THREADS; - case VX_CAPS_CACHE_LINESIZE: - return 64; - case VX_CAPS_LOCAL_MEM_SIZE: - return 0xffffffff; - case VX_CAPS_ALLOC_BASE_ADDR: - return 0x10000000; - case VX_CAPS_KERNEL_BASE_ADDR: - return 0x80000000; - default: - std::cout << "invalid caps id: " << caps_id << std::endl; - std::abort(); - return 0; - } -} - extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_t size) { int err = 0; @@ -36,7 +11,10 @@ extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_ return -1; uint32_t buffer_transfer_size = 65536; - uint32_t kernel_base_addr = vx_dev_caps(VX_CAPS_KERNEL_BASE_ADDR); + unsigned kernel_base_addr; + err = vx_dev_caps(device, VX_CAPS_KERNEL_BASE_ADDR, &kernel_base_addr); + if (err != 0) + return -1; // allocate device buffer vx_buffer_h buffer; @@ -47,7 +25,7 @@ extern int vx_upload_kernel_bytes(vx_device_h device, const void* content, size_ // get buffer address auto buf_ptr = (uint8_t*)vx_host_ptr(buffer); - #if defined(USE_SIMX) +#if defined(USE_SIMX) // default startup routine ((uint32_t*)buf_ptr)[0] = 0xf1401073; ((uint32_t*)buf_ptr)[1] = 0xf1401073; diff --git a/driver/include/vortex.h b/driver/include/vortex.h index 2f379b11..ded648db 100644 --- a/driver/include/vortex.h +++ b/driver/include/vortex.h @@ -21,15 +21,15 @@ typedef void* vx_buffer_h; #define VX_CAPS_ALLOC_BASE_ADDR 0x6 #define VX_CAPS_KERNEL_BASE_ADDR 0x7 -// return device configurations -int vx_dev_caps(int caps_id); - // open the device and connect to it int vx_dev_open(vx_device_h* hdevice); // Close the device when all the operations are done int vx_dev_close(vx_device_h hdevice); +// return device configurations +int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value); + // Allocate shared buffer with device int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hbuffer); @@ -58,10 +58,10 @@ int vx_start(vx_device_h hdevice); int vx_ready_wait(vx_device_h hdevice, long long timeout); // set device constant registers -int vx_set_regiters(int state, int value); +int vx_csr_set(vx_device_h hdevice, int address, int value); // get device constant registers -int vx_get_regiters(int state, int* value); +int vx_csr_get(vx_device_h hdevice, int address, int* value); ////////////////////////////// UTILITY FUNCIONS /////////////////////////////// diff --git a/driver/opae/scope.cpp b/driver/opae/scope.cpp index 1f642659..6053d353 100644 --- a/driver/opae/scope.cpp +++ b/driver/opae/scope.cpp @@ -18,8 +18,8 @@ return -1; \ } while (false) -#define MMIO_CSR_SCOPE_CMD (AFU_IMAGE_MMIO_CSR_SCOPE_CMD * 4) -#define MMIO_CSR_SCOPE_DATA (AFU_IMAGE_MMIO_CSR_SCOPE_DATA * 4) +#define MMIO_SCOPE_READ (AFU_IMAGE_MMIO_SCOPE_READ * 4) +#define MMIO_SCOPE_WRITE (AFU_IMAGE_MMIO_SCOPE_WRITE * 4) struct scope_signal_t { int width; @@ -136,7 +136,7 @@ int vx_scope_start(fpga_handle hfpga, uint64_t delay) { if (delay != uint64_t(-1)) { // set start delay uint64_t cmd_delay = ((delay << 3) | 4); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, cmd_delay)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_delay)); std::cout << "scope start delay: " << delay << std::endl; } @@ -150,7 +150,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { if (delay != uint64_t(-1)) { // stop recording uint64_t cmd_stop = ((delay << 3) | 5); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, cmd_stop)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, cmd_stop)); std::cout << "scope stop delay: " << delay << std::endl; } @@ -170,9 +170,9 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { uint64_t frame_width, max_frames, data_valid; // wait for recording to terminate - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 0)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0)); do { - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); if (data_valid) break; std::this_thread::sleep_for(std::chrono::seconds(1)); @@ -180,15 +180,15 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { std::cout << "scope trace dump begin..." << std::endl; - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 2)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &frame_width)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 2)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &frame_width)); std::cout << "scope::frame_width=" << std::dec << frame_width << std::endl; - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 3)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &max_frames)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 3)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &max_frames)); std::cout << "scope::max_frames=" << std::dec << max_frames << std::endl; - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 1)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 1)); if (fwidth != (int)frame_width) { std::cerr << "invalid frame_width: expecting " << std::dec << fwidth << "!" << std::endl; @@ -209,7 +209,7 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { ofs << "b1 0" << std::endl; uint64_t delta; - fpga_result res = fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &delta); + fpga_result res = fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &delta); assert(res == FPGA_OK); while (delta != 0) { @@ -228,14 +228,14 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { do { if (frame_no == (max_frames-1)) { // verify last frame is valid - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 0)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); assert(data_valid == 1); - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 1)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 1)); } uint64_t word; - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &word)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &word)); do { int signal_width = scope_signals[signal_id-1].width; @@ -267,8 +267,8 @@ int vx_scope_stop(fpga_handle hfpga, uint64_t delay) { std::cout << "scope trace dump done! - " << (timestamp/2) << " cycles" << std::endl; // verify data not valid - CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_CSR_SCOPE_CMD, 0)); - CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_CSR_SCOPE_DATA, &data_valid)); + CHECK_RES(fpgaWriteMMIO64(hfpga, 0, MMIO_SCOPE_WRITE, 0)); + CHECK_RES(fpgaReadMMIO64(hfpga, 0, MMIO_SCOPE_READ, &data_valid)); assert(data_valid == 0); return 0; diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index ff020636..abb9c5b1 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -1,17 +1,24 @@ #include +#include #include #include +#include #include #include #include #include #include #include +#include #include "vortex_afu.h" #ifdef SCOPE #include "scope.h" #endif +#define CACHE_LINESIZE 64 +#define ALLOC_BASE_ADDR 0x10000000 +#define LOCAL_MEM_SIZE 0xffffffff + #define CHECK_RES(_expr) \ do { \ fpga_result res = _expr; \ @@ -24,22 +31,31 @@ /////////////////////////////////////////////////////////////////////////////// -#define CMD_TYPE_READ AFU_IMAGE_CMD_TYPE_READ -#define CMD_TYPE_WRITE AFU_IMAGE_CMD_TYPE_WRITE -#define CMD_TYPE_RUN AFU_IMAGE_CMD_TYPE_RUN -#define CMD_TYPE_CLFLUSH AFU_IMAGE_CMD_TYPE_CLFLUSH +#define CMD_MEM_READ AFU_IMAGE_CMD_MEM_READ +#define CMD_MEM_WRITE AFU_IMAGE_CMD_MEM_WRITE +#define CMD_RUN AFU_IMAGE_CMD_RUN +#define CMD_CLFLUSH AFU_IMAGE_CMD_CLFLUSH +#define CMD_CSR_READ AFU_IMAGE_CMD_CSR_READ +#define CMD_CSR_WRITE AFU_IMAGE_CMD_CSR_WRITE -#define MMIO_CSR_CMD (AFU_IMAGE_MMIO_CSR_CMD * 4) -#define MMIO_CSR_IO_ADDR (AFU_IMAGE_MMIO_CSR_IO_ADDR * 4) -#define MMIO_CSR_MEM_ADDR (AFU_IMAGE_MMIO_CSR_MEM_ADDR * 4) -#define MMIO_CSR_DATA_SIZE (AFU_IMAGE_MMIO_CSR_DATA_SIZE * 4) -#define MMIO_CSR_STATUS (AFU_IMAGE_MMIO_CSR_STATUS * 4) +#define MMIO_CMD_TYPE (AFU_IMAGE_MMIO_CMD_TYPE * 4) +#define MMIO_IO_ADDR (AFU_IMAGE_MMIO_IO_ADDR * 4) +#define MMIO_MEM_ADDR (AFU_IMAGE_MMIO_MEM_ADDR * 4) +#define MMIO_DATA_SIZE (AFU_IMAGE_MMIO_DATA_SIZE * 4) +#define MMIO_STATUS (AFU_IMAGE_MMIO_STATUS * 4) +#define MMIO_CSR_ADDR (AFU_IMAGE_MMIO_CSR_ADDR * 4) +#define MMIO_CSR_DATA (AFU_IMAGE_MMIO_CSR_DATA * 4) +#define MMIO_CSR_READ (AFU_IMAGE_MMIO_CSR_READ * 4) /////////////////////////////////////////////////////////////////////////////// typedef struct vx_device_ { fpga_handle fpga; size_t mem_allocation; + int implementation_id; + int num_cores; + int num_warps; + int num_threads; } vx_device_t; typedef struct vx_buffer_ { @@ -62,21 +78,58 @@ inline bool is_aligned(size_t addr, size_t alignment) { /////////////////////////////////////////////////////////////////////////////// +extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { + if (nullptr == hdevice) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + switch (caps_id) { + case VX_CAPS_VERSION: + *value = device->implementation_id; + break; + case VX_CAPS_MAX_CORES: + *value = device->num_cores; + break; + case VX_CAPS_MAX_WARPS: + *value = device->num_warps; + break; + case VX_CAPS_MAX_THREADS: + *value = device->num_threads; + break; + case VX_CAPS_CACHE_LINESIZE: + *value = CACHE_LINESIZE; + break; + case VX_CAPS_LOCAL_MEM_SIZE: + *value = LOCAL_MEM_SIZE; + break; + case VX_CAPS_ALLOC_BASE_ADDR: + *value = ALLOC_BASE_ADDR; + break; + case VX_CAPS_KERNEL_BASE_ADDR: + *value = STARTUP_ADDR; + break; + default: + fprintf(stderr, "invalid caps id: %d\n", caps_id); + std::abort(); + return -1; + } + + return 0; +} + extern int vx_dev_open(vx_device_h* hdevice) { + if (nullptr == hdevice) + return -1; + fpga_properties filter = nullptr; fpga_result res; fpga_guid guid; fpga_token accel_token; uint32_t num_matches; fpga_handle accel_handle; - vx_device_t* device; - - if (nullptr == hdevice) - return -1; - - // ensure that the block size 64 - assert(64 == vx_dev_caps(VX_CAPS_CACHE_LINESIZE)); - + vx_device_t* device; + // Set up a filter that will search for an accelerator fpgaGetProperties(nullptr, &filter); fpgaPropertiesSetObjectType(filter, FPGA_ACCELERATOR); @@ -114,17 +167,32 @@ extern int vx_dev_open(vx_device_h* hdevice) { } device->fpga = accel_handle; - device->mem_allocation = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); + device->mem_allocation = ALLOC_BASE_ADDR; - *hdevice = device; + { + // Load device CAPS + int ret = 0; + ret |= vx_csr_get(device, CSR_IMPL_ID, &device->implementation_id); + ret |= vx_csr_get(device, CSR_NC, &device->num_cores); + ret |= vx_csr_get(device, CSR_NW, &device->num_warps); + ret |= vx_csr_get(device, CSR_NT, &device->num_threads); + if (ret != 0) { + fpgaClose(accel_handle); + return ret; + } + } #ifdef SCOPE { - int ret = vx_scope_start(device->fpga, 0); - if (ret != 0) + int ret = vx_scope_start(accel_handle, 0); + if (ret != 0) { + fpgaClose(accel_handle); return ret; + } } -#endif +#endif + + *hdevice = device; return 0; } @@ -154,10 +222,8 @@ extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr) vx_device_t *device = ((vx_device_t*)hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - size_t dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); - - size_t asize = align_size(size, line_size); + size_t dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); if (device->mem_allocation + asize > dev_mem_size) return -1; @@ -182,9 +248,7 @@ extern int vx_alloc_shared_mem(vx_device_h hdevice, size_t size, vx_buffer_h* hb vx_device_t *device = ((vx_device_t*)hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - - size_t asize = align_size(size, line_size); + size_t asize = align_size(size, CACHE_LINESIZE); res = fpgaPrepareBuffer(device->fpga, asize, &host_ptr, &wsid, 0); if (FPGA_OK != res) { @@ -260,7 +324,7 @@ extern int vx_ready_wait(vx_device_h hdevice, long long timeout) { long long sleep_time_ms = (sleep_time.tv_sec * 1000) + (sleep_time.tv_nsec / 1000000); for (;;) { - CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_STATUS, &data)); + CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_STATUS, &data)); if (0 == data || 0 == timeout) { if (data != 0) { fprintf(stdout, "ready-wait timed out: status=%ld\n", data); @@ -282,17 +346,15 @@ extern int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, si vx_buffer_t *buffer = ((vx_buffer_t*)hbuffer); vx_device_t *device = ((vx_device_t*)buffer->hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - size_t dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); - - size_t asize = align_size(size, line_size); + size_t dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); // check alignment - if (!is_aligned(dev_maddr, line_size)) + if (!is_aligned(dev_maddr, CACHE_LINESIZE)) return -1; - if (!is_aligned(buffer->io_addr + src_offset, line_size)) + if (!is_aligned(buffer->io_addr + src_offset, CACHE_LINESIZE)) return -1; - + // bound checking if (src_offset + asize > buffer->size) return -1; @@ -303,12 +365,12 @@ extern int vx_copy_to_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, si if (vx_ready_wait(buffer->hdevice, -1) != 0) return -1; - auto ls_shift = (int)std::log2(line_size); + auto ls_shift = (int)std::log2(CACHE_LINESIZE); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_IO_ADDR, (buffer->io_addr + src_offset) >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_WRITE)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_IO_ADDR, (buffer->io_addr + src_offset) >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_MEM_WRITE)); // Wait for the write operation to finish if (vx_ready_wait(buffer->hdevice, -1) != 0) @@ -325,15 +387,13 @@ extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, vx_buffer_t *buffer = ((vx_buffer_t*)hbuffer); vx_device_t *device = ((vx_device_t*)buffer->hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - size_t dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); - - size_t asize = align_size(size, line_size); + size_t dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); // check alignment - if (!is_aligned(dev_maddr, line_size)) + if (!is_aligned(dev_maddr, CACHE_LINESIZE)) return -1; - if (!is_aligned(buffer->io_addr + dest_offset, line_size)) + if (!is_aligned(buffer->io_addr + dest_offset, CACHE_LINESIZE)) return -1; // bound checking @@ -346,12 +406,12 @@ extern int vx_copy_from_dev(vx_buffer_h hbuffer, size_t dev_maddr, size_t size, if (vx_ready_wait(buffer->hdevice, -1) != 0) return -1; - auto ls_shift = (int)std::log2(line_size); + auto ls_shift = (int)std::log2(CACHE_LINESIZE); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_IO_ADDR, (buffer->io_addr + dest_offset) >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_READ)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_IO_ADDR, (buffer->io_addr + dest_offset) >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_MEM_READ)); // Wait for the write operation to finish if (vx_ready_wait(buffer->hdevice, -1) != 0) @@ -367,23 +427,21 @@ extern int vx_flush_caches(vx_device_h hdevice, size_t dev_maddr, size_t size) { vx_device_t* device = ((vx_device_t*)hdevice); - int line_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - - size_t asize = align_size(size, line_size); + size_t asize = align_size(size, CACHE_LINESIZE); // check alignment - if (!is_aligned(dev_maddr, line_size)) + if (!is_aligned(dev_maddr, CACHE_LINESIZE)) return -1; // Ensure ready for new command if (vx_ready_wait(hdevice, -1) != 0) return -1; - auto ls_shift = (int)std::log2(line_size); + auto ls_shift = (int)std::log2(CACHE_LINESIZE); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_MEM_ADDR, dev_maddr >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA_SIZE, asize >> ls_shift)); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_CLFLUSH)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_MEM_ADDR, dev_maddr >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_DATA_SIZE, asize >> ls_shift)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CLFLUSH)); // Wait for the write operation to finish if (vx_ready_wait(hdevice, -1) != 0) @@ -396,13 +454,59 @@ extern int vx_start(vx_device_h hdevice) { if (nullptr == hdevice) return -1; + vx_device_t *device = ((vx_device_t*)hdevice); + // Ensure ready for new command if (vx_ready_wait(hdevice, -1) != 0) return -1; - // start execution + // start execution + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_RUN)); + + return 0; +} + +// set device constant registers +extern int vx_csr_set(vx_device_h hdevice, int address, int value) { + if (nullptr == hdevice) + return -1; + vx_device_t *device = ((vx_device_t*)hdevice); - CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CMD, CMD_TYPE_RUN)); + + // Ensure ready for new command + if (vx_ready_wait(hdevice, -1) != 0) + return -1; + + // write CSR value + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA, value)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_WRITE)); + + return 0; +} + +// get device constant registers +extern int vx_csr_get(vx_device_h hdevice, int address, int* value) { + if (nullptr == hdevice || nullptr == value) + return -1; + + vx_device_t *device = ((vx_device_t*)hdevice); + + // Ensure ready for new command + if (vx_ready_wait(hdevice, -1) != 0) + return -1; + + // write CSR value + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_READ)); + + // Ensure ready for new command + if (vx_ready_wait(hdevice, -1) != 0) + return -1; + + uint64_t value64; + CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_READ, &value64)); + *value = (int)value64; return 0; } \ No newline at end of file diff --git a/driver/rtlsim/vortex.cpp b/driver/rtlsim/vortex.cpp index 5550c821..51c3bb8c 100644 --- a/driver/rtlsim/vortex.cpp +++ b/driver/rtlsim/vortex.cpp @@ -7,14 +7,19 @@ #include #include +#include #include #include +#define CACHE_LINESIZE 64 +#define ALLOC_BASE_ADDR 0x10000000 +#define LOCAL_MEM_SIZE 0xffffffff + /////////////////////////////////////////////////////////////////////////////// -static size_t align_size(size_t size) { - uint32_t cache_block_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - return cache_block_size * ((size + cache_block_size - 1) / cache_block_size); +inline size_t align_size(size_t size, size_t alignment) { + assert(0 == (alignment & (alignment - 1))); + return (size + alignment - 1) & ~(alignment - 1); } /////////////////////////////////////////////////////////////////////////////// @@ -26,7 +31,7 @@ public: vx_buffer(size_t size, vx_device* device) : size_(size) , device_(device) { - auto aligned_asize = align_size(size); + auto aligned_asize = align_size(size, CACHE_LINESIZE); data_ = malloc(aligned_asize); } @@ -59,7 +64,7 @@ private: class vx_device { public: vx_device() { - mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); + mem_allocation_ = ALLOC_BASE_ADDR; simulator_.attach_ram(&ram_); } @@ -70,8 +75,8 @@ public: } int alloc_local_mem(size_t size, size_t* dev_maddr) { - size_t asize = align_size(size); - auto dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); + auto dev_mem_size = LOCAL_MEM_SIZE; + size_t asize = align_size(size, CACHE_LINESIZE); if (mem_allocation_ + asize > dev_mem_size) return -1; *dev_maddr = mem_allocation_; @@ -80,7 +85,7 @@ public: } int upload(void* src, size_t dest_addr, size_t size, size_t src_offset) { - size_t asize = align_size(size); + size_t asize = align_size(size, CACHE_LINESIZE); if (dest_addr + asize > ram_.size()) return -1; @@ -94,7 +99,7 @@ public: } int download(const void* dest, size_t src_addr, size_t size, size_t dest_offset) { - size_t asize = align_size(size); + size_t asize = align_size(size, CACHE_LINESIZE); if (src_addr + asize > ram_.size()) return -1; @@ -156,6 +161,44 @@ private: /////////////////////////////////////////////////////////////////////////////// +extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { + if (nullptr == hdevice) + return -1; + + switch (caps_id) { + case VX_CAPS_VERSION: + *value = IMPLEMENTATION_ID; + break; + case VX_CAPS_MAX_CORES: + *value = NUM_CORES; + break; + case VX_CAPS_MAX_WARPS: + *value = NUM_WARPS; + break; + case VX_CAPS_MAX_THREADS: + *value = NUM_THREADS; + break; + case VX_CAPS_CACHE_LINESIZE: + *value = CACHE_LINESIZE; + break; + case VX_CAPS_LOCAL_MEM_SIZE: + *value = 0xffffffff; + break; + case VX_CAPS_ALLOC_BASE_ADDR: + *value = 0x10000000; + break; + case VX_CAPS_KERNEL_BASE_ADDR: + *value = STARTUP_ADDR; + break; + default: + std::cout << "invalid caps id: " << caps_id << std::endl; + std::abort(); + return -1; + } + + return 0; +} + extern int vx_dev_open(vx_device_h* hdevice) { if (nullptr == hdevice) return -1; diff --git a/driver/simx/vortex.cpp b/driver/simx/vortex.cpp index 394e1db2..981ca5c1 100644 --- a/driver/simx/vortex.cpp +++ b/driver/simx/vortex.cpp @@ -11,13 +11,16 @@ #include #include -#define PAGE_SIZE 4096 +#define CACHE_LINESIZE 64 +#define PAGE_SIZE 4096 +#define ALLOC_BASE_ADDR 0x10000000 +#define LOCAL_MEM_SIZE 0xffffffff /////////////////////////////////////////////////////////////////////////////// -static size_t align_size(size_t size) { - uint32_t cache_block_size = vx_dev_caps(VX_CAPS_CACHE_LINESIZE); - return cache_block_size * ((size + cache_block_size - 1) / cache_block_size); +inline size_t align_size(size_t size, size_t alignment) { + assert(0 == (alignment & (alignment - 1))); + return (size + alignment - 1) & ~(alignment - 1); } /////////////////////////////////////////////////////////////////////////////// @@ -29,7 +32,7 @@ public: vx_buffer(size_t size, vx_device* device) : size_(size) , device_(device) { - auto aligned_asize = align_size(size); + auto aligned_asize = align_size(size, CACHE_LINESIZE); data_ = malloc(aligned_asize); } @@ -65,7 +68,7 @@ public: : is_done_(false) , is_running_(false) , thread_(__thread_proc__, this) { - mem_allocation_ = vx_dev_caps(VX_CAPS_ALLOC_BASE_ADDR); + mem_allocation_ = ALLOC_BASE_ADDR; } ~vx_device() { @@ -77,8 +80,8 @@ public: } int alloc_local_mem(size_t size, size_t* dev_maddr) { - auto asize = align_size(size); - auto dev_mem_size = vx_dev_caps(VX_CAPS_LOCAL_MEM_SIZE); + auto dev_mem_size = LOCAL_MEM_SIZE; + auto asize = align_size(size, CACHE_LINESIZE); if (mem_allocation_ + asize > dev_mem_size) return -1; *dev_maddr = mem_allocation_; @@ -87,7 +90,7 @@ public: } int upload(void* src, size_t dest_addr, size_t size, size_t src_offset) { - auto asize = align_size(size); + auto asize = align_size(size, CACHE_LINESIZE); if (dest_addr + asize > ram_.size()) return -1; @@ -101,7 +104,7 @@ public: } int download(const void* dest, size_t src_addr, size_t size, size_t dest_offset) { - size_t asize = align_size(size); + size_t asize = align_size(size, CACHE_LINESIZE); if (src_addr + asize > ram_.size()) return -1; @@ -216,6 +219,44 @@ extern int vx_dev_close(vx_device_h hdevice) { return 0; } +extern int vx_dev_caps(vx_device_h hdevice, unsigned caps_id, unsigned *value) { + if (nullptr == hdevice) + return -1; + + switch (caps_id) { + case VX_CAPS_VERSION: + *value = IMPLEMENTATION_ID; + break; + case VX_CAPS_MAX_CORES: + *value = NUM_CORES; + break; + case VX_CAPS_MAX_WARPS: + *value = NUM_WARPS; + break; + case VX_CAPS_MAX_THREADS: + *value = NUM_THREADS; + break; + case VX_CAPS_CACHE_LINESIZE: + *value = CACHE_LINESIZE; + break; + case VX_CAPS_LOCAL_MEM_SIZE: + *value = LOCAL_MEM_SIZE; + break; + case VX_CAPS_ALLOC_BASE_ADDR: + *value = ALLOC_BASE_ADDR; + break; + case VX_CAPS_KERNEL_BASE_ADDR: + *value = STARTUP_ADDR; + break; + default: + std::cout << "invalid caps id: " << caps_id << std::endl; + std::abort(); + return -1; + } + + return 0; +} + extern int vx_alloc_dev_mem(vx_device_h hdevice, size_t size, size_t* dev_maddr) { if (nullptr == hdevice || nullptr == dev_maddr diff --git a/driver/stub/vortex.cpp b/driver/stub/vortex.cpp index 13f09ae5..532e64d7 100644 --- a/driver/stub/vortex.cpp +++ b/driver/stub/vortex.cpp @@ -8,6 +8,10 @@ extern int vx_dev_close(vx_device_h /*hdevice*/) { return -1; } +extern int vx_dev_caps(vx_device_h /*hdevice*/, unsigned /*caps_id*/, unsigned* /*value*/) { + return -1; +} + extern int vx_alloc_dev_mem(vx_device_h /*hdevice*/, size_t /*size*/, size_t* /*dev_maddr*/) { return -1; } diff --git a/driver/tests/basic/basic.cpp b/driver/tests/basic/basic.cpp index 7301e12d..92a785f4 100755 --- a/driver/tests/basic/basic.cpp +++ b/driver/tests/basic/basic.cpp @@ -179,7 +179,12 @@ int main(int argc, char *argv[]) { count = 1; } - uint32_t max_cores = vx_dev_caps(VX_CAPS_MAX_CORES); + // open device connection + std::cout << "open device connection" << std::endl; + RT_CHECK(vx_dev_open(&device)); + + unsigned max_cores; + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_CORES, &max_cores)); uint32_t num_points = max_cores * count; uint32_t num_blocks = (num_points * sizeof(uint32_t) + 63) / 64; uint32_t buf_size = num_blocks * 64; @@ -187,10 +192,6 @@ int main(int argc, char *argv[]) { std::cout << "number of points: " << num_points << std::endl; std::cout << "buffer size: " << buf_size << " bytes" << std::endl; - // open device connection - std::cout << "open device connection" << std::endl; - RT_CHECK(vx_dev_open(&device)); - // allocate device memory RT_CHECK(vx_alloc_dev_mem(device, buf_size, &value)); kernel_arg.src_ptr = value; diff --git a/driver/tests/demo/demo.cpp b/driver/tests/demo/demo.cpp index 71f42e0b..2d5b47f8 100644 --- a/driver/tests/demo/demo.cpp +++ b/driver/tests/demo/demo.cpp @@ -110,9 +110,14 @@ int main(int argc, char *argv[]) { count = 1; } - uint32_t max_cores = vx_dev_caps(VX_CAPS_MAX_CORES); - uint32_t max_warps = vx_dev_caps(VX_CAPS_MAX_WARPS); - uint32_t max_threads = vx_dev_caps(VX_CAPS_MAX_THREADS); + // open device connection + std::cout << "open device connection" << std::endl; + RT_CHECK(vx_dev_open(&device)); + + unsigned max_cores, max_warps, max_threads; + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_CORES, &max_cores)); + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_WARPS, &max_warps)); + RT_CHECK(vx_dev_caps(device, VX_CAPS_MAX_THREADS, &max_threads)); uint32_t num_points = count * max_cores * max_warps * max_threads; uint32_t buf_size = num_points * sizeof(uint32_t); @@ -120,10 +125,6 @@ int main(int argc, char *argv[]) { std::cout << "number of points: " << num_points << std::endl; std::cout << "buffer size: " << buf_size << " bytes" << std::endl; - // open device connection - std::cout << "open device connection" << std::endl; - RT_CHECK(vx_dev_open(&device)); - // upload program std::cout << "upload program" << std::endl; RT_CHECK(vx_upload_kernel_file(device, kernel_file)); diff --git a/hw/opae/vortex_afu.json b/hw/opae/vortex_afu.json index 98dcecfd..f198383c 100644 --- a/hw/opae/vortex_afu.json +++ b/hw/opae/vortex_afu.json @@ -5,18 +5,23 @@ "clock-frequency-high": "auto", "clock-frequency-low": "auto", - "mmio-csr-cmd": 10, - "mmio-csr-io-addr": 12, - "mmio-csr-mem-addr": 14, - "mmio-csr-data-size": 16, - "mmio-csr-status": 18, - "mmio-csr-scope-cmd": 20, - "mmio-csr-scope-data": 22, + "cmd-mem-read": 1, + "cmd-mem-write": 2, + "cmd-run": 3, + "cmd-clflush": 4, + "cmd-csr-read": 5, + "cmd-csr-write": 6, - "cmd-type-read": 1, - "cmd-type-write": 2, - "cmd-type-run": 3, - "cmd-type-clflush": 4, + "mmio-cmd-type": 10, + "mmio-io-addr": 12, + "mmio-mem-addr": 14, + "mmio-data-size": 16, + "mmio-status": 18, + "mmio-scope-read": 20, + "mmio-scope-write": 22, + "mmio-csr-addr": 24, + "mmio-csr-data": 26, + "mmio-csr-read": 28, "afu-top-interface": { diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 0650c0ac..2216611e 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -53,19 +53,25 @@ localparam CCI_RW_QUEUE_SIZE = 1024; localparam AFU_ID_L = 16'h0002; // AFU ID Lower localparam AFU_ID_H = 16'h0004; // AFU ID Higher -localparam CMD_TYPE_READ = `AFU_IMAGE_CMD_TYPE_READ; -localparam CMD_TYPE_WRITE = `AFU_IMAGE_CMD_TYPE_WRITE; -localparam CMD_TYPE_RUN = `AFU_IMAGE_CMD_TYPE_RUN; -localparam CMD_TYPE_CLFLUSH = `AFU_IMAGE_CMD_TYPE_CLFLUSH; +localparam CMD_MEM_READ = `AFU_IMAGE_CMD_MEM_READ; +localparam CMD_MEM_WRITE = `AFU_IMAGE_CMD_MEM_WRITE; +localparam CMD_RUN = `AFU_IMAGE_CMD_RUN; +localparam CMD_CLFLUSH = `AFU_IMAGE_CMD_CLFLUSH; +localparam CMD_CSR_READ = `AFU_IMAGE_CMD_CSR_READ; +localparam CMD_CSR_WRITE = `AFU_IMAGE_CMD_CSR_WRITE; -localparam MMIO_CSR_CMD = `AFU_IMAGE_MMIO_CSR_CMD; -localparam MMIO_CSR_IO_ADDR = `AFU_IMAGE_MMIO_CSR_IO_ADDR; -localparam MMIO_CSR_MEM_ADDR = `AFU_IMAGE_MMIO_CSR_MEM_ADDR; -localparam MMIO_CSR_DATA_SIZE = `AFU_IMAGE_MMIO_CSR_DATA_SIZE; -localparam MMIO_CSR_STATUS = `AFU_IMAGE_MMIO_CSR_STATUS; +localparam MMIO_CMD_TYPE = `AFU_IMAGE_MMIO_CMD_TYPE; +localparam MMIO_IO_ADDR = `AFU_IMAGE_MMIO_IO_ADDR; +localparam MMIO_MEM_ADDR = `AFU_IMAGE_MMIO_MEM_ADDR; +localparam MMIO_DATA_SIZE = `AFU_IMAGE_MMIO_DATA_SIZE; +localparam MMIO_STATUS = `AFU_IMAGE_MMIO_STATUS; -localparam MMIO_CSR_SCOPE_CMD = `AFU_IMAGE_MMIO_CSR_SCOPE_CMD; -localparam MMIO_CSR_SCOPE_DATA= `AFU_IMAGE_MMIO_CSR_SCOPE_DATA; +localparam MMIO_SCOPE_READ = `AFU_IMAGE_MMIO_SCOPE_READ; +localparam MMIO_SCOPE_WRITE = `AFU_IMAGE_MMIO_SCOPE_WRITE; + +localparam MMIO_CSR_ADDR = `AFU_IMAGE_MMIO_CSR_ADDR; +localparam MMIO_CSR_DATA = `AFU_IMAGE_MMIO_CSR_DATA; +localparam MMIO_CSR_READ = `AFU_IMAGE_MMIO_CSR_READ; logic [127:0] afu_id = `AFU_ACCEL_UUID; @@ -75,7 +81,9 @@ typedef enum logic[3:0] { STATE_WRITE, STATE_START, STATE_RUN, - STATE_CLFLUSH + STATE_CLFLUSH, + STATE_CSR_READ, + STATE_CSR_WRITE } state_t; typedef logic [$clog2(CCI_RD_WINDOW_SIZE)-1:0] t_cci_rdq_tag; @@ -134,20 +142,24 @@ logic avs_rdq_empty; logic avs_rdq_full; `DEBUG_END -// CSR variables ////////////////////////////////////////////////////////////// +// CMD variables ////////////////////////////////////////////////////////////// -logic [2:0] csr_cmd; -t_ccip_clAddr csr_io_addr; -logic[DRAM_ADDR_WIDTH-1:0] csr_mem_addr; -logic[DRAM_ADDR_WIDTH-1:0] csr_data_size; +logic [2:0] cmd_type; +t_ccip_clAddr cmd_io_addr; +logic[DRAM_ADDR_WIDTH-1:0] cmd_mem_addr; +logic[DRAM_ADDR_WIDTH-1:0] cmd_data_size; `ifdef SCOPE -logic [63:0] csr_scope_cmd; -logic [63:0] csr_scope_data; -logic csr_scope_read; -logic csr_scope_write; +logic [63:0] cmd_scope_rdata; +logic [63:0] cmd_scope_wdata; +logic cmd_scope_read; +logic cmd_scope_write; `endif +logic [31:0] cmd_csr_addr; +logic [31:0] cmd_csr_rdata; +logic [31:0] cmd_csr_wdata; + // MMIO controller //////////////////////////////////////////////////////////// `IGNORE_WARNINGS_BEGIN @@ -159,9 +171,9 @@ t_if_ccip_c2_Tx mmio_tx; assign af2cp_sTxPort.c2 = mmio_tx; `ifdef SCOPE -assign csr_scope_cmd = 64'(cp2af_sRxPort.c0.data); -assign csr_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_CSR_SCOPE_CMD == mmio_hdr.address); -assign csr_scope_read = cp2af_sRxPort.c0.mmioRdValid && (MMIO_CSR_SCOPE_DATA == mmio_hdr.address); +assign cmd_scope_wdata = 64'(cp2af_sRxPort.c0.data); +assign cmd_scope_read = cp2af_sRxPort.c0.mmioRdValid && (MMIO_SCOPE_READ == mmio_hdr.address); +assign cmd_scope_write = cp2af_sRxPort.c0.mmioWrValid && (MMIO_SCOPE_WRITE == mmio_hdr.address); `endif always_ff @(posedge clk) @@ -170,57 +182,63 @@ begin mmio_tx.hdr <= 0; mmio_tx.data <= 0; mmio_tx.mmioRdValid <= 0; - csr_cmd <= 0; - csr_io_addr <= 0; - csr_mem_addr <= 0; - csr_data_size <= 0; + cmd_type <= 0; + cmd_io_addr <= 0; + cmd_mem_addr <= 0; + cmd_data_size <= 0; end else begin - csr_cmd <= 0; + cmd_type <= 0; mmio_tx.mmioRdValid <= 0; // serve MMIO write request if (cp2af_sRxPort.c0.mmioWrValid) begin case (mmio_hdr.address) - MMIO_CSR_IO_ADDR: begin - csr_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); + MMIO_IO_ADDR: begin + cmd_io_addr <= t_ccip_clAddr'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_IO_ADDR: 0x%0h", $time, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_IO_ADDR: 0x%0h", $time, t_ccip_clAddr'(cp2af_sRxPort.c0.data)); `endif end - MMIO_CSR_MEM_ADDR: begin - csr_mem_addr <= t_local_mem_addr'(cp2af_sRxPort.c0.data); + MMIO_MEM_ADDR: begin + cmd_mem_addr <= t_local_mem_addr'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_MEM_ADDR: 0x%0h", $time, t_local_mem_addr'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_MEM_ADDR: 0x%0h", $time, t_local_mem_addr'(cp2af_sRxPort.c0.data)); `endif end - MMIO_CSR_DATA_SIZE: begin - csr_data_size <= $bits(csr_data_size)'(cp2af_sRxPort.c0.data); + MMIO_DATA_SIZE: begin + cmd_data_size <= $bits(cmd_data_size)'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_DATA_SIZE: %0d", $time, $bits(csr_data_size)'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_DATA_SIZE: %0d", $time, $bits(cmd_data_size)'(cp2af_sRxPort.c0.data)); `endif end - MMIO_CSR_CMD: begin - csr_cmd <= $bits(csr_cmd)'(cp2af_sRxPort.c0.data); + MMIO_CMD_TYPE: begin + cmd_type <= $bits(cmd_type)'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE - $display("%t: CSR_CMD: %0d", $time, $bits(csr_cmd)'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_CMD_TYPE: %0d", $time, $bits(cmd_type)'(cp2af_sRxPort.c0.data)); `endif end `ifdef SCOPE - MMIO_CSR_SCOPE_CMD: begin + MMIO_SCOPE_WRITE: begin `ifdef DBG_PRINT_OPAE - $display("%t: CSR_SCOPE_CMD: %0h", $time, 64'(cp2af_sRxPort.c0.data)); + $display("%t: MMIO_SCOPE_WRITE: %0h", $time, 64'(cp2af_sRxPort.c0.data)); `endif end `endif - default: begin - // user-defined CSRs - //if (mmio_hdr.addres >= MMIO_CSR_USER) begin - // write Vortex CRS - //end - end + MMIO_CSR_ADDR: begin + cmd_csr_addr <= $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data); + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_ADDR: %0h", $time, $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data)); + `endif + end + MMIO_CSR_DATA: begin + cmd_csr_wdata <= $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data); + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_DATA: %0h", $time, $bits(cmd_csr_wdata)'(cp2af_sRxPort.c0.data)); + `endif + end endcase end @@ -243,22 +261,28 @@ begin AFU_ID_H: mmio_tx.data <= afu_id[127:64]; // afu id hi 16'h0006: mmio_tx.data <= 64'h0; // next AFU 16'h0008: mmio_tx.data <= 64'h0; // reserved - MMIO_CSR_STATUS: begin + MMIO_STATUS: begin `ifdef DBG_PRINT_OPAE if (state != state_t'(mmio_tx.data)) begin - $display("%t: STATUS: state=%0d", $time, state); + $display("%t: MMIO_STATUS: state=%0d", $time, state); end `endif mmio_tx.data <= 64'(state); end `ifdef SCOPE - MMIO_CSR_SCOPE_DATA: begin - mmio_tx.data <= csr_scope_data; + MMIO_SCOPE_READ: begin + mmio_tx.data <= cmd_scope_rdata; `ifdef DBG_PRINT_OPAE - $display("%t: SCOPE: data=%0h", $time, csr_scope_data); + $display("%t: MMIO_SCOPE_READ: data=%0h", $time, cmd_scope_rdata); `endif end `endif + MMIO_CSR_READ: begin + mmio_tx.data <= cmd_csr_rdata; + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_READ: data=%0h", $time, cmd_csr_rdata); + `endif + end default: mmio_tx.data <= 64'h0; endcase mmio_tx.mmioRdValid <= 1; // post response @@ -271,6 +295,8 @@ end logic cmd_read_done; logic cmd_write_done; logic cmd_clflush_done; +logic cmd_csr_read_done; +logic cmd_csr_write_done; logic cmd_run_done; always_ff @(posedge clk) @@ -285,32 +311,44 @@ begin case (state) STATE_IDLE: begin - case (csr_cmd) - CMD_TYPE_READ: begin + case (cmd_type) + CMD_MEM_READ: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE READ: ia=%0h da=%0h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size); + $display("%t: STATE READ: ia=%0h addr=%0h size=%0d", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_READ; end - CMD_TYPE_WRITE: begin + CMD_MEM_WRITE: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE WRITE: ia=%0h da=%0h sz=%0d", $time, csr_io_addr, csr_mem_addr, csr_data_size); + $display("%t: STATE WRITE: ia=%0h addr=%0h size=%0d", $time, cmd_io_addr, cmd_mem_addr, cmd_data_size); `endif state <= STATE_WRITE; end - CMD_TYPE_RUN: begin + CMD_RUN: begin `ifdef DBG_PRINT_OPAE $display("%t: STATE START", $time); `endif vx_reset <= 1; state <= STATE_START; end - CMD_TYPE_CLFLUSH: begin + CMD_CLFLUSH: begin `ifdef DBG_PRINT_OPAE - $display("%t: STATE CFLUSH: da=%0h sz=%0d", $time, csr_mem_addr, csr_data_size); + $display("%t: STATE CFLUSH: addr=%0h size=%0d", $time, cmd_mem_addr, cmd_data_size); `endif state <= STATE_CLFLUSH; end + CMD_CSR_READ: begin + `ifdef DBG_PRINT_OPAE + $display("%t: STATE CSR_READ: addr=%0h", $time, cmd_csr_addr); + `endif + state <= STATE_CSR_READ; + end + CMD_CSR_WRITE: begin + `ifdef DBG_PRINT_OPAE + $display("%t: STATE CSR_WRITE: addr=%0h data=%0d", $time, cmd_csr_addr, cmd_csr_wdata); + `endif + state <= STATE_CSR_WRITE; + end default: begin state <= state; end @@ -345,6 +383,18 @@ begin end end + STATE_CSR_READ: begin + if (cmd_csr_read_done) begin + state <= STATE_IDLE; + end + end + + STATE_CSR_WRITE: begin + if (cmd_csr_write_done) begin + state <= STATE_IDLE; + end + end + default: begin state <= state; end @@ -385,7 +435,7 @@ assign cci_dram_rd_req_enable = (state == STATE_READ) assign cci_dram_wr_req_enable = (state == STATE_WRITE) && !cci_rdq_empty - && (cci_dram_wr_req_ctr < csr_data_size); + && (cci_dram_wr_req_ctr < cmd_data_size); assign vx_dram_req_enable = vortex_enabled && (avs_pending_reads < AVS_RD_QUEUE_SIZE); assign vx_dram_rd_req_enable = vx_dram_req_enable && vx_dram_req_valid && !vx_dram_req_rw; @@ -414,19 +464,19 @@ end always_comb begin case (state) - CMD_TYPE_READ: avs_address = cci_dram_rd_req_addr; - CMD_TYPE_WRITE: avs_address = cci_dram_wr_req_addr + ((DRAM_ADDR_WIDTH)'(t_cci_rdq_tag'(cci_rdq_dout))); + CMD_MEM_READ: avs_address = cci_dram_rd_req_addr; + CMD_MEM_WRITE: avs_address = cci_dram_wr_req_addr + ((DRAM_ADDR_WIDTH)'(t_cci_rdq_tag'(cci_rdq_dout))); default: avs_address = vx_dram_req_addr[`VX_DRAM_ADDR_WIDTH-1:`VX_DRAM_ADDR_WIDTH-DRAM_ADDR_WIDTH]; endcase case (state) - CMD_TYPE_READ: avs_byteenable = 64'hffffffffffffffff; - CMD_TYPE_WRITE: avs_byteenable = 64'hffffffffffffffff; + CMD_MEM_READ: avs_byteenable = 64'hffffffffffffffff; + CMD_MEM_WRITE: avs_byteenable = 64'hffffffffffffffff; default: avs_byteenable = vx_dram_req_byteen_; endcase case (state) - CMD_TYPE_WRITE: avs_writedata = cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)]; + CMD_MEM_WRITE: avs_writedata = cci_rdq_dout[$bits(t_ccip_clData) + $bits(t_cci_rdq_tag)-1:$bits(t_cci_rdq_tag)]; default: avs_writedata = (DRAM_LINE_WIDTH)'(vx_dram_req_data) << vx_dram_req_offset; endcase end @@ -434,7 +484,7 @@ end assign avs_read = cci_dram_rd_req_enable || vx_dram_rd_req_enable; assign avs_write = cci_dram_wr_req_enable || vx_dram_wr_req_enable; -assign cmd_write_done = (cci_dram_wr_req_ctr >= csr_data_size); +assign cmd_write_done = (cci_dram_wr_req_ctr >= cmd_data_size); always_ff @(posedge clk) begin @@ -451,12 +501,12 @@ begin else begin if (state == STATE_IDLE) begin - if (CMD_TYPE_READ == csr_cmd) begin - cci_dram_rd_req_addr <= csr_mem_addr; - cci_dram_rd_req_ctr <= csr_data_size; + if (CMD_MEM_READ == cmd_type) begin + cci_dram_rd_req_addr <= cmd_mem_addr; + cci_dram_rd_req_ctr <= cmd_data_size; end - else if (CMD_TYPE_WRITE == csr_cmd) begin - cci_dram_wr_req_addr <= csr_mem_addr; + else if (CMD_MEM_WRITE == cmd_type) begin + cci_dram_wr_req_addr <= cmd_mem_addr; cci_dram_wr_req_ctr <= 0; end end @@ -598,17 +648,17 @@ begin else begin if ((STATE_IDLE == state) - && (CMD_TYPE_WRITE == csr_cmd)) begin - cci_rd_req_addr <= csr_io_addr; + && (CMD_MEM_WRITE == cmd_type)) begin + cci_rd_req_addr <= cmd_io_addr; cci_rd_req_ctr <= 0; cci_rd_rsp_ctr <= 0; cci_pending_reads <= 0; - cci_rd_req_enable <= (csr_data_size != 0); + cci_rd_req_enable <= (cmd_data_size != 0); cci_rd_req_wait <= 0; end cci_rd_req_enable <= (STATE_WRITE == state) - && (cci_rd_req_ctr_next < csr_data_size) + && (cci_rd_req_ctr_next < cmd_data_size) && (cci_pending_reads_next < CCI_RD_QUEUE_SIZE); if (cci_rd_req_fire) begin @@ -618,7 +668,7 @@ begin cci_rd_req_wait <= 1; // end current request batch end `ifdef DBG_PRINT_OPAE - $display("%t: CCI Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, (csr_data_size - cci_rd_req_ctr_next), cci_pending_reads_next); + $display("%t: CCI Rd Req: addr=%0h, rem=%0d, pending=%0d", $time, cci_rd_req_addr, (cmd_data_size - cci_rd_req_ctr_next), cci_pending_reads_next); `endif end @@ -695,9 +745,9 @@ begin else begin if ((STATE_IDLE == state) - && (CMD_TYPE_READ == csr_cmd)) begin - cci_wr_req_addr <= csr_io_addr; - cci_wr_req_ctr <= csr_data_size; + && (CMD_MEM_READ == cmd_type)) begin + cci_wr_req_addr <= cmd_io_addr; + cci_wr_req_ctr <= cmd_data_size; cci_pending_writes <= 0; end @@ -733,11 +783,11 @@ logic [`VX_DRAM_ADDR_WIDTH-1:0] snp_rsp_ctr, snp_rsp_ctr_next; logic vx_snp_req_fire, vx_snp_rsp_fire; if (`VX_DRAM_LINE_WIDTH != DRAM_LINE_WIDTH) begin - assign snp_req_baseaddr = {csr_mem_addr, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; - assign snp_req_size = {csr_data_size, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; + assign snp_req_baseaddr = {cmd_mem_addr, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; + assign snp_req_size = {cmd_data_size, (`VX_DRAM_ADDR_WIDTH - DRAM_ADDR_WIDTH)'(0)}; end else begin - assign snp_req_baseaddr = csr_mem_addr; - assign snp_req_size = csr_data_size; + assign snp_req_baseaddr = cmd_mem_addr; + assign snp_req_size = cmd_data_size; end assign vx_snp_req_fire = vx_snp_req_valid && vx_snp_req_ready; @@ -761,7 +811,7 @@ begin else begin if ((STATE_IDLE == state) - && (CMD_TYPE_CLFLUSH == csr_cmd)) begin + && (CMD_CLFLUSH == cmd_type)) begin vx_snp_req_addr <= snp_req_baseaddr; vx_snp_req_tag <= 0; snp_req_ctr <= 0; @@ -802,6 +852,23 @@ begin end end +// CSRs/////////////////////////////////////////////////////////////////////// + +assign cmd_csr_read_done = 1; +assign cmd_csr_write_done = 1; + +always_comb begin + case (cmd_csr_addr) + `CSR_VEND_ID : cmd_csr_rdata = `VENDOR_ID; + `CSR_ARCH_ID : cmd_csr_rdata = `ARCHITECTURE_ID; + `CSR_IMPL_ID : cmd_csr_rdata = `IMPLEMENTATION_ID; + `CSR_NT : cmd_csr_rdata = `NUM_THREADS; + `CSR_NW : cmd_csr_rdata = `NUM_WARPS; + `CSR_NC : cmd_csr_rdata = `NUM_CORES * `NUM_CLUSTERS; + default : cmd_csr_rdata = 0; + endcase +end + // Vortex ///////////////////////////////////////////////////////////////////// assign cmd_run_done = !vx_busy; @@ -944,10 +1011,10 @@ VX_scope #( .stop (0), .changed (scope_data_in_ste[1]), .data_in (scope_data_in_ste[SCOPE_DATAW+1:2]), - .bus_in (csr_scope_cmd), - .bus_out (csr_scope_data), - .bus_read (csr_scope_read), - .bus_write(csr_scope_write) + .bus_in (cmd_scope_wdata), + .bus_out (cmd_scope_rdata), + .bus_read (cmd_scope_read), + .bus_write(cmd_scope_write) ); `endif diff --git a/hw/rtl/VX_config.vh b/hw/rtl/VX_config.vh index 4f6377a0..6a5f7386 100644 --- a/hw/rtl/VX_config.vh +++ b/hw/rtl/VX_config.vh @@ -59,21 +59,33 @@ `define L3_ENABLE (`NUM_CLUSTERS > 1) `endif -`define CSR_LTID 12'h020 -`define CSR_LWID 12'h021 -`define CSR_GTID 12'hF14 // reserved Hardware Thread ID (mhartid) -`define CSR_GWID 12'h023 -`define CSR_GCID 12'h024 -`define CSR_NT 12'h025 -`define CSR_NW 12'h026 -`define CSR_NC 12'h027 +// Configuration Values ======================================================= -`define CSR_CYCLL 12'hC00 -`define CSR_CYCLH 12'hC80 -`define CSR_INSTL 12'hC02 -`define CSR_INSTH 12'hC82 +`define VENDOR_ID 0 +`define ARCHITECTURE_ID 0 +`define IMPLEMENTATION_ID 0 -// ========================= Dcache Configurable Knobs ======================== +// CSR Addresses ============================================================== + +`define CSR_VEND_ID 12'hF11 +`define CSR_ARCH_ID 12'hF12 +`define CSR_IMPL_ID 12'hF13 +`define CSR_GTID 12'hF14 + +`define CSR_LTID 12'h020 +`define CSR_LWID 12'h021 +`define CSR_GWID 12'h023 +`define CSR_GCID 12'h024 +`define CSR_NT 12'h025 +`define CSR_NW 12'h026 +`define CSR_NC 12'h027 + +`define CSR_CYCLE_L 12'hC00 +`define CSR_CYCLE_H 12'hC80 +`define CSR_INSTR_L 12'hC02 +`define CSR_INSTR_H 12'hC82 + +// Dcache Configurable Knobs ================================================== // Size of cache in bytes `ifndef DCACHE_SIZE @@ -144,7 +156,7 @@ `define DPRFQ_STRIDE 0 `endif -// ========================== Icache Configurable Knobs ======================= +// Icache Configurable Knobs ================================================== // Size of cache in bytes `ifndef ICACHE_SIZE @@ -210,7 +222,7 @@ `define IPRFQ_STRIDE 0 `endif -// =========================== SM Configurable Knobs ========================== +// SM Configurable Knobs ====================================================== // Size of cache in bytes `ifndef SCACHE_SIZE @@ -247,7 +259,7 @@ `define SCWBQ_SIZE `SCREQ_SIZE `endif -// ======================== L2cache Configurable Knobs ======================== +// L2cache Configurable Knobs ================================================= // Size of cache in bytes `ifndef L2CACHE_SIZE @@ -318,7 +330,7 @@ `define L2PRFQ_STRIDE 0 `endif -// ======================== L3cache Configurable Knobs ======================== +// L3cache Configurable Knobs ================================================= // Size of cache in bytes `ifndef L3CACHE_SIZE diff --git a/hw/rtl/VX_csr_data.v b/hw/rtl/VX_csr_data.v index b8144358..7488129e 100644 --- a/hw/rtl/VX_csr_data.v +++ b/hw/rtl/VX_csr_data.v @@ -43,18 +43,21 @@ module VX_csr_data #( always @(*) begin case (read_addr) - `CSR_LWID : read_data = 32'(warp_num); - `CSR_GTID , - `CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num); - `CSR_GCID : read_data = CORE_ID; - `CSR_NT : read_data = `NUM_THREADS; - `CSR_NW : read_data = `NUM_WARPS; - `CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS; - `CSR_CYCLL : read_data = num_cycles[31:0]; - `CSR_CYCLH : read_data = num_cycles[63:32]; - `CSR_INSTL : read_data = num_instrs[31:0]; - `CSR_INSTH : read_data = num_instrs[63:32]; - default: read_data = 32'(csr_table[rd_addr]); + `CSR_LWID : read_data = 32'(warp_num); + `CSR_GTID , + `CSR_GWID : read_data = CORE_ID * `NUM_WARPS + 32'(warp_num); + `CSR_GCID : read_data = CORE_ID; + `CSR_NT : read_data = `NUM_THREADS; + `CSR_NW : read_data = `NUM_WARPS; + `CSR_NC : read_data = `NUM_CORES * `NUM_CLUSTERS; + `CSR_CYCLE_L : read_data = num_cycles[31:0]; + `CSR_CYCLE_H : read_data = num_cycles[63:32]; + `CSR_INSTR_L : read_data = num_instrs[31:0]; + `CSR_INSTR_H : read_data = num_instrs[63:32]; + `CSR_VEND_ID : read_data = `VENDOR_ID; + `CSR_ARCH_ID : read_data = `ARCHITECTURE_ID; + `CSR_IMPL_ID : read_data = `IMPLEMENTATION_ID; + default : read_data = 32'(csr_table[rd_addr]); endcase end From 582a00d69005931d3ba9de01f288a7e18c096645 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 30 Jun 2020 10:05:57 -0700 Subject: [PATCH 05/22] adding OPAE CSR support --- driver/rtlsim/Makefile | 8 +- hw/opae/vortex_afu.sv | 51 ++++++--- hw/opae/vortex_afu.vh | 29 +++-- hw/rtl/VX_back_end.v | 7 +- hw/rtl/VX_cluster.v | 77 +++++++++++-- hw/rtl/VX_core.v | 30 +++-- hw/rtl/{VX_csr_arbiter.v => VX_csr_arb.v} | 12 +- hw/rtl/VX_csr_io_arb.v | 85 +++++++++++++++ hw/rtl/Vortex.v | 127 ++++++++++++++++++---- hw/rtl/cache/VX_snp_forwarder.v | 2 +- 10 files changed, 334 insertions(+), 94 deletions(-) rename hw/rtl/{VX_csr_arbiter.v => VX_csr_arb.v} (97%) create mode 100644 hw/rtl/VX_csr_io_arb.v diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 4129ade5..19b39484 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG=1 -#AFU=1 +AFU=1 CFLAGS += -fPIC @@ -56,8 +56,10 @@ endif # AFU ifdef AFU TOP = vortex_afu_sim - VL_FLAGS += -DNOPAE -DSCOPE - CFLAGS += -DNOPAE -DSCOPE + VL_FLAGS += -DNOPAE + CFLAGS += -DNOPAE + #VL_FLAGS += -DSCOPE + #CFLAGS += -DSCOPE RTL_INCLUDE += -I../../hw/opae -I../../hw/opae/ccip endif diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 2216611e..b57a3bc9 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -122,6 +122,17 @@ logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag; `DEBUG_END logic vx_snp_rsp_ready; +logic vx_csr_io_req_valid; +logic [`NC_BITS-1:0] vx_csr_io_req_coreid; +logic [11:0] vx_csr_io_req_addr; +logic vx_csr_io_req_rw; +logic [31:0] vx_csr_io_req_data; +logic vx_csr_io_req_ready; + +logic vx_csr_io_rsp_valid; +logic [31:0] vx_csr_io_rsp_data; +logic vx_csr_io_rsp_ready; + logic vx_reset; logic vx_busy; @@ -156,7 +167,7 @@ logic cmd_scope_read; logic cmd_scope_write; `endif -logic [31:0] cmd_csr_addr; +logic [11:0] cmd_csr_addr; logic [31:0] cmd_csr_rdata; logic [31:0] cmd_csr_wdata; @@ -278,7 +289,7 @@ begin end `endif MMIO_CSR_READ: begin - mmio_tx.data <= cmd_csr_rdata; + mmio_tx.data <= 64'(cmd_csr_rdata); `ifdef DBG_PRINT_OPAE $display("%t: MMIO_CSR_READ: data=%0h", $time, cmd_csr_rdata); `endif @@ -854,20 +865,17 @@ end // CSRs/////////////////////////////////////////////////////////////////////// -assign cmd_csr_read_done = 1; -assign cmd_csr_write_done = 1; +assign vx_csr_io_req_valid = (STATE_CSR_READ == state || STATE_CSR_WRITE == state); +assign vx_csr_io_req_coreid = 0; +assign vx_csr_io_req_rw = (STATE_CSR_WRITE == state); +assign vx_csr_io_req_addr = cmd_csr_addr; +assign vx_csr_io_req_data = cmd_csr_wdata; -always_comb begin - case (cmd_csr_addr) - `CSR_VEND_ID : cmd_csr_rdata = `VENDOR_ID; - `CSR_ARCH_ID : cmd_csr_rdata = `ARCHITECTURE_ID; - `CSR_IMPL_ID : cmd_csr_rdata = `IMPLEMENTATION_ID; - `CSR_NT : cmd_csr_rdata = `NUM_THREADS; - `CSR_NW : cmd_csr_rdata = `NUM_WARPS; - `CSR_NC : cmd_csr_rdata = `NUM_CORES * `NUM_CLUSTERS; - default : cmd_csr_rdata = 0; - endcase -end +assign cmd_csr_rdata = vx_csr_io_rsp_data; +assign vx_csr_io_rsp_ready = 1; + +assign cmd_csr_read_done = vx_csr_io_rsp_valid; +assign cmd_csr_write_done = vx_csr_io_req_ready; // Vortex ///////////////////////////////////////////////////////////////////// @@ -925,6 +933,19 @@ Vortex #() vortex ( .io_rsp_data (0), .io_rsp_tag (0), `UNUSED_PIN (io_rsp_ready), + + // CSR I/O Request + .csr_io_req_valid (vx_csr_io_req_valid), + .csr_io_req_coreid(vx_csr_io_req_coreid), + .csr_io_req_addr (vx_csr_io_req_addr), + .csr_io_req_rw (vx_csr_io_req_rw), + .csr_io_req_data (vx_csr_io_req_data), + .csr_io_req_ready (vx_csr_io_req_ready), + + // CSR I/O Response + .csr_io_rsp_valid (vx_csr_io_rsp_valid), + .csr_io_rsp_data (vx_csr_io_rsp_data), + .csr_io_rsp_ready (vx_csr_io_rsp_ready), // status .busy (vx_busy), diff --git a/hw/opae/vortex_afu.vh b/hw/opae/vortex_afu.vh index 8d437c38..2b201bfd 100644 --- a/hw/opae/vortex_afu.vh +++ b/hw/opae/vortex_afu.vh @@ -12,17 +12,24 @@ `define AFU_ACCEL_NAME "vortex_afu" `define AFU_ACCEL_UUID 128'h35f9452b_25c2_434c_93d5_6f8c60db361c -`define AFU_IMAGE_CMD_TYPE_CLFLUSH 4 -`define AFU_IMAGE_CMD_TYPE_READ 1 -`define AFU_IMAGE_CMD_TYPE_RUN 3 -`define AFU_IMAGE_CMD_TYPE_WRITE 2 -`define AFU_IMAGE_MMIO_CSR_CMD 10 -`define AFU_IMAGE_MMIO_CSR_DATA_SIZE 12 -`define AFU_IMAGE_MMIO_CSR_IO_ADDR 14 -`define AFU_IMAGE_MMIO_CSR_MEM_ADDR 16 -`define AFU_IMAGE_MMIO_CSR_STATUS 18 -`define AFU_IMAGE_MMIO_CSR_SCOPE_CMD 20 -`define AFU_IMAGE_MMIO_CSR_SCOPE_DATA 22 + +`define AFU_IMAGE_CMD_CLFLUSH 4 +`define AFU_IMAGE_CMD_CSR_READ 5 +`define AFU_IMAGE_CMD_CSR_WRITE 6 +`define AFU_IMAGE_CMD_MEM_READ 1 +`define AFU_IMAGE_CMD_MEM_WRITE 2 +`define AFU_IMAGE_CMD_RUN 3 +`define AFU_IMAGE_MMIO_CMD_TYPE 10 +`define AFU_IMAGE_MMIO_CSR_ADDR 24 +`define AFU_IMAGE_MMIO_CSR_DATA 26 +`define AFU_IMAGE_MMIO_CSR_READ 28 +`define AFU_IMAGE_MMIO_DATA_SIZE 16 +`define AFU_IMAGE_MMIO_IO_ADDR 12 +`define AFU_IMAGE_MMIO_MEM_ADDR 14 +`define AFU_IMAGE_MMIO_SCOPE_READ 20 +`define AFU_IMAGE_MMIO_SCOPE_WRITE 22 +`define AFU_IMAGE_MMIO_STATUS 18 + `define AFU_IMAGE_POWER 0 `define AFU_TOP_IFC "ccip_std_afu_avalon_mm" diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index c9f45d04..00b118ee 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -106,9 +106,9 @@ module VX_back_end #( VX_csr_req_if issued_csr_req(); - VX_wb_if csr_pipe_rsp(); + VX_wb_if csr_pipe_rsp(); - VX_csr_arbiter csr_arbiter ( + VX_csr_arb csr_arbiter ( .clk (clk), .reset (reset), .csr_pipe_stall(stall_gpr_csr), @@ -118,8 +118,7 @@ module VX_back_end #( .csr_pipe_rsp (csr_pipe_rsp), .csr_wb_if (csr_wb_if), - .csr_io_rsp (io_csr_rsp) - + .csr_io_rsp (io_csr_rsp) ); VX_csr_pipe #( diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index f2ebe770..9264a7a5 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -56,6 +56,19 @@ module VX_cluster #( input wire [`L2CORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, + // CSR I/O Request + input wire csr_io_req_valid, + input wire [`NC_BITS-1:0] csr_io_req_coreid, + input wire [11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire [31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // CSR I/O Response + output wire csr_io_rsp_valid, + output wire [31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, + // Status output wire busy, output wire ebreak @@ -109,10 +122,22 @@ module VX_cluster #( wire [`NUM_CORES-1:0][31:0] per_core_io_rsp_data; wire [`NUM_CORES-1:0] per_core_io_rsp_ready; + wire [`NUM_CORES-1:0] per_core_csr_io_req_valid; + wire [`NUM_CORES-1:0][`NC_BITS-1:0] per_core_csr_io_req_coreid; + wire [`NUM_CORES-1:0][11:0] per_core_csr_io_req_addr; + wire [`NUM_CORES-1:0] per_core_csr_io_req_rw; + wire [`NUM_CORES-1:0][31:0] per_core_csr_io_req_data; + wire [`NUM_CORES-1:0] per_core_csr_io_req_ready; + + wire [`NUM_CORES-1:0] per_core_csr_io_rsp_valid; + wire [`NUM_CORES-1:0][31:0] per_core_csr_io_rsp_data; + wire [`NUM_CORES-1:0] per_core_csr_io_rsp_ready; + wire [`NUM_CORES-1:0] per_core_busy; wire [`NUM_CORES-1:0] per_core_ebreak; genvar i; + for (i = 0; i < `NUM_CORES; i++) begin VX_core #( .CORE_ID(i + (CLUSTER_ID * `NUM_CORES)) @@ -174,18 +199,15 @@ module VX_cluster #( .io_rsp_tag (per_core_io_rsp_tag [i]), .io_rsp_ready (per_core_io_rsp_ready [i]), + .csr_io_req_valid (per_core_csr_io_req_valid[i] && (per_core_csr_io_req_coreid[i] == `NC_BITS'(i))), + .csr_io_req_rw (per_core_csr_io_req_rw [i]), + .csr_io_req_addr (per_core_csr_io_req_addr [i]), + .csr_io_req_data (per_core_csr_io_req_data [i]), + .csr_io_req_ready (per_core_csr_io_req_ready [i]), - - .csr_io_req_valid (1'b0), // Valid CSR IO Request - `UNUSED_PIN(csr_io_req_ready), // Core is ready to accept Request - `UNUSED_PIN(csr_io_req_cid), // CORE_ID of the intended request - `UNUSED_PIN(csr_io_req_addr), // ADDRESS of request - `UNUSED_PIN(csr_io_req_rw), // Read=0, Write=1 - `UNUSED_PIN(csr_io_req_data), // Data to write - - `UNUSED_PIN(csr_io_rsp_valid), // Core IO Response valid - `UNUSED_PIN(csr_io_rsp_data), // Core IO Response data - + .csr_io_rsp_valid (per_core_csr_io_rsp_valid [i]), + .csr_io_rsp_data (per_core_csr_io_rsp_data [i]), + .csr_io_rsp_ready (per_core_csr_io_rsp_ready [i]), .busy (per_core_busy [i]), .ebreak (per_core_ebreak [i]) @@ -231,6 +253,39 @@ module VX_cluster #( .out_mem_rsp_data (io_rsp_data), .out_mem_rsp_ready (io_rsp_ready) ); + + VX_csr_io_arb #( + .NUM_REQUESTS (`NUM_CORES) + ) csr_io_arb ( + .clk (clk), + .reset (reset), + + // input requests + .in_csr_io_req_valid (csr_io_req_valid), + .in_csr_io_req_coreid (csr_io_req_coreid), + .in_csr_io_req_addr (csr_io_req_addr), + .in_csr_io_req_rw (csr_io_req_rw), + .in_csr_io_req_data (csr_io_req_data), + .in_csr_io_req_ready (csr_io_req_ready), + + // input responses + .in_csr_io_rsp_valid (per_core_csr_io_rsp_valid), + .in_csr_io_rsp_data (per_core_csr_io_rsp_data), + .in_csr_io_rsp_ready (per_core_csr_io_rsp_ready), + + // output request + .out_csr_io_req_valid (per_core_csr_io_req_valid), + .out_csr_io_req_coreid (per_core_csr_io_req_coreid), + .out_csr_io_req_addr (per_core_csr_io_req_addr), + .out_csr_io_req_rw (per_core_csr_io_req_rw), + .out_csr_io_req_data (per_core_csr_io_req_data), + .out_csr_io_req_ready (per_core_csr_io_req_ready), + + // output response + .out_csr_io_rsp_valid (csr_io_rsp_valid), + .out_csr_io_rsp_data (csr_io_rsp_data), + .out_csr_io_rsp_ready (csr_io_rsp_ready) + ); assign busy = (| per_core_busy); assign ebreak = (& per_core_ebreak); diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index fb176c5b..6ec07382 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -70,46 +70,45 @@ module VX_core #( input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, - // IO CSR Request - input wire csr_io_req_valid, - input wire[`NC_BITS-1:0] csr_io_req_cid, - input wire[11:0] csr_io_req_addr, - input wire csr_io_req_rw, - input wire[31:0] csr_io_req_data, - output wire csr_io_req_ready, + // CSR I/O Request + input wire csr_io_req_valid, + input wire[11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire[31:0] csr_io_req_data, + output wire csr_io_req_ready, - // IO CSR Response - output wire csr_io_rsp_valid, - output wire[31:0] csr_io_rsp_data, + // CSR I/O Response + output wire csr_io_rsp_valid, + output wire[31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, // Status output wire busy, output wire ebreak ); + `UNUSED_VAR(csr_io_rsp_ready) + // IO CSR request VX_csr_req_if io_csr_req(); - wire temp_io_csr_req_valid = csr_io_req_valid & (csr_io_req_cid == CORE_ID[`NC_BITS-1:0]); + wire temp_io_csr_req_valid = csr_io_req_valid; assign io_csr_req.valid = {`NUM_THREADS{temp_io_csr_req_valid}}; assign io_csr_req.is_csr = 1'b1; assign io_csr_req.csr_address = csr_io_req_addr; assign io_csr_req.alu_op = csr_io_req_rw ? `ALU_CSR_RW : `ALU_CSR_RS; assign io_csr_req.csr_mask = csr_io_req_rw ? csr_io_req_data : 32'b0; - - VX_wb_if io_csr_rsp(); assign csr_io_req_ready = io_csr_rsp.is_io; assign csr_io_rsp_valid = io_csr_rsp.valid[0]; assign csr_io_rsp_data = io_csr_rsp.data[0]; + `IGNORE_WARNINGS_BEGIN wire [4:0] unused_rd = io_csr_rsp.rd; wire [1:0] unused_wb = io_csr_rsp.wb; wire [31:0] unused_curr_PC = io_csr_rsp.curr_PC; `IGNORE_WARNINGS_END - - // Dcache Interfaces VX_cache_dram_req_if #( .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), @@ -213,7 +212,6 @@ module VX_core #( .clk(clk), .reset(reset), - // IO CSR .io_csr_req (io_csr_req), .io_csr_rsp (io_csr_rsp), diff --git a/hw/rtl/VX_csr_arbiter.v b/hw/rtl/VX_csr_arb.v similarity index 97% rename from hw/rtl/VX_csr_arbiter.v rename to hw/rtl/VX_csr_arb.v index 214d4ebd..7abe4f9a 100644 --- a/hw/rtl/VX_csr_arbiter.v +++ b/hw/rtl/VX_csr_arb.v @@ -1,25 +1,23 @@ `include "VX_define.vh" -module VX_csr_arbiter ( +module VX_csr_arb ( input wire clk, input wire reset, + input wire csr_pipe_stall, VX_csr_req_if core_csr_req, - VX_csr_req_if io_csr_req, - + VX_csr_req_if io_csr_req, VX_csr_req_if issued_csr_req, VX_wb_if csr_pipe_rsp, VX_wb_if csr_wb_if, VX_wb_if csr_io_rsp - ); `UNUSED_VAR (clk) `UNUSED_VAR (reset) - wire pick_core = (|core_csr_req.valid); // Which request to pick @@ -37,8 +35,6 @@ module VX_csr_arbiter ( assign issued_csr_req.rd = core_csr_req.rd; assign issued_csr_req.wb = core_csr_req.wb; - - // Core Writeback assign csr_wb_if.valid = csr_pipe_rsp.valid & {`NUM_THREADS{~csr_pipe_rsp.is_io}}; @@ -59,6 +55,4 @@ module VX_csr_arbiter ( assign csr_io_rsp.curr_PC = csr_pipe_rsp.curr_PC; assign csr_io_rsp.is_io = !(csr_pipe_stall || pick_core); - - endmodule diff --git a/hw/rtl/VX_csr_io_arb.v b/hw/rtl/VX_csr_io_arb.v new file mode 100644 index 00000000..3c5ada5e --- /dev/null +++ b/hw/rtl/VX_csr_io_arb.v @@ -0,0 +1,85 @@ +`include "VX_define.vh" + +module VX_csr_io_arb #( + parameter NUM_REQUESTS = 1, + parameter REQS_BITS = `CLOG2(NUM_REQUESTS) +) ( + input wire clk, + input wire reset, + + // input requests + input wire in_csr_io_req_valid, + input wire [`NC_BITS-1:0] in_csr_io_req_coreid, + input wire [11:0] in_csr_io_req_addr, + input wire in_csr_io_req_rw, + input wire [31:0] in_csr_io_req_data, + output wire in_csr_io_req_ready, + + // input response + input wire [NUM_REQUESTS-1:0] in_csr_io_rsp_valid, + input wire [NUM_REQUESTS-1:0][31:0] in_csr_io_rsp_data, + output wire [NUM_REQUESTS-1:0] in_csr_io_rsp_ready, + + // output request + output wire [NUM_REQUESTS-1:0] out_csr_io_req_valid, + output wire [NUM_REQUESTS-1:0][`NC_BITS-1:0] out_csr_io_req_coreid, + output wire [NUM_REQUESTS-1:0][11:0] out_csr_io_req_addr, + output wire [NUM_REQUESTS-1:0] out_csr_io_req_rw, + output wire [NUM_REQUESTS-1:0][31:0] out_csr_io_req_data, + input wire [NUM_REQUESTS-1:0] out_csr_io_req_ready, + + // output response + output wire out_csr_io_rsp_valid, + output wire [31:0] out_csr_io_rsp_data, + input wire out_csr_io_rsp_ready +); + if (NUM_REQUESTS == 1) begin + + `UNUSED_VAR (clk) + `UNUSED_VAR (reset) + + assign out_csr_io_req_valid = in_csr_io_req_valid; + assign out_csr_io_req_coreid = in_csr_io_req_coreid; + assign out_csr_io_req_rw = in_csr_io_req_rw; + assign out_csr_io_req_addr = in_csr_io_req_addr; + assign out_csr_io_req_data = in_csr_io_req_data; + assign in_csr_io_req_ready = out_csr_io_req_ready; + + assign out_csr_io_rsp_valid = in_csr_io_rsp_valid; + assign out_csr_io_rsp_data = in_csr_io_rsp_data; + assign in_csr_io_rsp_ready = out_csr_io_rsp_ready; + + end else begin + + reg [REQS_BITS-1:0] bus_rsp_sel; + + VX_fixed_arbiter #( + .N(NUM_REQUESTS) + ) arbiter ( + .clk (clk), + .reset (reset), + .requests (in_csr_io_rsp_valid), + .grant_index (bus_rsp_sel), + `UNUSED_PIN (grant_valid), + `UNUSED_PIN (grant_onehot) + ); + + assign out_csr_io_rsp_valid = in_csr_io_rsp_valid [bus_rsp_sel]; + assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel]; + assign in_csr_io_rsp_ready [bus_rsp_sel] = out_csr_io_rsp_ready; + + genvar i; + + for (i = 0; i < NUM_REQUESTS; i++) begin + assign out_csr_io_req_valid[i] = in_csr_io_req_valid && in_csr_io_req_ready; + assign out_csr_io_req_coreid[i] = in_csr_io_req_coreid; + assign out_csr_io_req_rw[i] = in_csr_io_req_rw; + assign out_csr_io_req_addr[i] = in_csr_io_req_addr; + assign out_csr_io_req_data[i] = in_csr_io_req_data; + end + + assign in_csr_io_req_ready = (& out_csr_io_req_ready); + + end + +endmodule \ No newline at end of file diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index 09e381a0..f3c3c56b 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -54,6 +54,19 @@ module Vortex ( input wire [`VX_CORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, + // CSR I/O Request + input wire csr_io_req_valid, + input wire [`NC_BITS-1:0] csr_io_req_coreid, + input wire [11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire [31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // CSR I/O Response + output wire csr_io_rsp_valid, + output wire [31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, + // Status output wire busy, output wire ebreak @@ -109,6 +122,17 @@ module Vortex ( .io_rsp_tag (io_rsp_tag), .io_rsp_ready (io_rsp_ready), + .csr_io_req_valid (csr_io_req_valid), + .csr_io_req_coreid (csr_io_req_coreid), + .csr_io_req_rw (csr_io_req_rw), + .csr_io_req_addr (csr_io_req_addr), + .csr_io_req_data (csr_io_req_data), + .csr_io_req_ready (csr_io_req_ready), + + .csr_io_rsp_valid (csr_io_rsp_valid), + .csr_io_rsp_data (csr_io_rsp_data), + .csr_io_rsp_ready (csr_io_rsp_ready), + .busy (busy), .ebreak (ebreak) ); @@ -151,6 +175,17 @@ module Vortex ( wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid; + wire [`NUM_CLUSTERS-1:0][`NC_BITS-1:0] per_cluster_csr_io_req_coreid; + wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready; + + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid; + wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data; + wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready; + wire [`NUM_CLUSTERS-1:0] per_cluster_busy; wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; @@ -205,6 +240,17 @@ module Vortex ( .io_rsp_tag (per_cluster_io_rsp_tag [i]), .io_rsp_ready (per_cluster_io_rsp_ready [i]), + .csr_io_req_valid (per_cluster_csr_io_req_valid[i]), + .csr_io_req_coreid (per_cluster_csr_io_req_coreid[i]), + .csr_io_req_rw (per_cluster_csr_io_req_rw [i]), + .csr_io_req_addr (per_cluster_csr_io_req_addr[i]), + .csr_io_req_data (per_cluster_csr_io_req_data[i]), + .csr_io_req_ready (per_cluster_csr_io_req_ready[i]), + + .csr_io_rsp_valid (per_cluster_csr_io_rsp_valid[i]), + .csr_io_rsp_data (per_cluster_csr_io_rsp_data[i]), + .csr_io_rsp_ready (per_cluster_csr_io_rsp_ready[i]), + .busy (per_cluster_busy [i]), .ebreak (per_cluster_ebreak [i]) ); @@ -216,38 +262,71 @@ module Vortex ( .TAG_IN_WIDTH (`L2CORE_TAG_WIDTH), .TAG_OUT_WIDTH (`L3CORE_TAG_WIDTH) ) io_arb ( - .clk (clk), - .reset (reset), + .clk (clk), + .reset (reset), // input requests - .in_mem_req_valid (per_cluster_io_req_valid), - .in_mem_req_rw (per_cluster_io_req_rw), - .in_mem_req_byteen (per_cluster_io_req_byteen), - .in_mem_req_addr (per_cluster_io_req_addr), - .in_mem_req_data (per_cluster_io_req_data), - .in_mem_req_tag (per_cluster_io_req_tag), - .in_mem_req_ready (per_cluster_io_req_ready), + .in_mem_req_valid (per_cluster_io_req_valid), + .in_mem_req_rw (per_cluster_io_req_rw), + .in_mem_req_byteen (per_cluster_io_req_byteen), + .in_mem_req_addr (per_cluster_io_req_addr), + .in_mem_req_data (per_cluster_io_req_data), + .in_mem_req_tag (per_cluster_io_req_tag), + .in_mem_req_ready (per_cluster_io_req_ready), // input responses - .in_mem_rsp_valid (per_cluster_io_rsp_valid), - .in_mem_rsp_data (per_cluster_io_rsp_data), - .in_mem_rsp_tag (per_cluster_io_rsp_tag), - .in_mem_rsp_ready (per_cluster_io_rsp_ready), + .in_mem_rsp_valid (per_cluster_io_rsp_valid), + .in_mem_rsp_data (per_cluster_io_rsp_data), + .in_mem_rsp_tag (per_cluster_io_rsp_tag), + .in_mem_rsp_ready (per_cluster_io_rsp_ready), // output request - .out_mem_req_valid (io_req_valid), - .out_mem_req_rw (io_req_rw), - .out_mem_req_byteen (io_req_byteen), - .out_mem_req_addr (io_req_addr), - .out_mem_req_data (io_req_data), - .out_mem_req_tag (io_req_tag), - .out_mem_req_ready (io_req_ready), + .out_mem_req_valid (io_req_valid), + .out_mem_req_rw (io_req_rw), + .out_mem_req_byteen (io_req_byteen), + .out_mem_req_addr (io_req_addr), + .out_mem_req_data (io_req_data), + .out_mem_req_tag (io_req_tag), + .out_mem_req_ready (io_req_ready), // output response - .out_mem_rsp_valid (io_rsp_valid), - .out_mem_rsp_tag (io_rsp_tag), - .out_mem_rsp_data (io_rsp_data), - .out_mem_rsp_ready (io_rsp_ready) + .out_mem_rsp_valid (io_rsp_valid), + .out_mem_rsp_tag (io_rsp_tag), + .out_mem_rsp_data (io_rsp_data), + .out_mem_rsp_ready (io_rsp_ready) + ); + + VX_csr_io_arb #( + .NUM_REQUESTS (`NUM_CLUSTERS) + ) csr_io_arb ( + .clk (clk), + .reset (reset), + + // input requests + .in_csr_io_req_valid (csr_io_req_valid), + .in_csr_io_req_coreid (csr_io_req_coreid), + .in_csr_io_req_addr (csr_io_req_addr), + .in_csr_io_req_rw (csr_io_req_rw), + .in_csr_io_req_data (csr_io_req_data), + .in_csr_io_req_ready (csr_io_req_ready), + + // input responses + .in_csr_io_rsp_valid (per_cluster_csr_io_rsp_valid), + .in_csr_io_rsp_data (per_cluster_csr_io_rsp_data), + .in_csr_io_rsp_ready (per_cluster_csr_io_rsp_ready), + + // output request + .out_csr_io_req_valid (per_cluster_csr_io_req_valid), + .out_csr_io_req_coreid (per_cluster_csr_io_req_coreid), + .out_csr_io_req_addr (per_cluster_csr_io_req_addr), + .out_csr_io_req_rw (per_cluster_csr_io_req_rw), + .out_csr_io_req_data (per_cluster_csr_io_req_data), + .out_csr_io_req_ready (per_cluster_csr_io_req_ready), + + // output response + .out_csr_io_rsp_valid (csr_io_rsp_valid), + .out_csr_io_rsp_data (csr_io_rsp_data), + .out_csr_io_rsp_ready (csr_io_rsp_ready) ); assign busy = (| per_cluster_busy); diff --git a/hw/rtl/cache/VX_snp_forwarder.v b/hw/rtl/cache/VX_snp_forwarder.v index 7af7f80c..0536d393 100644 --- a/hw/rtl/cache/VX_snp_forwarder.v +++ b/hw/rtl/cache/VX_snp_forwarder.v @@ -88,7 +88,7 @@ module VX_snp_forwarder #( genvar i; for (i = 0; i < NUM_REQUESTS; i++) begin - assign snp_fwdout_valid[i] = snp_req_valid && !sfq_full; + assign snp_fwdout_valid[i] = snp_req_valid && snp_req_ready; assign snp_fwdout_addr[i] = snp_req_addr; assign snp_fwdout_invalidate[i] = snp_req_invalidate; assign snp_fwdout_tag[i] = sfq_write_addr; From 7d5ed7ac5f9ebf59fafd22cc5c5be2887ea8b6e7 Mon Sep 17 00:00:00 2001 From: felsabbagh3 Date: Tue, 30 Jun 2020 12:03:55 -0700 Subject: [PATCH 06/22] Removed stall dependancy on csr_req_if_valid --- hw/rtl/VX_csr_pipe.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index dd80a811..52b6ff94 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -77,6 +77,6 @@ module VX_csr_pipe #( csr_read_data_s2; end - assign stall_gpr_csr = no_slot_csr && csr_req_if.is_csr && (| csr_req_if.valid); + assign stall_gpr_csr = no_slot_csr; endmodule From 9f33a9feb7661e8252cb5882be86abdf79641f23 Mon Sep 17 00:00:00 2001 From: trmontgomery Date: Tue, 30 Jun 2020 17:49:43 -0400 Subject: [PATCH 07/22] cache_sim.cpp created --- hw/unit_tests/cache/Makefile | 42 + hw/unit_tests/cache/cache_sim.cpp | 74 + hw/unit_tests/cache/cache_sim.h | 0 hw/unit_tests/cache/obj_dir/VVX_cache.cpp | 56983 ++++++++++++++++ hw/unit_tests/cache/obj_dir/VVX_cache.h | 1681 + hw/unit_tests/cache/obj_dir/VVX_cache.mk | 67 + .../cache/obj_dir/VVX_cache__Syms.cpp | 107 + hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h | 123 + .../cache/obj_dir/VVX_cache__Trace.cpp | 9560 +++ .../cache/obj_dir/VVX_cache__Trace__Slow.cpp | 15246 +++++ .../cache/obj_dir/VVX_cache_classes.mk | 43 + hw/unit_tests/cache/simulator.cpp | 83 + hw/unit_tests/cache/simulator.h | 52 + hw/unit_tests/cache/testbase.cpp | 59 + hw/unit_tests/cache/testbench.cpp | 12 + 15 files changed, 84132 insertions(+) create mode 100644 hw/unit_tests/cache/Makefile create mode 100644 hw/unit_tests/cache/cache_sim.cpp create mode 100644 hw/unit_tests/cache/cache_sim.h create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache.cpp create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache.h create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache.mk create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk create mode 100644 hw/unit_tests/cache/simulator.cpp create mode 100644 hw/unit_tests/cache/simulator.h create mode 100644 hw/unit_tests/cache/testbase.cpp create mode 100644 hw/unit_tests/cache/testbench.cpp diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile new file mode 100644 index 00000000..343fd281 --- /dev/null +++ b/hw/unit_tests/cache/Makefile @@ -0,0 +1,42 @@ +PARAM += + + +# control RTL debug print states +DBG_PRINT_FLAGS = -DDBG_PRINT_CORE_ICACHE \ + -DDBG_PRINT_CORE_DCACHE \ + -DDBG_PRINT_CACHE_BANK \ + -DDBG_PRINT_CACHE_SNP \ + -DDBG_PRINT_CACHE_MSRQ \ + -DDBG_PRINT_DRAM \ + -DDBG_PRINT_OPAE + +#DBG_PRINT=$(DBG_PRINT_FLAGS) + +INCLUDE = -I../../rtl/ -I../../rtl/cache -I../../rtl/libs + + +SRCS = cache_sim.cpp + +all: build + +CF += -std=c++11 -fms-extensions -I../.. + +VF += --language 1800-2009 --assert -Wall --trace #-Wpedantic +VF += -Wno-DECLFILENAME +VF += --x-initial unique +VF += -exe $(SRCS) $(INCLUDE) + +DBG += -DVCD_OUTPUT $(DBG_PRINT) + + +gen: + verilator $(VF) -DNDEBUG -cc VX_cache.v $(PARAM) -CFLAGS '$(CF) -DNDEBUG $(PARAM)' --exe $(SRCS) + +build: gen + (cd obj_dir && make -j -f VVX_cache.mk) + +run: build + (cd obj_dir && ./VVX_cache) + +clean: + rm -rf obj_dir diff --git a/hw/unit_tests/cache/cache_sim.cpp b/hw/unit_tests/cache/cache_sim.cpp new file mode 100644 index 00000000..1931fd8a --- /dev/null +++ b/hw/unit_tests/cache/cache_sim.cpp @@ -0,0 +1,74 @@ +#include "VVX_cache.h" +#include "VVX_cache__Syms.h" +#include "verilated.h" + +#include + +#include +#include + +uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +void tick(VVX_cache* tb){ + tb->eval(); + tb->clk = 1; + + tb->eval(); + tb->clk = 0; + tb->eval(); +} + +int main(int argc, char **argv){ + Verilated::commandArgs(argc, argv); //passes the command args to the object + + VVX_cache *tb = new VVX_cachee; + + //reset the cache + tb->reset = 1; + tb->eval(); + tb->reset = 0; + + //declare variables for output - data members in cache class + unsigned int clk; + bool full; + bool empty; + int size; + int data_out; + + //assign inputs + tb->core_req_valid = 1; + tb->core_req_rw = 1; + + char byte_en[] = {}; //word size 4 bytes + tb->core_req_byteen[0] = 1; + tb->core_req_byteen[1] = 1; + tb->core_req_byteen[2] = 1; + tb->core_req_byteen[3] = 1; + + char addr[4] = {0x1a, 0x2b, 0x3c, 0x4d}; //word addr width + + tb->core_req_addr[0] = arr[0]; + tb->core_req_addr[0] = arr[1]; + tb->core_req_addr[0] = arr[2]; + tb->core_req_addr[0] = arr[3]; + + //char req_data[] = {}; //word width + //tb->core_req_data + + //char req_tag[] = {}; //core_req_tag_count by core req_tag_width + //tb->core_req_tag = + + + for (int i = 0; i < 5; ++i){ + //toggle the clock + tick(tb); + } + + delete tb; + + exit(0); +} diff --git a/hw/unit_tests/cache/cache_sim.h b/hw/unit_tests/cache/cache_sim.h new file mode 100644 index 00000000..e69de29b diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache.cpp new file mode 100644 index 00000000..179bbdb8 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.cpp @@ -0,0 +1,56983 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Design implementation internals +// See VVX_cache.h for the primary calling header + +#include "VVX_cache.h" +#include "VVX_cache__Syms.h" + +//========== +CData/*2:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[256]; +CData/*0:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[256]; +IData/*31:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; +CData/*2:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[256]; +CData/*0:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[256]; +IData/*31:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; +CData/*2:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[256]; +CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[256]; +IData/*31:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; +CData/*2:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[256]; +CData/*0:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[256]; +IData/*31:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; +CData/*1:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + +VL_CTOR_IMP(VVX_cache) { + VVX_cache__Syms* __restrict vlSymsp = __VlSymsp = new VVX_cache__Syms(this, name()); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Reset internal values + + // Reset structure values + _ctor_var_reset(); +} + +void VVX_cache::__Vconfigure(VVX_cache__Syms* vlSymsp, bool first) { + if (0 && first) {} // Prevent unused + this->__VlSymsp = vlSymsp; +} + +VVX_cache::~VVX_cache() { + delete __VlSymsp; __VlSymsp=NULL; +} + +void VVX_cache::eval_step() { + VL_DEBUG_IF(VL_DBG_MSGF("+++++TOP Evaluate VVX_cache::eval\n"); ); + VVX_cache__Syms* __restrict vlSymsp = this->__VlSymsp; // Setup global symbol table + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +#ifdef VL_DEBUG + // Debug assertions + _eval_debug_assertions(); +#endif // VL_DEBUG + // Initialize + if (VL_UNLIKELY(!vlSymsp->__Vm_didInit)) _eval_initial_loop(vlSymsp); +#ifdef VM_TRACE + // Tracing +#endif // VM_TRACE + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + VL_DEBUG_IF(VL_DBG_MSGF("+ Clock loop\n");); + vlSymsp->__Vm_activity = true; + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("../../rtl/cache/VX_cache.v", 3, "", + "Verilated model didn't converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void VVX_cache::_eval_initial_loop(VVX_cache__Syms* __restrict vlSymsp) { + vlSymsp->__Vm_didInit = true; + _eval_initial(vlSymsp); + vlSymsp->__Vm_activity = true; + // Evaluate till stable + int __VclockLoop = 0; + QData __Vchange = 1; + do { + _eval_settle(vlSymsp); + _eval(vlSymsp); + if (VL_UNLIKELY(++__VclockLoop > 100)) { + // About to fail, so enable debug to see what's not settling. + // Note you must run make with OPT=-DVL_DEBUG for debug prints. + int __Vsaved_debug = Verilated::debug(); + Verilated::debug(1); + __Vchange = _change_request(vlSymsp); + Verilated::debug(__Vsaved_debug); + VL_FATAL_MT("../../rtl/cache/VX_cache.v", 3, "", + "Verilated model didn't DC converge\n" + "- See DIDNOTCONVERGE in the Verilator manual"); + } else { + __Vchange = _change_request(vlSymsp); + } + } while (VL_UNLIKELY(__Vchange)); +} + +void VVX_cache::_initial__TOP__1(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_initial__TOP__1\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->snp_fwdout_valid = 0U; + vlTOPp->snp_fwdout_addr = VL_ULL(0); + vlTOPp->snp_fwdout_invalidate = 0U; + vlTOPp->snp_fwdout_tag = 0U; + vlTOPp->snp_fwdin_ready = 0U; +} + +VL_INLINE_OPT void VVX_cache::_combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_combo__TOP__2\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1cU & vlTOPp->core_req_addr[0U]))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & (IData)(vlTOPp->core_req_valid)) + << (0x1cU & vlTOPp->core_req_addr[0U]))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1fU & ((IData)(1U) + + (0x1cU & + (vlTOPp->core_req_addr[1U] + << 2U)))))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 1U)) << (0x1fU & ((IData)(1U) + + (0x1cU + & (vlTOPp->core_req_addr[1U] + << 2U)))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1fU & ((IData)(2U) + + (0x1cU & + ((vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 2U)) << (0x1fU & ((IData)(2U) + + (0x1cU + & ((vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1fU & ((IData)(3U) + + (0x1cU & + ((vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 3U)) << (0x1fU & ((IData)(3U) + + (0x1cU + & ((vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xffU; + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[1U] + << 0x1eU) | ( + vlTOPp->core_req_addr[0U] + >> 2U))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & vlTOPp->core_req_addr[1U]))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[2U] + << 2U) | (vlTOPp->core_req_addr[1U] + >> 0x1eU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[3U] + << 4U) | (vlTOPp->core_req_addr[2U] + >> 0x1cU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); +} + +void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_settle__TOP__3\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + WData/*191:0*/ __Vtemp268[6]; + WData/*255:0*/ __Vtemp269[8]; + WData/*191:0*/ __Vtemp281[6]; + WData/*255:0*/ __Vtemp282[8]; + WData/*191:0*/ __Vtemp294[6]; + WData/*255:0*/ __Vtemp295[8]; + WData/*191:0*/ __Vtemp307[6]; + WData/*255:0*/ __Vtemp308[8]; + WData/*191:0*/ __Vtemp320[6]; + WData/*255:0*/ __Vtemp321[8]; + WData/*191:0*/ __Vtemp333[6]; + WData/*255:0*/ __Vtemp334[8]; + WData/*191:0*/ __Vtemp346[6]; + WData/*255:0*/ __Vtemp347[8]; + WData/*191:0*/ __Vtemp359[6]; + WData/*255:0*/ __Vtemp360[8]; + WData/*127:0*/ __Vtemp361[4]; + WData/*287:0*/ __Vtemp368[9]; + WData/*287:0*/ __Vtemp369[9]; + WData/*319:0*/ __Vtemp370[10]; + WData/*127:0*/ __Vtemp373[4]; + WData/*287:0*/ __Vtemp380[9]; + WData/*287:0*/ __Vtemp381[9]; + WData/*319:0*/ __Vtemp382[10]; + WData/*127:0*/ __Vtemp385[4]; + WData/*287:0*/ __Vtemp392[9]; + WData/*287:0*/ __Vtemp393[9]; + WData/*319:0*/ __Vtemp394[10]; + WData/*127:0*/ __Vtemp397[4]; + WData/*287:0*/ __Vtemp404[9]; + WData/*287:0*/ __Vtemp405[9]; + WData/*319:0*/ __Vtemp406[10]; + WData/*127:0*/ __Vtemp409[4]; + WData/*287:0*/ __Vtemp416[9]; + WData/*287:0*/ __Vtemp417[9]; + WData/*319:0*/ __Vtemp418[10]; + WData/*127:0*/ __Vtemp421[4]; + WData/*287:0*/ __Vtemp428[9]; + WData/*287:0*/ __Vtemp429[9]; + WData/*319:0*/ __Vtemp430[10]; + WData/*127:0*/ __Vtemp433[4]; + WData/*287:0*/ __Vtemp440[9]; + WData/*287:0*/ __Vtemp441[9]; + WData/*319:0*/ __Vtemp442[10]; + WData/*127:0*/ __Vtemp445[4]; + WData/*287:0*/ __Vtemp452[9]; + WData/*287:0*/ __Vtemp453[9]; + WData/*319:0*/ __Vtemp454[10]; + // Body + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1cU & vlTOPp->core_req_addr[0U]))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & (IData)(vlTOPp->core_req_valid)) + << (0x1cU & vlTOPp->core_req_addr[0U]))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1fU & ((IData)(1U) + + (0x1cU & + (vlTOPp->core_req_addr[1U] + << 2U)))))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 1U)) << (0x1fU & ((IData)(1U) + + (0x1cU + & (vlTOPp->core_req_addr[1U] + << 2U)))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1fU & ((IData)(2U) + + (0x1cU & + ((vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 2U)) << (0x1fU & ((IData)(2U) + + (0x1cU + & ((vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))); + vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (((~ ((IData)(1U) << (0x1fU & ((IData)(3U) + + (0x1cU & + ((vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))) + & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 3U)) << (0x1fU & ((IData)(3U) + + (0x1cU + & ((vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xffU; + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[1U] + << 0x1eU) | ( + vlTOPp->core_req_addr[0U] + >> 2U))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & vlTOPp->core_req_addr[1U]))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[2U] + << 2U) | (vlTOPp->core_req_addr[1U] + >> 0x1eU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel + = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[3U] + << 4U) | (vlTOPp->core_req_addr[2U] + >> 0x1cU))))) + & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (0U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (0U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (1U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (1U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (2U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (2U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (3U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (3U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (4U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (4U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (5U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (5U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (6U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (6U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (7U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (7U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 5U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 7U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 5U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 5U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx5]; + vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx6]; + vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx7]; + vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx8]; + vlTOPp->__Vtableidx9 = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx9]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx9]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx9]; + vlTOPp->__Vtableidx10 = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx10]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx10]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx10]; + vlTOPp->__Vtableidx11 = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx11]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx11]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx11]; + vlTOPp->__Vtableidx12 = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx12]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx12]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx12]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 5U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 7U))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill + = (0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use + = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) + | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) + - (IData)(1U)))) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (0x1f8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0x80000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 5U)) | + (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xf8000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 1U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfffffU & ((0xfffffeU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 1U)) | (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1fU))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xff800000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x1dU) + | (0x1f800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) + | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 3U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) + | (0xffff0000U & (0x40000U | (0xfff80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x19U) + | (0x1f80000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 7U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] + = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) + | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 7U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] + = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) + | (0xfffff000U & (0x5000U | (0xffff8000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x15U) + | (0x1f8000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0xbU))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) + | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0xbU))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) + | (0xffffff00U & (0x600U | (0xfffff800U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x11U) + | (0x1f800U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0xfU))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] + = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) + | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0xfU))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] + = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) + | (0xfffffff0U & (0x70U | (0xffffff80U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xdU) | + (0x1f80U & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x13U))))))); + vlTOPp->__Vtableidx3 = vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)); + vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (7U & vlTOPp->snp_req_addr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->core_req_ready = (0xffU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) + | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfffcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfff3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x16U)) | (0xfffffc00U + & ((IData)(( + (VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0xaU)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xffcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0xcU)) | (0xfff00000U + & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x14U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xff3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 2U)) | (0xc0000000U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) + | (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfcffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x300U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) + | (0xffffff00U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 8U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + = ((0xfffc0000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) + | ((0xffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x18U)) | (0xffffff00U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 8U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xf3ffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc00U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + = ((0x3ffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) + | (0xfffc0000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x12U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) + | ((0x3ffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x12U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xcfffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x3000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) + | (0xf0000000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + = ((0xfffffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 4U)) | (0xf0000000U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + = ((0xffffffc0U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) + | (0xfffffffU & ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0x3fffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + = ((0x3fU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) + | (0xffffffc0U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + = ((0x3fU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x1aU)) | (0xffffffc0U & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 6U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[5U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[6U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid + = (0xffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) + & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + : (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] + & VL_NEGATE_I((IData)((1U & + (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 7U) | (0x78U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x19U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[5U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[6U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[7U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0x80000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 3U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xffffffU & ((0xffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 3U)) | + (7U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1dU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x18U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[9U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xaU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xbU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xf8000000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1fU) + | (0x78000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 1U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) + | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0xcU))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xdU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xeU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xfU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xff800000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1bU) + | (0x7800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 5U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) + | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) + | (0xffff0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x10U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] + = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) + | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x10U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x10U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x11U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x12U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x13U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) + | (0xffff0000U & (0x40000U | (0xfff80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x17U) + | (0x780000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 9U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] + = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) + | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 9U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] + = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) + | (0xfffff000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0xcU))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) + | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x14U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x15U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x16U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x17U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] + = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) + | (0xfffff000U & (0x5000U | (0xffff8000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x13U) + | (0x78000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0xdU))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) + | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0xdU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) + | (0xffffff00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 8U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] + = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) + | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x18U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x19U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1aU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1bU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) + | (0xffffff00U & (0x600U | (0xfffff800U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0xfU) + | (0x7800U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x11U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] + = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) + | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x11U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] + = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) + | (0xfffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1cU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1dU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1eU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1fU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] + = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) + | (0xfffffff0U & (0x70U | (0xffffff80U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0xbU) | + (0x780U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x15U))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid + = (0xfU & (vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x10U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x14U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x18U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x1cU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->core_rsp_tag = ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) : + ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0)); + vlTOPp->core_rsp_valid = 0U; + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (0xfU & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 2U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 4U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 6U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + >> 8U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 8U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + >> 0x12U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 0xaU)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + >> 0x1cU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 0xcU)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + >> 6U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 0xeU)))); + } + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U; + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (0xfU & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + >> 8U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + >> 0x12U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + >> 0x1cU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 7U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + >> 6U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 9U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U]); + } + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 1U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 2U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 3U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffff0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 4U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + >> 8U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 4U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xffffffe0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 5U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + << 0xeU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + >> 0x12U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 5U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xffffffc0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 6U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + << 4U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + >> 0x1cU))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 6U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xffffff80U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 7U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + << 0x1aU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + >> 6U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 7U)))); + vlTOPp->__Vtableidx1 = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) + << 7U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) + << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value + = (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U]; + vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U]; + vlTOPp->core_rsp_data[2U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U]; + vlTOPp->core_rsp_data[3U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual) + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_rsp_ready)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req + = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + >> (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->__Vtableidx4 = vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->__Vtableidx2 = vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 1U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall))) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 2U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall))) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 3U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall))) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + << 4U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 4U) | (0x3f0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 4U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall))) + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + << 5U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 5U) | (0x7e0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 5U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall))) + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + << 6U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 6U) | (0xfc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 6U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall))) + << 6U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + << 7U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 7U) | (0x1f80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 7U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall))) + << 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 4U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 5U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 6U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 7U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->snp_rsp_valid = vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))); + vlTOPp->snp_rsp_tag = ((0xdfU >= (0xffU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? (0xfffffffU & (((0U == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? 0U + : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + : 0U); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (4U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (5U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (6U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (7U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 7U)); + vlTOPp->dram_req_rw = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; + vlTOPp->dram_req_valid = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop + = (((~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)) + & (IData)(vlTOPp->dram_req_ready)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))); + vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (0xffffU & (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))) + ? 0U + : ( + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ + ((IData)(1U) + + + (3U + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + >> 1U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ + (3U + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + >> 1U))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) + : 0xffffU); + vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + (0x1cU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[1U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0x1cU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[2U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0x1cU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[3U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(4U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0x1cU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? ((0xdfU + >= + (0xffU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? ( + ((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))) + : 0U) + : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req) + ? ( + (0xdfU + >= + (0xffU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? + (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))) + : 0U) + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | ((IData)(vlTOPp->dram_req_ready) & (0U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (1U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (2U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (3U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (4U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (5U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (6U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (7U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing + = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 7U)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing + = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading + = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U != (0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->dram_req_tag = vlTOPp->dram_req_addr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp268[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp268[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp269[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp268[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp269[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp269[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp269[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp281[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp281[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? 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+ (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp281[5U]); + __Vtemp282[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp282[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp281[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp282[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp282[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp282[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp294[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp294[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp295[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp294[5U]); + __Vtemp295[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp295[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp294[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp295[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp295[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp295[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp307[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp307[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp308[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp307[5U]); + __Vtemp308[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp308[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp307[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp308[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp308[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp308[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp320[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp320[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp320[5U]); + __Vtemp321[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp321[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp320[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp321[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp321[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp321[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp333[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp333[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp334[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp333[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp334[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp334[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp334[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp346[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp346[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp347[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp346[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp347[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp347[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp347[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp359[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp359[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + 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vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp360[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp359[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp360[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp360[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp360[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + __Vtemp361[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp361[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp361[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp361[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp368[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp361[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp361[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp368[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp361[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp361[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp361[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp361[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp369[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp361[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp361[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp370[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp368[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp368[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp369[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp370[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp373[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp373[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp373[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp373[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp380[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp373[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp373[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp380[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp373[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp373[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp373[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp373[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp381[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp373[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp373[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp382[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp380[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp380[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp381[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp382[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp385[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp385[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp385[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp385[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp392[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp385[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp385[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp392[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp385[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp385[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp385[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp385[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp393[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp385[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp385[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp394[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp392[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp392[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp393[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp394[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp397[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp397[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp397[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp397[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp404[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp397[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp397[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp404[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp397[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp397[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp397[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp397[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp405[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp397[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp397[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp406[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp404[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp404[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp405[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp406[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp409[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp409[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp409[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp409[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp416[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp409[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp409[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp416[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp409[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp409[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp409[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp409[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp417[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp409[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp409[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp418[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp416[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp416[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp417[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp418[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp421[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp421[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp421[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp421[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp428[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp421[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp421[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp428[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp421[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp421[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp421[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp421[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp429[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp421[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp421[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp430[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp428[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp428[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp429[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp430[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp433[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp433[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp433[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp433[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp440[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp433[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp433[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp440[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp433[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp433[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp433[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp433[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp441[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp433[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp433[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp442[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp440[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp440[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp441[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp442[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp445[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp445[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp445[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp445[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp452[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp445[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp445[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp452[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp445[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp445[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp445[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp445[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp453[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp445[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp445[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp454[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp452[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp452[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp453[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp454[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we))); +} + +VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_sequent__TOP__4\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Variables + CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*0:0*/ __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0; + CData/*3:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*2:0*/ __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + CData/*4:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + CData/*4:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0; + CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*2:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; + CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; + CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; 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+ __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; 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+ __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; 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+ } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid = 0U; 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw + = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U)); + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] + = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] = 0U; + } else { + if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[5U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[6U]; + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr + = (0xfffffffU & ((IData)(0x10U) + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = 0U; + } else { + if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))); + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; + } else { + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = 0U; + } else { + if ((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use))) { + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original + = vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid; + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { + if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) + - (IData)(1U))); + } + } + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) + & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[7U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U]; + __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((7U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U]; + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp514[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp514[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp515[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp515[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp516[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp516[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp517[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp517[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp518[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp518[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp519[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp519[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp520[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp520[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp521[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1dU) + | (0x1fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 3U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xaU) + | (0x3fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x16U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp521[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; + } else { + if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + | ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((~ ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + | ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((~ ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + | ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((~ ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + | ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((~ ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + | ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((~ ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + | ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((~ ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + | ((IData)(1U) << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (((~ ((IData)(1U) << (0xfU & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)) + | ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = (((~ ((IData)(1U) << (0xfU & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)) + | ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + << (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = ((~ ((IData)(1U) << (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty)); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))); + if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { + VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) { + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; 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+ } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; 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+ } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); 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+ } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); 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+ } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x18U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 8U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x10U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + >> 0x18U))); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 + = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + >> 8U))); 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+ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U]); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 8U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; + __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 + = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 + = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + >> 0x10U)); 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; 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+ } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; 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+ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[6U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][7U] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[7U]; + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8); 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+ } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14); + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15) { + VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15), + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15); + } + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 6U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = + ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + if (vlTOPp->reset) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->dram_req_addr; + __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 + = (1U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r + = (1U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (1U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + = vlTOPp->dram_req_addr; + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r))); + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)))) { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.cache_dram_req_arb.prfqq.pfq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r + = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) + - (IData)(1U))); + } + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data + [(1U & ((IData)(1U) + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))))]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 6U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->__Vtableidx12 = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx12]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx12]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx12]; + vlTOPp->__Vtableidx11 = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx11]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx11]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx11]; + vlTOPp->__Vtableidx10 = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx10]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx10]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx10]; + vlTOPp->__Vtableidx9 = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx9]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx9]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx9]; + vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx8]; + vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx7]; + vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx6]; + vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 6U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use + = ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill) + ? (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + : (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; + } + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] + >> 0x12U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0U] + = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x12U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0U] + = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) + << 0x3fU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) + << 0x1fU) | + ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) + >> 1U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x10U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0x11U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] + = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + >> 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] + = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0] + = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0; + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty + = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))))) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + ((IData)(1U) + + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ + (3U & (((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x1eU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : 0U); + vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0x3fffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + = ((0x3fU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) + | (0xffffffc0U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + = ((0x3fU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x1aU)) | (0xffffffc0U & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xcfffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x3000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) + | (0xf0000000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + = ((0xfffffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 4U)) | (0xf0000000U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + = ((0xffffffc0U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) + | (0xfffffffU & ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xf3ffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc00U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + = ((0x3ffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) + | (0xfffc0000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x12U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) + | ((0x3ffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x12U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfcffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x300U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) + | (0xffffff00U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 8U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + = ((0xfffc0000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) + | ((0xffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x18U)) | (0xffffff00U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 8U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xff3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 2U)) | (0xc0000000U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) + | (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xffcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0xcU)) | (0xfff00000U + & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x14U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfff3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x16U)) | (0xfffffc00U + & ((IData)(( + (VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0xaU)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfffcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 5U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 7U))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[1U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[5U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[6U] + = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid + = (0xffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) + & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + : (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] + & VL_NEGATE_I((IData)((1U & + (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] + = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) + | (0xfffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 4U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1cU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1dU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1eU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1fU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] + = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) + | (0xfffffff0U & (0x70U | (0xffffff80U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0xbU) | + (0x780U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x15U))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) + | (0xffffff00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 8U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] + = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) + | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x18U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x19U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1aU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1bU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) + | (0xffffff00U & (0x600U | (0xfffff800U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0xfU) + | (0x7800U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x11U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] + = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) + | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x11U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] + = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) + | (0xfffff000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0xcU))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) + | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x14U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x15U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x16U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x17U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] + = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) + | (0xfffff000U & (0x5000U | (0xffff8000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x13U) + | (0x78000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0xdU))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) + | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0xdU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) + | (0xffff0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x10U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] + = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) + | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x10U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x10U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x11U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x12U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x13U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) + | (0xffff0000U & (0x40000U | (0xfff80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x17U) + | (0x780000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 9U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] + = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) + | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 9U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) + | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0xcU))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xdU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xeU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xfU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xff800000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1bU) + | (0x7800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 5U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) + | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x18U))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[9U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xaU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xbU] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xf8000000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 0x1fU) + | (0x78000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 1U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + << 0x1cU))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) + | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) + | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0x1bU) | (0x7ff0000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[5U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[6U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[7U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0x80000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 3U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) + | (0xffffffU & ((0xffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 3U)) | + (7U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1dU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) + | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) + | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[1U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[2U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[3U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) + | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 7U) | (0x78U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x19U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 7U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + >> 0x12U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x15U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + >> 0xbU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 4U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 3U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + >> 0x1dU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x16U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0x11U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0xfU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + >> 8U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x1fU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 1U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 9U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xaU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0xdU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x13U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xbU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0xcU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0x1bU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 5U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xdU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x1eU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) + ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 9U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0x17U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) : 0U) << 0xfU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) << 6U)) | ((0x20U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) + << 5U)) + | (0x1fffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [ + (0xfU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] + >> 0xbU)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use + = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) + | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) + - (IData)(1U)))) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill + = (0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)); + vlTOPp->__Vtableidx3 = vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid + [vlTOPp->__Vtableidx3]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx3]; + vlTOPp->__Vtableidx1 = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx1]; + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) + << 7U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) + << 7U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = + ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] + = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) + | (0xfffffff0U & (0x70U | (0xffffff80U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xdU) | + (0x1f80U & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x13U))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] + = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) + | (0xffffff00U & (0x600U | (0xfffff800U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x11U) + | (0x1f800U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0xfU))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] + = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) + | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0xfU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] + = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) + | (0xfffff000U & (0x5000U | (0xffff8000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x15U) + | (0x1f8000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0xbU))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] + = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) + | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0xbU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] + = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) + | (0xffff0000U & (0x40000U | (0xfff80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x19U) + | (0x1f80000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 7U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] + = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) + | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfff00000U & (0x300000U | (0xff800000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0x1dU) + | (0x1f800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 3U))))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] + = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) + | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xff000000U & (0x2000000U | (0xf8000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 1U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) + | (0xfffffU & ((0xfffffeU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 1U)) | (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1fU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xf0000000U & (0x10000000U | (0x80000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] + = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) + | (0xffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 5U)) | + (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1bU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] + = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U)))) + >> 0x20U))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] + = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) + | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (0x1f8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))) & (~ ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in + = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready + = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) + | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] + = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x15U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] + = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->core_rsp_tag = ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) : + ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0)); + vlTOPp->core_rsp_valid = 0U; + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (0xfU & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 2U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 4U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 6U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + >> 8U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 8U)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + >> 0x12U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 0xaU)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + >> 0x1cU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 0xcU)))); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + >> 6U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) + | ((IData)(1U) << + (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 0xeU)))); + } + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; + vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U; + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (0xfU & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> + (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + >> 8U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + >> 0x12U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + >> 0x1cU))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 7U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U]); + } + if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + >> 6U))) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : ( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & + (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { + VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) + >> 9U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U]); + } + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) + == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 1U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 2U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 3U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xfffffff0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 4U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + << 0x18U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + >> 8U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 4U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xffffffe0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 5U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + << 0xeU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] + >> 0x12U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 5U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xffffffc0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 6U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] + << 4U) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] + >> 0x1cU))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 6U)))); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + | (0xffffff80U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) + << 7U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] + << 0x1aU) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] + >> 6U))) + == ((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (( + (0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)) << 7U)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req + = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + >> (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))); + vlTOPp->__Vtableidx4 = vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid + [vlTOPp->__Vtableidx4]; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx4]; + vlTOPp->__Vtableidx2 = vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx2]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) | (0xfffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] + = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U)) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x1cU))) | (0xf0000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] + = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 2U)) | (0xfffffffU & + ((0xffffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x1cU)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] + = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 4U)) | (0x1fffffU & ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] + = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 6U)) | ((0xffffffe0U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) + << 5U)) | + (0x1fU & ((0x1ffff0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 4U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x1cU))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual + = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual + = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match + = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]); + vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U]; + vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U]; + vlTOPp->core_rsp_data[2U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U]; + vlTOPp->core_rsp_data[3U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U]; + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value + = (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))); + vlTOPp->snp_rsp_valid = vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))); + vlTOPp->snp_rsp_tag = ((0xdfU >= (0xffU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? (0xfffffffU & (((0U == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) + ? 0U + : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) + : 0U); + vlTOPp->dram_req_rw = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; + vlTOPp->dram_req_valid = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))); + vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (0xffffU & (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))) + ? 0U + : ( + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ + ((IData)(1U) + + + (3U + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + >> 1U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ + (3U + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + >> 1U))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) + : 0xffffU); + vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + (0x1cU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[1U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(1U) + + (0x1cU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[2U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(2U) + + (0x1cU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_data[3U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(4U) + + (0x1cU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ + ((IData)(3U) + + (0x1cU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U)))] + >> (0x1fU & + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 7U)))) + : 0U); + vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) + ? ((0xdfU + >= + (0xffU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? ( + ((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) + | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))))) + : 0U) + : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req) + ? ( + (0xdfU + >= + (0xffU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? + (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))) + : 0U) + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss + = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) | + ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing + = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->dram_req_tag = vlTOPp->dram_req_addr; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + << 7U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 7U) | (0x1f80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 7U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall))) + << 7U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + << 6U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 6U) | (0xfc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 6U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall))) + << 6U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + << 5U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 5U) | (0x7e0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 5U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall))) + << 5U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + << 4U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 4U) | (0x3f0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 4U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall))) + << 4U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 3U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall))) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 2U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall))) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U) + & ((~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)) + << 1U))))) + & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall))) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing + = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe + = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e + = (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing + = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq + = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending + = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp749[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp749[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp750[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp749[5U]); + __Vtemp750[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp750[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp749[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp750[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp750[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp750[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp762[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp762[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp763[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp762[5U]); + __Vtemp763[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp763[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp762[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp763[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp763[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp763[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp775[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp775[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp776[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp776[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp775[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp776[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp776[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp776[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp788[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp788[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp789[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp789[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp788[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp789[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp789[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp789[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp801[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp801[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp802[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp802[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp801[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp802[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp802[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp802[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp814[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp814[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp815[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp815[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp814[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp815[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp815[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp815[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp827[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp827[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp828[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? 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+ (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp828[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp827[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp828[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp828[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp828[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head + = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + __Vtemp840[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ( + (VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + __Vtemp840[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))) + >> 0x1fU)) | (0xfffffffeU + & ((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0)))) + >> 0x20U)) + << 1U))); + __Vtemp841[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + << 0x12U)) | + __Vtemp840[5U]); + __Vtemp841[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U)))))) + >> 0xeU)) | (0xfffc0000U + & ((IData)( + ((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + << 0x12U))); + __Vtemp841[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x1fU) + | ((0x40000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1eU)) + | ((0x20000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (1U + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U)) + << 0x1dU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1cU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) + << 0x1bU) + | ((0x7fffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U))))))))))) + << 0x20U) + | (QData)((IData)( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (((0U + == + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))))) + >> 0x20U)) + >> 0xeU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] + = __Vtemp840[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] + = __Vtemp841[5U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] + = __Vtemp841[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] + = __Vtemp841[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e + = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) + | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); + __Vtemp842[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp842[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp842[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp842[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp849[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp842[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp842[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp849[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp842[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp842[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp842[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp842[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp850[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp842[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp842[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp851[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp849[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp849[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp850[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp851[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp854[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp854[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp854[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp854[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp861[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp854[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp854[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp861[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp854[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp854[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp854[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp854[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp862[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp854[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp854[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp863[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp861[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp861[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp862[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp863[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp866[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp866[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp866[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp866[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp873[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp866[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp866[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp873[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp866[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp866[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp866[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp866[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp874[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp866[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp866[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp875[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp873[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp873[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp874[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp875[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp878[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp878[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp878[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp878[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp885[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp878[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp878[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp885[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp878[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp878[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp878[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp878[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp886[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp878[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp878[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp887[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp885[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp885[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp886[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp887[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp890[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp890[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp890[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp890[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp897[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp890[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp890[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp897[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp890[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp890[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp890[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp890[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp898[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp890[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp890[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp899[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp897[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp897[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp898[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp899[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp902[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp902[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp902[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp902[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp909[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp902[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp902[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp909[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp902[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp902[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp902[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp902[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp910[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp902[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp902[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp911[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp909[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp909[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp910[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp911[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp914[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp914[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp914[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp914[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp921[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp914[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp914[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp921[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp914[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp914[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp914[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp914[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp922[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp914[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp914[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp923[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp921[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp921[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp922[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp923[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + __Vtemp926[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp926[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp926[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp926[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + __Vtemp933[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 8U)) + | (0xff000000U & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp926[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp926[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + << 0x18U))); + __Vtemp933[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp926[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp926[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U)))))))) + >> 8U)) | (0xff000000U + & ((IData)( + ((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp926[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp926[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + << 0x18U))); + __Vtemp934[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x18U)) + | (0xffffffU & ((IData)(((((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U])) + << 0x20U) + | (QData)((IData)( + (((0U + == + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U + : + (__Vtemp926[ + ((IData)(1U) + + + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << + ((IData)(0x20U) + - + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp926[ + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> + (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))))) + >> 0x20U)) + >> 8U))); + __Vtemp935[9U] = (0x3ffffffU & ((0x2000000U & ( + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])) + << 0x19U)) + | ((0x3000000U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + << 0x18U)) + | ((0x3800000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U] + << 0x17U)) + | ((0x3c00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U] + << 0x16U)) + | ((0x3e00000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)) + << 0x15U)) + | ((0x3f00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] + << 0x14U)) + | ((0x3f80000U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] + & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + << 0x13U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] + >> 6U))))))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] + = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] + = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] << 0x11U)) | (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] + = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x18U)) | ((0xfffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U] + << 3U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) + << 2U)) + | ((0xfffffffeU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e) + << 1U)) + | (0x1ffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U] + >> 0xfU)))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] + = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 8U)) | (0xff000000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] + << 0x18U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] + = __Vtemp933[6U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] + = __Vtemp933[7U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] + = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x1aU)) | __Vtemp934[8U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] + = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])) << 0x1bU)) | + ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U] << 0x1aU)) | __Vtemp935[9U])); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write + = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e))) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 2U))) + : 0U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we + = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) + | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) + ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U))) + : 0U)) << 0xcU)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable + = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) + ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we))); +} + +VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_combo__TOP__5\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in + = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U)))) + << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) + << 0x1cU) + | vlTOPp->snp_req_tag)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] + = vlTOPp->dram_rsp_data[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] + = vlTOPp->dram_rsp_data[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] + = vlTOPp->dram_rsp_data[2U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] + = vlTOPp->dram_rsp_data[3U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] + = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (7U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (6U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (5U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (4U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (3U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (2U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (1U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing + = (((IData)(vlTOPp->snp_req_valid) & (0U == + (7U & vlTOPp->snp_req_addr))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (7U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (6U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (5U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (4U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (3U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (2U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (1U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing + = (((IData)(vlTOPp->dram_rsp_valid) & (0U == + (7U + & vlTOPp->dram_rsp_tag))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (7U & vlTOPp->snp_req_addr))); + vlTOPp->core_req_ready = (0xffU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) + | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready + = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual) + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_rsp_ready)))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (4U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (5U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (6U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = + ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + | (((IData)(vlTOPp->snp_rsp_ready) & (7U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) + << 7U)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop + = (((~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)) + & (IData)(vlTOPp->dram_req_ready)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | ((IData)(vlTOPp->dram_req_ready) & (0U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (1U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 1U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (2U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 2U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (3U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 3U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (4U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 4U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (5U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 5U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (6U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 6U)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready + = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + | (((IData)(vlTOPp->dram_req_ready) & (7U + == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) + << 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid + = (0xfU & (vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x10U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x14U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x18U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid + = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + >> 0x1cU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 4U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 5U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 6U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading + = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 7U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 7U)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading + = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U != (0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 4U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 5U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 6U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 7U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing + = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] + = (IData)(vlTOPp->core_req_tag); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] + = ((0xfffffc00U & (vlTOPp->core_req_data[0U] + << 0xaU)) | (IData)((vlTOPp->core_req_tag + >> 0x20U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] + = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] + = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] + = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_data[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] + = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] + << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] + >> 0x16U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] + = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[1U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] + = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[2U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] + = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) + | (0xfffffc00U & (vlTOPp->core_req_addr[3U] + << 0xaU))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] + = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid) + << 0x16U)) | ((0xfffc0000U + & ((IData)(vlTOPp->core_req_rw) + << 0x12U)) + | ((0xfffffffcU + & ((IData)(vlTOPp->core_req_byteen) + << 2U)) + | (0x3ffU + & (vlTOPp->core_req_addr[3U] + >> 0x16U))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading + = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); +} + +void VVX_cache::_eval(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_combo__TOP__2(vlSymsp); + vlTOPp->__Vm_traceActivity = (2U | vlTOPp->__Vm_traceActivity); + if (((IData)(vlTOPp->clk) & (~ (IData)(vlTOPp->__Vclklast__TOP__clk)))) { + vlTOPp->_sequent__TOP__4(vlSymsp); + vlTOPp->__Vm_traceActivity = (4U | vlTOPp->__Vm_traceActivity); + } + vlTOPp->_combo__TOP__5(vlSymsp); + // Final + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_cache::_eval_initial(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval_initial\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_initial__TOP__1(vlSymsp); + vlTOPp->__Vclklast__TOP__clk = vlTOPp->clk; +} + +void VVX_cache::final() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::final\n"); ); + // Variables + VVX_cache__Syms* __restrict vlSymsp = this->__VlSymsp; + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; +} + +void VVX_cache::_eval_settle(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval_settle\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + vlTOPp->_settle__TOP__3(vlSymsp); + vlTOPp->__Vm_traceActivity = (1U | vlTOPp->__Vm_traceActivity); +} + +VL_INLINE_OPT QData VVX_cache::_change_request(VVX_cache__Syms* __restrict vlSymsp) { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_change_request\n"); ); + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + // Body + // Change detection + QData __req = false; // Logically a bool + return __req; +} + +#ifdef VL_DEBUG +void VVX_cache::_eval_debug_assertions() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_eval_debug_assertions\n"); ); + // Body + if (VL_UNLIKELY((clk & 0xfeU))) { + Verilated::overWidthError("clk");} + if (VL_UNLIKELY((reset & 0xfeU))) { + Verilated::overWidthError("reset");} + if (VL_UNLIKELY((core_req_valid & 0xf0U))) { + Verilated::overWidthError("core_req_valid");} + if (VL_UNLIKELY((core_req_rw & 0xf0U))) { + Verilated::overWidthError("core_req_rw");} + if (VL_UNLIKELY((core_rsp_ready & 0xfeU))) { + Verilated::overWidthError("core_rsp_ready");} + if (VL_UNLIKELY((dram_req_ready & 0xfeU))) { + Verilated::overWidthError("dram_req_ready");} + if (VL_UNLIKELY((dram_rsp_valid & 0xfeU))) { + Verilated::overWidthError("dram_rsp_valid");} + if (VL_UNLIKELY((dram_rsp_tag & 0xf0000000U))) { + Verilated::overWidthError("dram_rsp_tag");} + if (VL_UNLIKELY((snp_req_valid & 0xfeU))) { + Verilated::overWidthError("snp_req_valid");} + if (VL_UNLIKELY((snp_req_addr & 0xf0000000U))) { + Verilated::overWidthError("snp_req_addr");} + if (VL_UNLIKELY((snp_req_invalidate & 0xfeU))) { + Verilated::overWidthError("snp_req_invalidate");} + if (VL_UNLIKELY((snp_req_tag & 0xf0000000U))) { + Verilated::overWidthError("snp_req_tag");} + if (VL_UNLIKELY((snp_rsp_ready & 0xfeU))) { + Verilated::overWidthError("snp_rsp_ready");} + if (VL_UNLIKELY((snp_fwdout_ready & 0xfcU))) { + Verilated::overWidthError("snp_fwdout_ready");} + if (VL_UNLIKELY((snp_fwdin_valid & 0xfcU))) { + Verilated::overWidthError("snp_fwdin_valid");} +} +#endif // VL_DEBUG + +void VVX_cache::_ctor_var_reset() { + VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_ctor_var_reset\n"); ); + // Body + clk = VL_RAND_RESET_I(1); + reset = VL_RAND_RESET_I(1); + core_req_valid = VL_RAND_RESET_I(4); + core_req_rw = VL_RAND_RESET_I(4); + core_req_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, core_req_addr); + VL_RAND_RESET_W(128, core_req_data); + core_req_tag = VL_RAND_RESET_Q(42); + core_req_ready = VL_RAND_RESET_I(1); + core_rsp_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(128, core_rsp_data); + core_rsp_tag = VL_RAND_RESET_Q(42); + core_rsp_ready = VL_RAND_RESET_I(1); + dram_req_valid = VL_RAND_RESET_I(1); + dram_req_rw = VL_RAND_RESET_I(1); + dram_req_byteen = VL_RAND_RESET_I(16); + dram_req_addr = VL_RAND_RESET_I(28); + VL_RAND_RESET_W(128, dram_req_data); + dram_req_tag = VL_RAND_RESET_I(28); + dram_req_ready = VL_RAND_RESET_I(1); + dram_rsp_valid = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(128, dram_rsp_data); + dram_rsp_tag = VL_RAND_RESET_I(28); + dram_rsp_ready = VL_RAND_RESET_I(1); + snp_req_valid = VL_RAND_RESET_I(1); + snp_req_addr = VL_RAND_RESET_I(28); + snp_req_invalidate = VL_RAND_RESET_I(1); + snp_req_tag = VL_RAND_RESET_I(28); + snp_req_ready = VL_RAND_RESET_I(1); + snp_rsp_valid = VL_RAND_RESET_I(1); + snp_rsp_tag = VL_RAND_RESET_I(28); + snp_rsp_ready = VL_RAND_RESET_I(1); + snp_fwdout_valid = VL_RAND_RESET_I(2); + snp_fwdout_addr = VL_RAND_RESET_Q(56); + snp_fwdout_invalidate = VL_RAND_RESET_I(2); + snp_fwdout_tag = VL_RAND_RESET_I(2); + snp_fwdout_ready = VL_RAND_RESET_I(2); + snp_fwdin_valid = VL_RAND_RESET_I(2); + snp_fwdin_tag = VL_RAND_RESET_I(2); + snp_fwdin_ready = VL_RAND_RESET_I(2); + VX_cache__DOT__per_bank_core_req_ready = VL_RAND_RESET_I(8); + VX_cache__DOT__per_bank_core_rsp_valid = VL_RAND_RESET_I(8); + VX_cache__DOT__per_bank_core_rsp_tid = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(256, VX_cache__DOT__per_bank_core_rsp_data); + VL_RAND_RESET_W(336, VX_cache__DOT__per_bank_core_rsp_tag); + VX_cache__DOT__per_bank_core_rsp_ready = VL_RAND_RESET_I(8); + VX_cache__DOT__per_bank_dram_fill_req_valid = VL_RAND_RESET_I(8); + VL_RAND_RESET_W(224, VX_cache__DOT__per_bank_dram_fill_req_addr); + VX_cache__DOT__per_bank_dram_fill_rsp_ready = VL_RAND_RESET_I(8); + VX_cache__DOT__per_bank_dram_wb_req_ready = VL_RAND_RESET_I(8); + VX_cache__DOT__per_bank_dram_wb_req_valid = VL_RAND_RESET_I(8); + VL_RAND_RESET_W(128, VX_cache__DOT__per_bank_dram_wb_req_byteen); + VL_RAND_RESET_W(224, VX_cache__DOT__per_bank_dram_wb_req_addr); + VL_RAND_RESET_W(1024, VX_cache__DOT__per_bank_dram_wb_req_data); + VX_cache__DOT__per_bank_snp_req_ready = VL_RAND_RESET_I(8); + VX_cache__DOT__per_bank_snp_rsp_valid = VL_RAND_RESET_I(8); + VL_RAND_RESET_W(224, VX_cache__DOT__per_bank_snp_rsp_tag); + VX_cache__DOT__per_bank_snp_rsp_ready = VL_RAND_RESET_I(8); + VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(128, VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = VL_RAND_RESET_I(28); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_I(28); + }} + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_I(28); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_I(28); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = VL_RAND_RESET_I(8); + VL_RAND_RESET_W(224, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid = VL_RAND_RESET_I(8); + VL_RAND_RESET_W(224, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr); + VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out); + VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank = VL_RAND_RESET_I(3); + VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); + }} + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + }} + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); + }} + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + }} + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); + }} + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); + VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value); + { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); + }} + VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + }} + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); + VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); + __Vtableidx1 = 0; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[0] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[1] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[2] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[3] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[4] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[5] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[6] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[7] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[8] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[9] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[10] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[11] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[12] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[13] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[14] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[15] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16] = 4U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[17] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[18] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[19] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[20] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[21] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[22] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[23] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[24] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[25] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[26] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[27] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[28] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[29] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[30] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[31] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[32] = 5U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[33] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[34] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[35] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[36] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[37] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[38] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[39] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[40] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[41] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[42] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[43] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[44] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[45] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[46] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[47] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[48] = 4U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[49] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[50] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[51] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[52] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[53] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[54] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[55] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[56] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[57] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[58] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[59] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[60] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[61] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[62] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[63] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[64] = 6U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[65] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[66] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[67] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[68] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[69] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[70] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[71] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[72] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[73] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[74] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[75] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[76] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[77] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[78] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[79] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[80] = 4U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[81] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[82] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[83] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[84] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[85] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[86] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[87] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[88] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[89] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[90] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[91] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[92] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[93] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[94] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[95] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[96] = 5U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[97] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[98] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[99] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[100] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[101] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[102] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[103] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[104] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[105] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[106] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[107] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[108] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[109] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[110] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[111] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[112] = 4U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[113] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[114] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[115] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[116] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[117] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[118] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[119] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[120] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[121] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[122] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[123] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[124] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[125] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[126] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[127] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[128] = 7U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[129] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[130] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[131] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[132] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[133] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[134] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[135] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[136] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[137] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[138] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[139] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[140] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[141] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[142] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[143] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[144] = 4U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[145] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[146] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[147] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[148] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[149] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[150] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[151] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[152] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[153] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[154] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[155] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[156] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[157] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[158] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[159] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[160] = 5U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[161] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[162] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[163] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[164] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[165] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[166] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[167] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[168] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[169] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[170] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[171] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[172] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[173] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[174] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[175] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[176] = 4U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[177] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[178] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[179] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[180] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[181] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[182] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[183] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[184] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[185] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[186] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[187] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[188] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[189] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[190] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[191] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[192] = 6U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[193] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[194] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[195] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[196] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[197] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[198] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[199] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[200] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[201] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[202] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[203] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[204] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[205] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[206] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[207] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[208] = 4U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[209] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[210] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[211] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[212] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[213] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[214] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[215] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[216] = 3U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[217] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[218] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[219] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[220] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[221] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[222] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[223] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[224] = 5U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[225] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[226] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[227] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[228] = 2U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[229] = 0U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[230] = 1U; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[231] = 0U; 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+ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; + __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; + __Vtableidx2 = 0; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[0] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[1] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[2] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[3] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[4] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[5] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[6] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[7] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[8] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[9] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[10] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[11] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[12] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[13] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[14] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[15] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[17] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[18] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[19] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[20] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[21] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[22] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[23] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[24] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[25] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[26] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[27] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[28] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[29] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[30] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[31] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[32] = 5U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[33] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[34] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[35] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[36] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[37] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[38] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[39] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[40] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[41] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[42] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[43] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[44] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[45] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[46] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[47] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[48] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[49] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[50] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[51] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[52] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[53] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[54] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[55] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[56] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[57] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[58] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[59] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[60] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[61] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[62] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[63] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[64] = 6U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[65] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[66] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[67] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[68] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[69] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[70] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[71] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[72] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[73] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[74] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[75] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[76] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[77] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[78] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[79] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[80] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[81] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[82] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[83] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[84] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[85] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[86] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[87] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[88] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[89] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[90] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[91] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[92] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[93] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[94] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[95] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[96] = 5U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[97] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[98] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[99] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[100] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[101] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[102] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[103] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[104] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[105] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[106] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[107] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[108] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[109] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[110] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[111] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[112] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[113] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[114] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[115] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[116] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[117] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[118] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[119] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[120] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[121] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[122] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[123] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[124] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[125] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[126] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[127] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[128] = 7U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[129] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[130] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[131] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[132] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[133] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[134] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[135] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[136] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[137] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[138] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[139] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[140] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[141] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[142] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[143] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[144] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[145] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[146] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[147] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[148] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[149] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[150] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[151] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[152] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[153] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[154] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[155] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[156] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[157] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[158] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[159] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[160] = 5U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[161] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[162] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[163] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[164] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[165] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[166] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[167] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[168] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[169] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[170] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[171] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[172] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[173] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[174] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[175] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[176] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[177] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[178] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[179] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[180] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[181] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[182] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[183] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[184] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[185] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[186] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[187] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[188] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[189] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[190] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[191] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[192] = 6U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[193] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[194] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[195] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[196] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[197] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[198] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[199] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[200] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[201] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[202] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[203] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[204] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[205] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[206] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[207] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[208] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[209] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[210] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[211] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[212] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[213] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[214] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[215] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[216] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[217] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[218] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[219] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[220] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[221] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[222] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[223] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[224] = 5U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[225] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[226] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[227] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[228] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[229] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[230] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[231] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[232] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[233] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[234] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[235] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[236] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[237] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[238] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[239] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[240] = 4U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[241] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[242] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[243] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[244] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[245] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[246] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[247] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[248] = 3U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[249] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[250] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[251] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[252] = 2U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[253] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[254] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[255] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[0] = 0U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[1] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[2] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[3] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[4] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[5] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[6] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[7] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[8] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[9] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[10] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[11] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[12] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[13] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[14] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[15] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[17] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[18] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[19] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[20] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[21] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[22] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[23] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[24] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[25] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[26] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[27] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[28] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[29] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[30] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[31] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[32] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[33] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[34] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[35] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[36] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[37] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[38] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[39] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[40] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[41] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[42] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[43] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[44] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[45] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[46] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[47] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[48] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[49] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[50] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[51] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[52] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[53] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[54] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[55] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[56] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[57] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[58] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[59] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[60] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[61] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[62] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[63] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[64] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[65] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[66] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[67] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[68] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[69] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[70] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[71] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[72] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[73] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[74] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[75] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[76] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[77] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[78] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[79] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[80] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[81] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[82] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[83] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[84] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[85] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[86] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[87] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[88] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[89] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[90] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[91] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[92] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[93] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[94] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[95] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[96] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[97] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[98] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[99] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[100] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[101] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[102] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[103] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[104] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[105] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[106] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[107] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[108] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[109] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[110] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[111] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[112] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[113] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[114] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[115] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[116] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[117] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[118] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[119] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[120] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[121] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[122] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[123] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[124] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[125] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[126] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[127] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[128] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[129] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[130] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[131] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[132] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[133] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[134] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[135] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[136] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[137] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[138] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[139] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[140] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[141] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[142] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[143] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[144] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[145] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[146] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[147] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[148] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[149] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[150] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[151] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[152] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[153] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[154] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[155] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[156] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[157] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[158] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[159] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[160] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[161] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[162] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[163] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[164] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[165] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[166] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[167] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[168] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[169] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[170] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[171] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[172] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[173] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[174] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[175] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[176] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[177] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[178] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[179] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[180] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[181] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[182] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[183] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[184] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[185] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[186] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[187] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[188] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[189] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[190] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[191] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[192] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[193] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[194] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[195] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[196] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[197] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[198] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[199] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[200] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[201] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[202] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[203] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[204] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[205] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[206] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[207] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[208] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[209] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[210] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[211] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[212] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[213] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[214] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[215] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[216] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[217] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[218] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[219] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[220] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[221] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[222] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[223] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[224] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[225] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[226] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[227] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[228] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[229] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[230] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[231] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[232] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[233] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[234] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[235] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[236] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[237] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[238] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[239] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[240] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[241] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[242] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[243] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[244] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[245] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[246] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[247] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[248] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[249] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[250] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[251] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[252] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[253] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[254] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[255] = 1U; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; + __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; + __Vtableidx3 = 0; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[0] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[1] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[2] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[3] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[4] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[5] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[6] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[7] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[8] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[9] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[10] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[11] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[12] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[13] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[14] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[15] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[17] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[18] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[19] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[20] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[21] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[22] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[23] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[24] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[25] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[26] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[27] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[28] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[29] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[30] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[31] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[32] = 5U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[33] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[34] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[35] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[36] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[37] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[38] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[39] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[40] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[41] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[42] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[43] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[44] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[45] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[46] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[47] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[48] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[49] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[50] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[51] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[52] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[53] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[54] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[55] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[56] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[57] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[58] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[59] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[60] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[61] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[62] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[63] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[64] = 6U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[65] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[66] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[67] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[68] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[69] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[70] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[71] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[72] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[73] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[74] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[75] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[76] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[77] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[78] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[79] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[80] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[81] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[82] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[83] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[84] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[85] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[86] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[87] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[88] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[89] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[90] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[91] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[92] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[93] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[94] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[95] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[96] = 5U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[97] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[98] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[99] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[100] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[101] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[102] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[103] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[104] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[105] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[106] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[107] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[108] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[109] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[110] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[111] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[112] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[113] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[114] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[115] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[116] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[117] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[118] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[119] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[120] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[121] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[122] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[123] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[124] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[125] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[126] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[127] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[128] = 7U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[129] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[130] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[131] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[132] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[133] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[134] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[135] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[136] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[137] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[138] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[139] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[140] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[141] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[142] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[143] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[144] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[145] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[146] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[147] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[148] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[149] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[150] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[151] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[152] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[153] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[154] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[155] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[156] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[157] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[158] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[159] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[160] = 5U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[161] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[162] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[163] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[164] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[165] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[166] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[167] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[168] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[169] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[170] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[171] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[172] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[173] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[174] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[175] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[176] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[177] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[178] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[179] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[180] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[181] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[182] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[183] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[184] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[185] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[186] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[187] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[188] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[189] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[190] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[191] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[192] = 6U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[193] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[194] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[195] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[196] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[197] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[198] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[199] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[200] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[201] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[202] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[203] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[204] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[205] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[206] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[207] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[208] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[209] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[210] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[211] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[212] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[213] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[214] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[215] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[216] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[217] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[218] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[219] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[220] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[221] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[222] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[223] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[224] = 5U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[225] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[226] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[227] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[228] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[229] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[230] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[231] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[232] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[233] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[234] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[235] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[236] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[237] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[238] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[239] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[240] = 4U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[241] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[242] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[243] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[244] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[245] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[246] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[247] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[248] = 3U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[249] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[250] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[251] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[252] = 2U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[253] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[254] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[255] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[0] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[1] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[2] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[3] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[4] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[5] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[6] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[7] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[8] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[9] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[10] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[11] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[12] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[13] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[14] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[15] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[17] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[18] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[19] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[20] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[21] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[22] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[23] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[24] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[25] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[26] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[27] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[28] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[29] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[30] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[31] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[32] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[33] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[34] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[35] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[36] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[37] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[38] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[39] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[40] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[41] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[42] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[43] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[44] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[45] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[46] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[47] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[48] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[49] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[50] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[51] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[52] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[53] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[54] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[55] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[56] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[57] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[58] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[59] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[60] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[61] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[62] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[63] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[64] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[65] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[66] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[67] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[68] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[69] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[70] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[71] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[72] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[73] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[74] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[75] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[76] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[77] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[78] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[79] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[80] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[81] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[82] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[83] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[84] = 1U; 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+ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[255] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; + __Vtableidx4 = 0; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[0] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[1] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[2] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[3] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[4] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[5] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[6] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[7] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[8] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[9] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[10] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[11] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[12] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[13] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[14] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[15] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[17] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[18] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[19] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[20] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[21] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[22] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[23] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[24] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[25] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[26] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[27] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[28] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[29] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[30] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[31] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[32] = 5U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[33] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[34] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[35] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[36] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[37] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[38] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[39] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[40] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[41] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[42] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[43] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[44] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[45] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[46] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[47] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[48] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[49] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[50] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[51] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[52] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[53] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[54] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[55] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[56] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[57] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[58] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[59] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[60] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[61] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[62] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[63] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[64] = 6U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[65] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[66] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[67] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[68] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[69] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[70] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[71] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[72] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[73] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[74] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[75] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[76] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[77] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[78] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[79] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[80] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[81] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[82] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[83] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[84] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[85] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[86] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[87] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[88] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[89] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[90] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[91] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[92] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[93] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[94] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[95] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[96] = 5U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[97] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[98] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[99] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[100] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[101] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[102] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[103] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[104] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[105] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[106] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[107] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[108] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[109] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[110] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[111] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[112] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[113] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[114] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[115] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[116] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[117] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[118] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[119] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[120] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[121] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[122] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[123] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[124] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[125] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[126] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[127] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[128] = 7U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[129] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[130] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[131] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[132] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[133] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[134] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[135] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[136] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[137] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[138] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[139] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[140] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[141] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[142] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[143] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[144] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[145] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[146] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[147] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[148] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[149] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[150] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[151] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[152] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[153] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[154] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[155] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[156] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[157] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[158] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[159] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[160] = 5U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[161] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[162] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[163] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[164] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[165] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[166] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[167] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[168] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[169] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[170] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[171] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[172] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[173] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[174] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[175] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[176] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[177] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[178] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[179] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[180] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[181] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[182] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[183] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[184] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[185] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[186] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[187] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[188] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[189] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[190] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[191] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[192] = 6U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[193] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[194] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[195] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[196] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[197] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[198] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[199] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[200] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[201] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[202] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[203] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[204] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[205] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[206] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[207] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[208] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[209] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[210] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[211] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[212] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[213] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[214] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[215] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[216] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[217] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[218] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[219] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[220] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[221] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[222] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[223] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[224] = 5U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[225] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[226] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[227] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[228] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[229] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[230] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[231] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[232] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[233] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[234] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[235] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[236] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[237] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[238] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[239] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[240] = 4U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[241] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[242] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[243] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[244] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[245] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[246] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[247] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[248] = 3U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[249] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[250] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[251] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[252] = 2U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[253] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[254] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[255] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[0] = 0U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[1] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[2] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[3] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[4] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[5] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[6] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[7] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[8] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[9] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[10] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[11] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[12] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[13] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[14] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[15] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[17] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[18] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[19] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[20] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[21] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[22] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[23] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[24] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[25] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[26] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[27] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[28] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[29] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[30] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[31] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[32] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[33] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[34] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[35] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[36] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[37] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[38] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[39] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[40] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[41] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[42] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[43] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[44] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[45] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[46] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[47] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[48] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[49] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[50] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[51] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[52] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[53] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[54] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[55] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[56] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[57] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[58] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[59] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[60] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[61] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[62] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[63] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[64] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[65] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[66] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[67] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[68] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[69] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[70] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[71] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[72] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[73] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[74] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[75] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[76] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[77] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[78] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[79] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[80] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[81] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[82] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[83] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[84] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[85] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[86] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[87] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[88] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[89] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[90] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[91] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[92] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[93] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[94] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[95] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[96] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[97] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[98] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[99] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[100] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[101] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[102] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[103] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[104] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[105] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[106] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[107] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[108] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[109] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[110] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[111] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[112] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[113] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[114] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[115] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[116] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[117] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[118] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[119] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[120] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[121] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[122] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[123] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[124] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[125] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[126] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[127] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[128] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[129] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[130] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[131] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[132] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[133] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[134] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[135] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[136] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[137] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[138] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[139] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[140] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[141] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[142] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[143] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[144] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[145] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[146] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[147] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[148] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[149] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[150] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[151] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[152] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[153] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[154] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[155] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[156] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[157] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[158] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[159] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[160] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[161] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[162] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[163] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[164] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[165] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[166] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[167] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[168] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[169] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[170] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[171] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[172] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[173] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[174] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[175] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[176] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[177] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[178] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[179] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[180] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[181] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[182] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[183] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[184] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[185] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[186] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[187] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[188] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[189] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[190] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[191] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[192] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[193] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[194] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[195] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[196] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[197] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[198] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[199] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[200] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[201] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[202] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[203] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[204] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[205] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[206] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[207] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[208] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[209] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[210] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[211] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[212] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[213] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[214] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[215] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[216] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[217] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[218] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[219] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[220] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[221] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[222] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[223] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[224] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[225] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[226] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[227] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[228] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[229] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[230] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[231] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[232] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[233] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[234] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[235] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[236] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[237] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[238] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[239] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[240] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[241] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[242] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[243] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[244] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[245] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[246] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[247] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[248] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[249] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[250] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[251] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[252] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[253] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[254] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[255] = 1U; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; + __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; + __Vtableidx5 = 0; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx6 = 0; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx7 = 0; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx8 = 0; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; 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+ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx9 = 0; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; 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+ __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx10 = 0; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; 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+ __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx11 = 0; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vtableidx12 = 0; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; + __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; + __Vm_traceActivity = 0; +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.h b/hw/unit_tests/cache/obj_dir/VVX_cache.h new file mode 100644 index 00000000..3fe788ef --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.h @@ -0,0 +1,1681 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Primary design header +// +// This header should be included by all source files instantiating the design. +// The class here is then constructed to instantiate the design. +// See the Verilator manual for examples. + +#ifndef _VVX_CACHE_H_ +#define _VVX_CACHE_H_ // guard + +#include "verilated_heavy.h" + +//========== + +class VVX_cache__Syms; +class VVX_cache_VerilatedVcd; + + +//---------- + +VL_MODULE(VVX_cache) { + public: + + // PORTS + // The application code writes and reads these signals to + // propagate new values into/out from the Verilated model. + VL_IN8(clk,0,0); + VL_IN8(reset,0,0); + VL_IN8(core_req_valid,3,0); + VL_IN8(core_req_rw,3,0); + VL_IN16(core_req_byteen,15,0); + VL_OUT8(core_req_ready,0,0); + VL_OUT8(core_rsp_valid,3,0); + VL_IN8(core_rsp_ready,0,0); + VL_OUT8(dram_req_valid,0,0); + VL_OUT8(dram_req_rw,0,0); + VL_IN8(dram_req_ready,0,0); + VL_IN8(dram_rsp_valid,0,0); + VL_OUT8(dram_rsp_ready,0,0); + VL_IN8(snp_req_valid,0,0); + VL_IN8(snp_req_invalidate,0,0); + VL_OUT8(snp_req_ready,0,0); + VL_OUT8(snp_rsp_valid,0,0); + VL_IN8(snp_rsp_ready,0,0); + VL_OUT8(snp_fwdout_valid,1,0); + VL_OUT8(snp_fwdout_invalidate,1,0); + VL_OUT8(snp_fwdout_tag,1,0); + VL_IN8(snp_fwdout_ready,1,0); + VL_IN8(snp_fwdin_valid,1,0); + VL_IN8(snp_fwdin_tag,1,0); + VL_OUT8(snp_fwdin_ready,1,0); + VL_OUT16(dram_req_byteen,15,0); + VL_INW(core_req_addr,119,0,4); + VL_INW(core_req_data,127,0,4); + VL_OUTW(core_rsp_data,127,0,4); + VL_OUT(dram_req_addr,27,0); + VL_OUTW(dram_req_data,127,0,4); + VL_OUT(dram_req_tag,27,0); + VL_INW(dram_rsp_data,127,0,4); + VL_IN(dram_rsp_tag,27,0); + VL_IN(snp_req_addr,27,0); + VL_IN(snp_req_tag,27,0); + VL_OUT(snp_rsp_tag,27,0); + VL_OUT64(snp_fwdout_addr,55,0); + VL_IN64(core_req_tag,41,0); + VL_OUT64(core_rsp_tag,41,0); + + // LOCAL SIGNALS + // Internals; generally not touched by application code + // Anonymous structures to workaround compiler member-count bugs + struct { + CData/*7:0*/ VX_cache__DOT__per_bank_core_req_ready; + CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_valid; + SData/*15:0*/ VX_cache__DOT__per_bank_core_rsp_tid; + CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_ready; + CData/*7:0*/ VX_cache__DOT__per_bank_dram_fill_req_valid; + CData/*7:0*/ VX_cache__DOT__per_bank_dram_fill_rsp_ready; + CData/*7:0*/ VX_cache__DOT__per_bank_dram_wb_req_ready; + CData/*7:0*/ VX_cache__DOT__per_bank_dram_wb_req_valid; + CData/*7:0*/ VX_cache__DOT__per_bank_snp_req_ready; + CData/*7:0*/ VX_cache__DOT__per_bank_snp_rsp_valid; + CData/*7:0*/ VX_cache__DOT__per_bank_snp_rsp_ready; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid; + CData/*7:0*/ VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop; + CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; + CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid; + CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; + CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing; + CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; + CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; + }; + struct { + CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; + CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r; + CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual; + CData/*2:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index; + CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid; + CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; + CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value; + CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill; + CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original; + CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; + CData/*2:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank; + CData/*0:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; + CData/*7:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; + CData/*4:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading; 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+ WData/*84:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[1]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[1]; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[1]; + IData/*31:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[1]; + QData/*48:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[1][4]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[1]; + }; + struct { + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[1]; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; + IData/*20:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; + IData/*20:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; + WData/*84:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[1]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[1]; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[1]; + IData/*31:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[1]; + QData/*48:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[1][4]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[1]; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; + CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; + IData/*20:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; + IData/*20:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; + WData/*84:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + }; + + // LOCAL VARIABLES + // Internals; generally not touched by application code + // Anonymous structures to workaround compiler member-count bugs + struct { + IData/*31:0*/ VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid; + CData/*7:0*/ __Vtableidx1; + CData/*7:0*/ __Vtableidx2; + CData/*7:0*/ __Vtableidx3; + CData/*7:0*/ __Vtableidx4; + CData/*3:0*/ __Vtableidx5; + CData/*3:0*/ __Vtableidx6; + CData/*3:0*/ __Vtableidx7; + CData/*3:0*/ __Vtableidx8; + CData/*3:0*/ __Vtableidx9; + CData/*3:0*/ __Vtableidx10; + CData/*3:0*/ __Vtableidx11; + CData/*3:0*/ __Vtableidx12; + CData/*0:0*/ __Vclklast__TOP__clk; + WData/*127:0*/ VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[4]; + WData/*231:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[8]; + WData/*231:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[8]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + }; + struct { + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*152:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*241:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*315:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*198:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; + WData/*166:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*24:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + IData/*31:0*/ __Vm_traceActivity; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + }; + struct { + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + }; + static CData/*2:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[256]; + static CData/*0:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[256]; + static IData/*31:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; + static CData/*2:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[256]; + static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[256]; + static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; + static CData/*2:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[256]; + static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[256]; + static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; + static CData/*2:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[256]; + static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[256]; + static IData/*31:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; + static CData/*1:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + + // INTERNAL VARIABLES + // Internals; generally not touched by application code + VVX_cache__Syms* __VlSymsp; // Symbol table + + // CONSTRUCTORS + private: + VL_UNCOPYABLE(VVX_cache); ///< Copying not allowed + public: + /// Construct the model; called by application code + /// The special name may be used to make a wrapper with a + /// single model invisible with respect to DPI scope names. + VVX_cache(const char* name = "TOP"); + /// Destroy the model; called (often implicitly) by application code + ~VVX_cache(); + /// Trace signals in the model; called by application code + void trace(VerilatedVcdC* tfp, int levels, int options = 0); + + // API METHODS + /// Evaluate the model. Application must call when inputs change. + void eval() { eval_step(); } + /// Evaluate when calling multiple units/models per time step. + void eval_step(); + /// Evaluate at end of a timestep for tracing, when using eval_step(). + /// Application must call after all eval() and before time changes. + void eval_end_step() {} + /// Simulation complete, run final blocks. Application must call on completion. + void final(); + + // INTERNAL METHODS + private: + static void _eval_initial_loop(VVX_cache__Syms* __restrict vlSymsp); + public: + void __Vconfigure(VVX_cache__Syms* symsp, bool first); + private: + static QData _change_request(VVX_cache__Syms* __restrict vlSymsp); + public: + static void _combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp); + static void _combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp); + private: + void _ctor_var_reset() VL_ATTR_COLD; + public: + static void _eval(VVX_cache__Syms* __restrict vlSymsp); + private: +#ifdef VL_DEBUG + void _eval_debug_assertions(); +#endif // VL_DEBUG + public: + static void _eval_initial(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _eval_settle(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _initial__TOP__1(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void _sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp); + static void _settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) VL_ATTR_COLD; + static void traceChgThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__3(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceChgThis__6(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code); + static void traceFullThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInitThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) VL_ATTR_COLD; + static void traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code); + static void traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code); +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +//---------- + + +#endif // guard diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.mk b/hw/unit_tests/cache/obj_dir/VVX_cache.mk new file mode 100644 index 00000000..a00727e3 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.mk @@ -0,0 +1,67 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Makefile for building Verilated archive or executable +# +# Execute this makefile from the object directory: +# make -f VVX_cache.mk + +default: VVX_cache + +### Constants... +# Perl executable (from $PERL) +PERL = perl +# Path to Verilator kit (from $VERILATOR_ROOT) +VERILATOR_ROOT = /usr/local/share/verilator +# SystemC include directory with systemc.h (from $SYSTEMC_INCLUDE) +SYSTEMC_INCLUDE ?= +# SystemC library directory with libsystemc.a (from $SYSTEMC_LIBDIR) +SYSTEMC_LIBDIR ?= + +### Switches... +# SystemC output mode? 0/1 (from --sc) +VM_SC = 0 +# Legacy or SystemC output mode? 0/1 (from --sc) +VM_SP_OR_SC = $(VM_SC) +# Deprecated +VM_PCLI = 1 +# Deprecated: SystemC architecture to find link library path (from $SYSTEMC_ARCH) +VM_SC_TARGET_ARCH = linux + +### Vars... +# Design prefix (from --prefix) +VM_PREFIX = VVX_cache +# Module prefix (from --prefix) +VM_MODPREFIX = VVX_cache +# User CFLAGS (from -CFLAGS on Verilator command line) +VM_USER_CFLAGS = \ + -std=c++11 -fms-extensions -I../.. -DNDEBUG -DDATAW=4 -DSIZE=4 \ + +# User LDLIBS (from -LDFLAGS on Verilator command line) +VM_USER_LDLIBS = \ + +# User .cpp files (from .cpp's on Verilator command line) +VM_USER_CLASSES = \ + cache_sim \ + +# User .cpp directories (from .cpp's on Verilator command line) +VM_USER_DIR = \ + . \ + + +### Default rules... +# Include list of all generated classes +include VVX_cache_classes.mk +# Include global rules +include $(VERILATOR_ROOT)/include/verilated.mk + +### Executable rules... (from --exe) +VPATH += $(VM_USER_DIR) + +cache_sim.o: cache_sim.cpp + $(OBJCACHE) $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(OPT_FAST) -c -o $@ $< + +### Link rules... (from --exe) +VVX_cache: $(VK_USER_OBJS) $(VK_GLOBAL_OBJS) $(VM_PREFIX)__ALL.a + $(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) $(SC_LIBS) + + +# Verilated -*- Makefile -*- diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp new file mode 100644 index 00000000..35a510dc --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp @@ -0,0 +1,107 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table implementation internals + +#include "VVX_cache__Syms.h" +#include "VVX_cache.h" + + + +// FUNCTIONS +VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep) + // Setup locals + : __Vm_namep(namep) + , __Vm_activity(false) + , __Vm_didInit(false) + // Setup submodule names +{ + // Pointer to top level + TOPp = topp; + // Setup each module's pointers to their submodules + // Setup each module's pointer back to symbol table (for public functions) + TOPp->__Vconfigure(this, true); + // Setup scopes + __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue", "dfqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue", "pfq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[1].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[2].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); + __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h new file mode 100644 index 00000000..b6041fd0 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h @@ -0,0 +1,123 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Symbol table internal header +// +// Internal details; most calling programs do not need this header, +// unless using verilator public meta comments. + +#ifndef _VVX_CACHE__SYMS_H_ +#define _VVX_CACHE__SYMS_H_ // guard + +#include "verilated_heavy.h" + +// INCLUDE MODULE CLASSES +#include "VVX_cache.h" + +// SYMS CLASS +class VVX_cache__Syms : public VerilatedSyms { + public: + + // LOCAL STATE + const char* __Vm_namep; + bool __Vm_activity; ///< Used by trace routines to determine change occurred + bool __Vm_didInit; + + // SUBCELL STATE + VVX_cache* TOPp; + + // SCOPE NAMES + VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue; + VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue; + VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__1__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__2__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue; + VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2; + + // CREATORS + VVX_cache__Syms(VVX_cache* topp, const char* namep); + ~VVX_cache__Syms() {} + + // METHODS + inline const char* name() { return __Vm_namep; } + inline bool getClearActivity() { bool r=__Vm_activity; __Vm_activity=false; return r; } + +} VL_ATTR_ALIGNED(VL_CACHE_LINE_BYTES); + +#endif // guard diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp new file mode 100644 index 00000000..956c0c84 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp @@ -0,0 +1,9560 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "VVX_cache__Syms.h" + + +//====================== + +void VVX_cache::traceChg(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + VVX_cache* t = (VVX_cache*)userthis; + VVX_cache__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (vlSymsp->getClearActivity()) { + t->traceChgThis(vlSymsp, vcdp, code); + } +} + +//====================== + + +void VVX_cache::traceChgThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U))))) { + vlTOPp->traceChgThis__2(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & ((vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 1U)) | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__3(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((1U & (vlTOPp->__Vm_traceActivity + | (vlTOPp->__Vm_traceActivity + >> 2U))))) { + vlTOPp->traceChgThis__4(vlSymsp, vcdp, code); + } + if (VL_UNLIKELY((4U & vlTOPp->__Vm_traceActivity))) { + vlTOPp->traceChgThis__5(vlSymsp, vcdp, code); + } + vlTOPp->traceChgThis__6(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void VVX_cache::traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBus(c+1,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid),32); + vcdp->chgBus(c+9,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready),8); + vcdp->chgBus(c+17,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready),8); + vcdp->chgBus(c+25,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready),8); + vcdp->chgBus(c+33,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+41,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)))); + vcdp->chgBit(c+49,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)))); + vcdp->chgBit(c+57,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)))); + vcdp->chgBus(c+65,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+73,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)))); + vcdp->chgBit(c+81,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)))); + vcdp->chgBit(c+89,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)))); + vcdp->chgBus(c+97,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+105,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)))); + vcdp->chgBit(c+113,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)))); + vcdp->chgBit(c+121,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)))); + vcdp->chgBus(c+129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+137,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)))); + vcdp->chgBit(c+145,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)))); + vcdp->chgBit(c+153,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)))); + vcdp->chgBus(c+161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+169,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 4U)))); + vcdp->chgBit(c+177,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 4U)))); + vcdp->chgBit(c+185,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 4U)))); + vcdp->chgBus(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+201,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 5U)))); + vcdp->chgBit(c+209,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 5U)))); + vcdp->chgBit(c+217,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 5U)))); + vcdp->chgBus(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+233,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 6U)))); + vcdp->chgBit(c+241,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 6U)))); + vcdp->chgBit(c+249,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 6U)))); + vcdp->chgBus(c+257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid),4); + vcdp->chgBit(c+265,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 7U)))); + vcdp->chgBit(c+273,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 7U)))); + vcdp->chgBit(c+281,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 7U)))); + vcdp->chgBus(c+289,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),8); + vcdp->chgBit(c+297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); + vcdp->chgBit(c+305,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); + vcdp->chgBit(c+313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+401,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+1057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+1065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+1073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+1081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+1089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+1097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+1113,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+1121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+1161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+1169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+1249,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+1257,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+1265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+1273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+1281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+1289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+1305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+1313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+1353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+1361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+1441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+1449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+1457,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+1465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+1473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+1497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+1505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+1545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+1553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+1633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+1641,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+1649,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+1657,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+1665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+1673,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->chgBit(c+1689,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+1697,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->chgBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+1745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+1825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+1833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+1841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + } +} + +void VVX_cache::traceChgThis__3(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBit(c+1849,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U + != + (0xffU + & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); + vcdp->chgBit(c+1857,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1865,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); + vcdp->chgBit(c+1873,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+1881,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1889,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1897,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U))))); + vcdp->chgBit(c+1905,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+1913,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1921,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1929,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U))))); + vcdp->chgBit(c+1937,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+1945,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1953,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1961,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U))))); + vcdp->chgBit(c+1969,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+1977,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1985,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1993,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 4U))))); + vcdp->chgBit(c+2001,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+2009,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+2017,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+2025,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 5U))))); + vcdp->chgBit(c+2033,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+2041,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+2049,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+2057,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 6U))))); + vcdp->chgBit(c+2065,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+2073,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+2081,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+2089,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 7U))))); + vcdp->chgBit(c+2097,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+2105,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + } +} + +void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*127:0*/ __Vtemp1366[4]; + WData/*127:0*/ __Vtemp1385[4]; + WData/*127:0*/ __Vtemp1404[4]; + WData/*127:0*/ __Vtemp1423[4]; + WData/*127:0*/ __Vtemp1442[4]; + WData/*127:0*/ __Vtemp1461[4]; + WData/*127:0*/ __Vtemp1480[4]; + WData/*127:0*/ __Vtemp1499[4]; + WData/*127:0*/ __Vtemp1339[4]; + WData/*127:0*/ __Vtemp1340[4]; + WData/*127:0*/ __Vtemp1341[4]; + WData/*127:0*/ __Vtemp1342[4]; + WData/*127:0*/ __Vtemp1343[4]; + WData/*127:0*/ __Vtemp1344[4]; + WData/*127:0*/ __Vtemp1345[4]; + WData/*127:0*/ __Vtemp1346[4]; + WData/*223:0*/ __Vtemp1347[7]; + WData/*127:0*/ __Vtemp1348[4]; + WData/*127:0*/ __Vtemp1353[4]; + WData/*127:0*/ __Vtemp1359[4]; + WData/*127:0*/ __Vtemp1360[4]; + WData/*127:0*/ __Vtemp1363[4]; + WData/*127:0*/ __Vtemp1364[4]; + WData/*127:0*/ __Vtemp1365[4]; + WData/*127:0*/ __Vtemp1367[4]; + WData/*127:0*/ __Vtemp1372[4]; + WData/*127:0*/ __Vtemp1378[4]; + WData/*127:0*/ __Vtemp1379[4]; + WData/*127:0*/ __Vtemp1382[4]; + WData/*127:0*/ __Vtemp1383[4]; + WData/*127:0*/ __Vtemp1384[4]; + WData/*127:0*/ __Vtemp1386[4]; + WData/*127:0*/ __Vtemp1391[4]; + WData/*127:0*/ __Vtemp1397[4]; + WData/*127:0*/ __Vtemp1398[4]; + WData/*127:0*/ __Vtemp1401[4]; + WData/*127:0*/ __Vtemp1402[4]; + WData/*127:0*/ __Vtemp1403[4]; + WData/*127:0*/ __Vtemp1405[4]; + WData/*127:0*/ __Vtemp1410[4]; + WData/*127:0*/ __Vtemp1416[4]; + WData/*127:0*/ __Vtemp1417[4]; + WData/*127:0*/ __Vtemp1420[4]; + WData/*127:0*/ __Vtemp1421[4]; + WData/*127:0*/ __Vtemp1422[4]; + WData/*127:0*/ __Vtemp1424[4]; + WData/*127:0*/ __Vtemp1429[4]; + WData/*127:0*/ __Vtemp1435[4]; + WData/*127:0*/ __Vtemp1436[4]; + WData/*127:0*/ __Vtemp1439[4]; + WData/*127:0*/ __Vtemp1440[4]; + WData/*127:0*/ __Vtemp1441[4]; + WData/*127:0*/ __Vtemp1443[4]; + WData/*127:0*/ __Vtemp1448[4]; + WData/*127:0*/ __Vtemp1454[4]; + WData/*127:0*/ __Vtemp1455[4]; + WData/*127:0*/ __Vtemp1458[4]; + WData/*127:0*/ __Vtemp1459[4]; + WData/*127:0*/ __Vtemp1460[4]; + WData/*127:0*/ __Vtemp1462[4]; + WData/*127:0*/ __Vtemp1467[4]; + WData/*127:0*/ __Vtemp1473[4]; + WData/*127:0*/ __Vtemp1474[4]; + WData/*127:0*/ __Vtemp1477[4]; + WData/*127:0*/ __Vtemp1478[4]; + WData/*127:0*/ __Vtemp1479[4]; + WData/*127:0*/ __Vtemp1481[4]; + WData/*127:0*/ __Vtemp1486[4]; + WData/*127:0*/ __Vtemp1492[4]; + WData/*127:0*/ __Vtemp1493[4]; + WData/*127:0*/ __Vtemp1496[4]; + WData/*127:0*/ __Vtemp1497[4]; + WData/*127:0*/ __Vtemp1498[4]; + // Body + { + vcdp->chgBus(c+2113,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),8); + vcdp->chgBus(c+2121,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),8); + vcdp->chgBus(c+2129,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),16); + vcdp->chgArray(c+2137,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),256); + vcdp->chgArray(c+2201,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),336); + vcdp->chgBus(c+2289,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),8); + vcdp->chgArray(c+2297,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),224); + vcdp->chgBus(c+2353,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),8); + vcdp->chgBus(c+2361,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),8); + vcdp->chgArray(c+2369,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),128); + vcdp->chgArray(c+2401,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),224); + vcdp->chgArray(c+2457,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),1024); + vcdp->chgBus(c+2713,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),8); + vcdp->chgBus(c+2721,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),8); + vcdp->chgArray(c+2729,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),224); + vcdp->chgBus(c+2785,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+2801,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+2817,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+2833,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+2841,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1339[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1339[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1339[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1339[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+2849,(__Vtemp1339),128); + vcdp->chgBit(c+2881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+2889,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+2897,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+2913,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+2929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+2937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+2945,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+2953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1340[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1340[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1340[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1340[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+2961,(__Vtemp1340),128); + vcdp->chgBit(c+2993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+3001,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+3009,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+3025,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+3041,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+3057,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+3065,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1341[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1341[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1341[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1341[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+3073,(__Vtemp1341),128); + vcdp->chgBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+3113,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+3121,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+3137,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+3153,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+3169,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+3177,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1342[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1342[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1342[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1342[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+3185,(__Vtemp1342),128); + vcdp->chgBit(c+3217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+3225,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+3233,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+3241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+3249,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+3265,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+3273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+3281,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+3289,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1343[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1343[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1343[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1343[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+3297,(__Vtemp1343),128); + vcdp->chgBit(c+3329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+3337,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+3345,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+3361,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+3377,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+3385,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+3393,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+3401,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1344[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1344[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1344[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1344[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+3409,(__Vtemp1344),128); + vcdp->chgBit(c+3441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+3449,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+3457,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+3473,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+3489,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+3497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+3505,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+3513,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1345[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1345[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1345[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1345[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+3521,(__Vtemp1345),128); + vcdp->chgBit(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+3561,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+3569,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->chgBus(c+3577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+3585,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->chgBit(c+3601,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->chgBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+3617,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->chgBus(c+3625,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp1346[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp1346[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp1346[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp1346[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+3633,(__Vtemp1346),128); + vcdp->chgBit(c+3665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+3673,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBit(c+3681,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); + vcdp->chgBit(c+3689,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vcdp->chgBus(c+3697,(((0xdfU >= (0xffU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? (0xfffffffU & (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + : 0U)),28); + vcdp->chgBit(c+3705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+3713,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); + vcdp->chgBus(c+3721,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),3); + vcdp->chgBit(c+3729,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); + vcdp->chgBit(c+3737,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); + vcdp->chgBit(c+3745,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); + vcdp->chgBus(c+3753,((0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])),8); + __Vtemp1347[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; + __Vtemp1347[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; + __Vtemp1347[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; + __Vtemp1347[3U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]; + __Vtemp1347[4U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]; + __Vtemp1347[5U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]; + __Vtemp1347[6U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]; + vcdp->chgArray(c+3761,(__Vtemp1347),224); + vcdp->chgBus(c+3817,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),8); + vcdp->chgArray(c+3825,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),224); + vcdp->chgBus(c+3881,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),8); + vcdp->chgBit(c+3889,((1U & ((~ (IData)((0U + != + (0xffU + & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+3897,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+3905,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),3); + vcdp->chgBit(c+3913,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); + vcdp->chgArray(c+3921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),232); + vcdp->chgArray(c+3985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),232); + vcdp->chgBit(c+4049,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); + vcdp->chgBus(c+4057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->chgBus(c+4065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBus(c+4073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->chgBus(c+4081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+4089,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); + vcdp->chgQuad(c+4121,(((0x14fU >= (0x1ffU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) + : ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0))),42); + vcdp->chgBus(c+4137,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),8); + vcdp->chgBus(c+4145,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),3); + vcdp->chgBit(c+4153,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); + vcdp->chgBus(c+4161,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->chgBus(c+4169,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),8); + vcdp->chgBus(c+4177,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),8); + vcdp->chgBus(c+4185,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBus(c+4193,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),3); + vcdp->chgBit(c+4201,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); + vcdp->chgBus(c+4209,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->chgBus(c+4217,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBit(c+4225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+4233,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+4241,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+4249,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+4257,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+4265,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1348[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1348[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1348[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1348[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+4273,(__Vtemp1348),128); + vcdp->chgBit(c+4305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+4313,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+4321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+4329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+4337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+4345,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+4353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+4361,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+4369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+4393,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+4401,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+4417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+4449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+4457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+4513,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+4521,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+4529,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+4537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1353[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1353[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1353[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1353[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+4545,(__Vtemp1353),128); + vcdp->chgQuad(c+4577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+4601,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+4609,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+4617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+4625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+4633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+4641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+4649,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+4665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+4713,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1359[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1359[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1359[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1359[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+4721,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1359[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1359[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1360[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1360[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1360[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1360[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+4729,(__Vtemp1360),128); + vcdp->chgBus(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+4777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+4785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+4793,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+4809,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+4817,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+4825,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+4833,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+4849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+4857,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+4865,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+4873,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+4881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+4889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+4897,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+4913,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+4921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+4929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+4937,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+4953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+4969,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+4985,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+5017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+5025,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+5041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+5105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+5113,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+5121,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+5129,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1363[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1363[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1363[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1363[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+5137,(__Vtemp1363),120); + __Vtemp1364[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1364[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1364[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1364[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+5169,(__Vtemp1364),128); + vcdp->chgQuad(c+5201,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+5217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+5225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+5233,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+5241,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+5321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+5329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+5337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+5345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+5409,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+5417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+5425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1365[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1365[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1365[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1365[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+5433,(__Vtemp1365),128); + vcdp->chgBus(c+5465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+5489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+5497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+5505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+5537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+5545,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1366[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1366[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1366[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1366[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+5569,(__Vtemp1366),128); + vcdp->chgBit(c+5601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+5625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+5681,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+5689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+5697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+5705,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+5713,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+5729,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+5737,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5745,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5753,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5761,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+5769,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+5777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+5825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+5905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+5913,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+5921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+5929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+5937,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+5945,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+5953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+5961,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+5969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+6001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+6025,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+6153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+6161,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+6169,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+6177,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+6185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+6193,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1367[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1367[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1367[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1367[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+6201,(__Vtemp1367),128); + vcdp->chgBit(c+6233,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+6241,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+6249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+6257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+6265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+6273,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+6281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+6289,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+6297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+6321,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+6329,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+6345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+6377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+6385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+6441,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+6449,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+6457,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+6465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1372[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1372[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1372[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1372[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+6473,(__Vtemp1372),128); + vcdp->chgQuad(c+6505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+6529,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+6537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+6545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+6553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+6561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+6569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+6577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+6593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+6641,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1378[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1378[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1378[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1378[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+6649,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1378[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1378[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1379[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1379[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1379[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1379[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+6657,(__Vtemp1379),128); + vcdp->chgBus(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+6705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+6713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+6721,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+6737,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+6745,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+6753,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+6761,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+6777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+6785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+6793,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+6801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+6809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+6817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+6825,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+6841,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+6849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+6857,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+6865,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+6881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+6897,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+6913,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+6945,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+6953,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+6969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+7033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+7041,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+7049,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+7057,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1382[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1382[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1382[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1382[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+7065,(__Vtemp1382),120); + __Vtemp1383[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1383[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1383[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1383[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+7097,(__Vtemp1383),128); + vcdp->chgQuad(c+7129,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+7145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+7153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+7161,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+7169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+7249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+7257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+7265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+7273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+7337,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+7345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+7353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1384[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1384[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1384[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1384[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+7361,(__Vtemp1384),128); + vcdp->chgBus(c+7393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+7417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+7425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+7433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+7465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+7473,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1385[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1385[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1385[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1385[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+7497,(__Vtemp1385),128); + vcdp->chgBit(c+7529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+7553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+7609,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+7617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+7625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+7633,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+7641,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+7657,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+7665,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7673,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7681,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7689,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+7697,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+7753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+7833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+7841,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+7849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+7857,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+7865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+7873,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+7881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+7889,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+7897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+7929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+7953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+7961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+8017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+8073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+8081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+8089,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+8097,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+8105,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+8113,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+8121,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1386[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1386[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1386[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1386[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+8129,(__Vtemp1386),128); + vcdp->chgBit(c+8161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+8169,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+8177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+8185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+8193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+8201,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+8209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+8217,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+8225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+8233,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+8241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+8249,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+8257,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+8265,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+8273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+8305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+8313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+8369,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+8377,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+8385,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+8393,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1391[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1391[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1391[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1391[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+8401,(__Vtemp1391),128); + vcdp->chgQuad(c+8433,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+8457,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+8465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+8473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+8481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+8489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+8497,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+8505,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+8521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+8569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1397[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1397[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1397[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1397[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+8577,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1397[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1397[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1398[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1398[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1398[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1398[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+8585,(__Vtemp1398),128); + vcdp->chgBus(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+8633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+8641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+8649,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+8665,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+8673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+8681,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+8689,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+8705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+8713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+8721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+8729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+8737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+8745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+8753,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+8769,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+8777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+8785,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+8793,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+8809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+8825,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+8841,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+8873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+8881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+8897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+8961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+8969,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+8977,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+8985,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1401[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1401[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1401[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1401[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+8993,(__Vtemp1401),120); + __Vtemp1402[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1402[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1402[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1402[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+9025,(__Vtemp1402),128); + vcdp->chgQuad(c+9057,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+9073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+9081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+9089,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+9097,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+9177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+9185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+9193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+9201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+9265,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+9273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+9281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1403[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1403[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1403[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1403[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+9289,(__Vtemp1403),128); + vcdp->chgBus(c+9321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+9345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+9353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+9361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+9393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+9401,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1404[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1404[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1404[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1404[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+9425,(__Vtemp1404),128); + vcdp->chgBit(c+9457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+9481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+9537,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+9545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+9553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+9561,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+9569,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+9585,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+9593,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9601,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9609,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9617,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9625,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+9681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+9761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+9769,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+9777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+9785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+9793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+9801,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+9809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+9817,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+9825,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+9833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+9857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+9881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+9889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+9945,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+10001,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+10009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+10017,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+10025,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+10033,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+10041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+10049,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1405[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1405[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1405[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1405[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+10057,(__Vtemp1405),128); + vcdp->chgBit(c+10089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+10097,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+10105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+10113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+10121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+10129,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+10137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+10145,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+10153,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+10161,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+10169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+10177,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+10185,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+10193,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+10201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+10209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+10217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+10225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+10233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+10241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+10249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+10257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+10265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+10273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+10281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+10289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+10297,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+10305,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+10313,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+10321,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1410[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1410[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1410[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1410[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+10329,(__Vtemp1410),128); + vcdp->chgQuad(c+10361,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+10377,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+10385,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+10393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+10401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+10409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+10417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+10425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+10433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+10449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+10481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+10489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+10497,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1416[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1416[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1416[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1416[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+10505,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1416[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1416[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1417[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1417[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1417[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1417[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+10513,(__Vtemp1417),128); + vcdp->chgBus(c+10545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+10553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+10561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+10569,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+10577,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+10593,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+10601,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+10609,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+10617,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+10625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+10633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+10641,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+10649,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+10657,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+10665,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+10673,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+10681,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+10689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+10697,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+10705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+10713,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+10721,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+10729,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+10737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+10745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+10753,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+10761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+10769,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+10777,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+10785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+10793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+10801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+10809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+10817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+10825,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+10841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+10849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+10889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+10897,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+10905,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+10913,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1420[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1420[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1420[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1420[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+10921,(__Vtemp1420),120); + __Vtemp1421[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1421[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1421[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1421[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+10953,(__Vtemp1421),128); + vcdp->chgQuad(c+10985,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+11001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+11009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+11017,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+11025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+11105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+11113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+11121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+11129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+11193,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+11201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+11209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1422[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1422[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1422[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1422[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+11217,(__Vtemp1422),128); + vcdp->chgBus(c+11249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+11257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+11265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+11273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+11281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+11289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+11321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+11329,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+11337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+11345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1423[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1423[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1423[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1423[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+11353,(__Vtemp1423),128); + vcdp->chgBit(c+11385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+11393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+11401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+11409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+11441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+11449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+11457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+11465,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+11473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+11481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+11489,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+11497,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+11505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+11513,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+11521,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+11529,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+11537,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+11545,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+11553,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+11561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+11609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+11689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+11697,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+11705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+11713,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+11721,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+11729,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+11737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+11745,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+11753,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+11761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+11785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+11809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+11817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+11873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+11929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+11937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+11945,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+11953,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+11961,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+11969,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+11977,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1424[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1424[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1424[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1424[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+11985,(__Vtemp1424),128); + vcdp->chgBit(c+12017,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+12025,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+12033,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+12041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+12049,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+12057,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+12065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+12073,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+12081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+12089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+12097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+12105,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+12113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+12121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+12129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+12137,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+12145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+12153,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+12161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+12169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+12177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+12185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+12193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+12201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+12209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+12217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+12225,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+12233,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+12241,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+12249,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1429[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1429[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1429[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1429[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+12257,(__Vtemp1429),128); + vcdp->chgQuad(c+12289,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+12305,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+12313,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+12321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+12329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+12337,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+12345,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+12353,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+12361,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+12377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+12409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+12417,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+12425,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1435[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1435[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1435[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1435[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+12433,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1435[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1435[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1436[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1436[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1436[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1436[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+12441,(__Vtemp1436),128); + vcdp->chgBus(c+12473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+12481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+12489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+12497,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+12505,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+12521,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+12529,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+12537,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+12545,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+12553,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+12561,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+12569,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+12577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+12585,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+12593,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+12601,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+12609,((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+12617,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+12625,((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+12633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+12641,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+12649,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+12657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+12665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+12673,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+12681,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+12689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+12697,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+12705,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+12713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+12721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+12729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+12737,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+12745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+12753,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+12769,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+12777,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+12817,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+12825,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+12833,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+12841,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1439[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1439[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1439[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1439[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+12849,(__Vtemp1439),120); + __Vtemp1440[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1440[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1440[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1440[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+12881,(__Vtemp1440),128); + vcdp->chgQuad(c+12913,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+12929,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+12937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+12945,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+12953,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+13033,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+13041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+13049,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+13057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+13121,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+13129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+13137,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1441[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1441[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1441[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1441[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+13145,(__Vtemp1441),128); + vcdp->chgBus(c+13177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+13185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+13193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+13201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+13209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+13217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+13249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+13257,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+13265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+13273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1442[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1442[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1442[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1442[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+13281,(__Vtemp1442),128); + vcdp->chgBit(c+13313,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+13321,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+13329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+13337,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+13369,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+13377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+13385,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+13393,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+13401,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+13409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+13417,((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+13425,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+13433,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+13441,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+13449,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+13457,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+13465,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+13473,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+13481,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+13489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+13537,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+13617,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+13625,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+13633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+13649,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+13657,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+13673,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+13681,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+13713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+13737,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+13745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+13801,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+13857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+13865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+13873,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+13881,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+13889,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+13897,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+13905,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1443[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1443[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1443[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1443[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+13913,(__Vtemp1443),128); + vcdp->chgBit(c+13945,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+13953,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+13961,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+13969,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+13977,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+13985,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+13993,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+14001,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+14009,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+14017,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+14025,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+14033,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+14041,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+14049,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+14121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+14129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+14137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+14145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+14153,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+14161,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+14169,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+14177,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1448[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1448[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1448[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1448[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+14185,(__Vtemp1448),128); + vcdp->chgQuad(c+14217,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+14233,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+14241,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+14249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+14257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+14265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+14273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+14281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+14289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+14305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+14337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+14345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+14353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1454[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1454[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1454[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1454[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+14361,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1454[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1454[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1455[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1455[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1455[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1455[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+14369,(__Vtemp1455),128); + vcdp->chgBus(c+14401,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+14409,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+14417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+14425,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+14433,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+14449,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+14457,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+14465,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+14473,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+14481,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+14489,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+14497,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+14505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+14513,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+14521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+14529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+14537,((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+14545,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+14553,((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+14561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+14569,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+14577,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+14585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+14593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+14601,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+14609,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+14617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+14625,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+14633,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+14641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+14649,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+14657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+14665,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+14673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+14681,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+14697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+14705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+14745,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+14753,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+14761,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+14769,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1458[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1458[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1458[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1458[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+14777,(__Vtemp1458),120); + __Vtemp1459[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1459[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1459[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1459[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+14809,(__Vtemp1459),128); + vcdp->chgQuad(c+14841,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+14857,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+14873,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+14881,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+14961,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+14969,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+14977,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+14985,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+15049,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+15057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+15065,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1460[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1460[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1460[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1460[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+15073,(__Vtemp1460),128); + vcdp->chgBus(c+15105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+15113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+15121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+15129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+15137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+15145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+15177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+15185,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+15193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+15201,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1461[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1461[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1461[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1461[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+15209,(__Vtemp1461),128); + vcdp->chgBit(c+15241,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+15249,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+15257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+15265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+15297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+15305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+15313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+15321,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+15329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+15337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+15345,((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+15353,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+15361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+15369,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+15377,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+15385,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+15393,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+15401,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+15409,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+15417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+15465,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+15545,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+15553,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+15585,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+15601,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+15609,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+15617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+15641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+15673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+15729,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+15785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+15793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+15801,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+15809,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+15817,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+15825,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+15833,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1462[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1462[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1462[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1462[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+15841,(__Vtemp1462),128); + vcdp->chgBit(c+15873,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+15881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+15889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+15897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+15905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+15913,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+15921,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+15929,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+15937,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+15945,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+15953,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+15961,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+15969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+15977,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+15985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+15993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+16001,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+16009,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+16017,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+16025,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+16033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+16041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+16049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+16057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+16065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+16073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+16081,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+16089,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+16097,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+16105,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1467[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1467[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1467[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1467[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+16113,(__Vtemp1467),128); + vcdp->chgQuad(c+16145,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+16161,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+16169,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+16177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+16185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+16193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+16201,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+16209,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+16217,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+16233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+16265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+16273,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+16281,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1473[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1473[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1473[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1473[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+16289,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1473[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1473[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1474[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1474[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1474[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1474[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+16297,(__Vtemp1474),128); + vcdp->chgBus(c+16329,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+16337,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+16345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+16353,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+16361,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+16377,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+16385,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+16393,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+16401,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+16409,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+16417,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+16425,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+16433,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+16441,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+16449,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+16457,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+16465,((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+16473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+16481,((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+16489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+16497,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+16505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+16513,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+16521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+16529,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+16537,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+16545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+16553,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+16561,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+16569,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+16577,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+16585,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+16593,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+16601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+16609,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+16625,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+16633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+16673,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+16681,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+16689,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+16697,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1477[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1477[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1477[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1477[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+16705,(__Vtemp1477),120); + __Vtemp1478[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1478[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1478[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1478[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+16737,(__Vtemp1478),128); + vcdp->chgQuad(c+16769,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+16785,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+16793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+16801,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+16809,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+16889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+16897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+16905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+16913,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+16977,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+16985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+16993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1479[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1479[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1479[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1479[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+17001,(__Vtemp1479),128); + vcdp->chgBus(c+17033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+17041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+17049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+17057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+17065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+17073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+17105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+17113,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+17121,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+17129,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1480[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1480[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1480[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1480[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+17137,(__Vtemp1480),128); + vcdp->chgBit(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+17185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+17193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+17225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+17233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+17241,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+17249,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+17257,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+17265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+17273,((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+17281,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+17289,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+17297,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+17305,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+17313,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+17321,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+17329,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+17337,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+17345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+17393,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+17473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+17481,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+17489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+17497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+17505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+17513,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+17529,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+17537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+17593,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+17601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+17657,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+17713,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+17721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+17729,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->chgBit(c+17737,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+17745,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+17753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+17761,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1481[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1481[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1481[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1481[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+17769,(__Vtemp1481),128); + vcdp->chgBit(c+17801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+17809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+17817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+17825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+17833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+17841,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+17849,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+17857,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+17865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+17873,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+17881,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+17889,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+17897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+17905,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+17937,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+17945,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+17953,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+17961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+17969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+17977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+17985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+17993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+18001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+18009,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+18017,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->chgBus(c+18025,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+18033,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1486[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1486[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1486[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1486[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+18041,(__Vtemp1486),128); + vcdp->chgQuad(c+18073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+18089,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+18097,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+18105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+18113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+18121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->chgBus(c+18129,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+18137,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+18145,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+18161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+18193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+18201,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+18209,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1492[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1492[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1492[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1492[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgBus(c+18217,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1492[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1492[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1493[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1493[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1493[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1493[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+18225,(__Vtemp1493),128); + vcdp->chgBus(c+18257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->chgBit(c+18265,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+18273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+18281,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+18289,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+18305,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+18313,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+18321,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+18329,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+18337,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+18345,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+18353,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+18361,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+18369,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+18377,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+18385,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+18393,((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+18401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->chgBit(c+18409,((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+18417,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+18425,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+18433,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+18441,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+18449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+18457,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+18465,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+18473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+18481,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+18489,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+18497,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+18505,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+18513,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+18521,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->chgBit(c+18529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+18537,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->chgBit(c+18553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+18561,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->chgBit(c+18601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+18609,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+18617,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+18625,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1496[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1496[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1496[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1496[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+18633,(__Vtemp1496),120); + __Vtemp1497[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1497[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1497[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1497[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+18665,(__Vtemp1497),128); + vcdp->chgQuad(c+18697,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+18713,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+18721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+18729,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+18737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+18817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+18825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+18833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+18841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->chgBus(c+18905,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->chgBit(c+18913,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+18921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1498[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1498[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1498[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1498[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+18929,(__Vtemp1498),128); + vcdp->chgBus(c+18961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+18969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+18977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+18985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+18993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->chgArray(c+19001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+19033,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBit(c+19041,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->chgBus(c+19049,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+19057,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1499[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1499[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1499[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1499[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->chgArray(c+19065,(__Vtemp1499),128); + vcdp->chgBit(c+19097,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+19105,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+19113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+19121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+19153,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+19161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+19169,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+19177,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->chgBus(c+19185,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+19193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+19201,((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+19209,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+19217,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+19225,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+19233,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+19241,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+19249,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+19257,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+19265,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+19273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->chgArray(c+19321,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+19401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+19409,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+19417,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+19425,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+19433,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+19441,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+19449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+19457,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+19465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+19473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+19497,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+19521,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+19529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->chgArray(c+19585,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->chgBit(c+19641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + } +} + +void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*127:0*/ __Vtemp1508[4]; + WData/*127:0*/ __Vtemp1509[4]; + WData/*127:0*/ __Vtemp1510[4]; + WData/*127:0*/ __Vtemp1511[4]; + WData/*127:0*/ __Vtemp1512[4]; + WData/*127:0*/ __Vtemp1513[4]; + WData/*127:0*/ __Vtemp1514[4]; + WData/*127:0*/ __Vtemp1515[4]; + WData/*127:0*/ __Vtemp1516[4]; + WData/*127:0*/ __Vtemp1517[4]; + WData/*127:0*/ __Vtemp1518[4]; + WData/*127:0*/ __Vtemp1519[4]; + WData/*127:0*/ __Vtemp1520[4]; + WData/*127:0*/ __Vtemp1521[4]; + WData/*127:0*/ __Vtemp1522[4]; + WData/*127:0*/ __Vtemp1523[4]; + WData/*127:0*/ __Vtemp1532[4]; + WData/*127:0*/ __Vtemp1533[4]; + WData/*127:0*/ __Vtemp1534[4]; + WData/*127:0*/ __Vtemp1535[4]; + WData/*127:0*/ __Vtemp1536[4]; + WData/*127:0*/ __Vtemp1537[4]; + WData/*127:0*/ __Vtemp1538[4]; + WData/*127:0*/ __Vtemp1539[4]; + WData/*127:0*/ __Vtemp1540[4]; + WData/*127:0*/ __Vtemp1541[4]; + WData/*127:0*/ __Vtemp1542[4]; + WData/*127:0*/ __Vtemp1543[4]; + WData/*127:0*/ __Vtemp1544[4]; + WData/*127:0*/ __Vtemp1545[4]; + WData/*127:0*/ __Vtemp1546[4]; + WData/*127:0*/ __Vtemp1547[4]; + WData/*127:0*/ __Vtemp1556[4]; + WData/*127:0*/ __Vtemp1557[4]; + WData/*127:0*/ __Vtemp1558[4]; + WData/*127:0*/ __Vtemp1559[4]; + WData/*127:0*/ __Vtemp1560[4]; + WData/*127:0*/ __Vtemp1561[4]; + WData/*127:0*/ __Vtemp1562[4]; + WData/*127:0*/ __Vtemp1563[4]; + WData/*127:0*/ __Vtemp1564[4]; + WData/*127:0*/ __Vtemp1565[4]; + WData/*127:0*/ __Vtemp1566[4]; + WData/*127:0*/ __Vtemp1567[4]; + WData/*127:0*/ __Vtemp1568[4]; + WData/*127:0*/ __Vtemp1569[4]; + WData/*127:0*/ __Vtemp1570[4]; + WData/*127:0*/ __Vtemp1571[4]; + WData/*127:0*/ __Vtemp1580[4]; + WData/*127:0*/ __Vtemp1581[4]; + WData/*127:0*/ __Vtemp1582[4]; + WData/*127:0*/ __Vtemp1583[4]; + WData/*127:0*/ __Vtemp1584[4]; + WData/*127:0*/ __Vtemp1585[4]; + WData/*127:0*/ __Vtemp1586[4]; + WData/*127:0*/ __Vtemp1587[4]; + WData/*127:0*/ __Vtemp1588[4]; + WData/*127:0*/ __Vtemp1589[4]; + WData/*127:0*/ __Vtemp1590[4]; + WData/*127:0*/ __Vtemp1591[4]; + WData/*127:0*/ __Vtemp1592[4]; + WData/*127:0*/ __Vtemp1593[4]; + WData/*127:0*/ __Vtemp1594[4]; + WData/*127:0*/ __Vtemp1595[4]; + WData/*127:0*/ __Vtemp1604[4]; + WData/*127:0*/ __Vtemp1605[4]; + WData/*127:0*/ __Vtemp1606[4]; + WData/*127:0*/ __Vtemp1607[4]; + WData/*127:0*/ __Vtemp1608[4]; + WData/*127:0*/ __Vtemp1609[4]; + WData/*127:0*/ __Vtemp1610[4]; + WData/*127:0*/ __Vtemp1611[4]; + WData/*127:0*/ __Vtemp1612[4]; + WData/*127:0*/ __Vtemp1613[4]; + WData/*127:0*/ __Vtemp1614[4]; + WData/*127:0*/ __Vtemp1615[4]; + WData/*127:0*/ __Vtemp1616[4]; + WData/*127:0*/ __Vtemp1617[4]; + WData/*127:0*/ __Vtemp1618[4]; + WData/*127:0*/ __Vtemp1619[4]; + WData/*127:0*/ __Vtemp1628[4]; + WData/*127:0*/ __Vtemp1629[4]; + WData/*127:0*/ __Vtemp1630[4]; + WData/*127:0*/ __Vtemp1631[4]; + WData/*127:0*/ __Vtemp1632[4]; + WData/*127:0*/ __Vtemp1633[4]; + WData/*127:0*/ __Vtemp1634[4]; + WData/*127:0*/ __Vtemp1635[4]; + WData/*127:0*/ __Vtemp1636[4]; + WData/*127:0*/ __Vtemp1637[4]; + WData/*127:0*/ __Vtemp1638[4]; + WData/*127:0*/ __Vtemp1639[4]; + WData/*127:0*/ __Vtemp1640[4]; + WData/*127:0*/ __Vtemp1641[4]; + WData/*127:0*/ __Vtemp1642[4]; + WData/*127:0*/ __Vtemp1643[4]; + WData/*127:0*/ __Vtemp1652[4]; + WData/*127:0*/ __Vtemp1653[4]; + WData/*127:0*/ __Vtemp1654[4]; + WData/*127:0*/ __Vtemp1655[4]; + WData/*127:0*/ __Vtemp1656[4]; + WData/*127:0*/ __Vtemp1657[4]; + WData/*127:0*/ __Vtemp1658[4]; + WData/*127:0*/ __Vtemp1659[4]; + WData/*127:0*/ __Vtemp1660[4]; + WData/*127:0*/ __Vtemp1661[4]; + WData/*127:0*/ __Vtemp1662[4]; + WData/*127:0*/ __Vtemp1663[4]; + WData/*127:0*/ __Vtemp1664[4]; + WData/*127:0*/ __Vtemp1665[4]; + WData/*127:0*/ __Vtemp1666[4]; + WData/*127:0*/ __Vtemp1667[4]; + WData/*127:0*/ __Vtemp1676[4]; + WData/*127:0*/ __Vtemp1677[4]; + WData/*127:0*/ __Vtemp1678[4]; + WData/*127:0*/ __Vtemp1679[4]; + WData/*127:0*/ __Vtemp1680[4]; + WData/*127:0*/ __Vtemp1681[4]; + WData/*127:0*/ __Vtemp1682[4]; + WData/*127:0*/ __Vtemp1683[4]; + WData/*127:0*/ __Vtemp1684[4]; + WData/*127:0*/ __Vtemp1685[4]; + WData/*127:0*/ __Vtemp1686[4]; + WData/*127:0*/ __Vtemp1687[4]; + WData/*127:0*/ __Vtemp1688[4]; + WData/*127:0*/ __Vtemp1689[4]; + WData/*127:0*/ __Vtemp1690[4]; + WData/*127:0*/ __Vtemp1691[4]; + WData/*127:0*/ __Vtemp1507[4]; + WData/*127:0*/ __Vtemp1531[4]; + WData/*127:0*/ __Vtemp1555[4]; + WData/*127:0*/ __Vtemp1579[4]; + WData/*127:0*/ __Vtemp1603[4]; + WData/*127:0*/ __Vtemp1627[4]; + WData/*127:0*/ __Vtemp1651[4]; + WData/*127:0*/ __Vtemp1675[4]; + // Body + { + vcdp->chgBit(c+19649,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19657,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19665,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19673,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19681,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19689,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19697,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19713,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19721,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19729,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19737,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19745,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19753,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19761,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19769,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19777,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19785,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19793,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19801,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19817,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19825,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19833,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19841,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19849,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19857,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19865,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19873,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19889,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19897,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19905,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19913,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19921,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19929,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19937,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+19945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->chgBit(c+19961,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+19969,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+19977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); + vcdp->chgBit(c+19985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+19993,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); + vcdp->chgBit(c+20001,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBus(c+20009,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r)),28); + vcdp->chgBit(c+20017,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+20025,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+20033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->chgBus(c+20041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[0]),28); + vcdp->chgBus(c+20042,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[1]),28); + vcdp->chgBus(c+20057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),28); + vcdp->chgBus(c+20065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),28); + vcdp->chgBit(c+20073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)); + vcdp->chgBit(c+20081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)); + vcdp->chgBit(c+20089,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)); + vcdp->chgBit(c+20097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+20105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),8); + vcdp->chgArray(c+20113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),224); + vcdp->chgBit(c+20169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+20177,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))))); + vcdp->chgBus(c+20185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),4); + vcdp->chgArray(c+20193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),232); + vcdp->chgArray(c+20201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),232); + vcdp->chgArray(c+20209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),232); + vcdp->chgArray(c+20217,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),232); + vcdp->chgArray(c+20225,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[4]),232); + vcdp->chgArray(c+20233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[5]),232); + vcdp->chgArray(c+20241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[6]),232); + vcdp->chgArray(c+20249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[7]),232); + vcdp->chgArray(c+20705,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),232); + vcdp->chgArray(c+20769,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),232); + vcdp->chgBus(c+20833,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+20841,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+20849,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+20857,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+20865,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),8); + vcdp->chgBit(c+20873,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); + vcdp->chgBus(c+20881,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),8); + vcdp->chgBit(c+20889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+20897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+20905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+20913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+20921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+20945,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+20953,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+20961,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+20969,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+20977,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+20985,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+20993,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+21009,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+21017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+21025,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+21033,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+21041,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+21057,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+21065,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+21073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+21081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+21097,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+21105,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1507[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1507[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1507[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1507[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+21113,(__Vtemp1507),128); + vcdp->chgBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+21153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+21161,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+21169,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+21185,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+21193,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+21201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+21209,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+21217,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+21225,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+21233,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+21241,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+21249,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21257,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+21265,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+21281,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+21289,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+21297,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+21305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+21313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+21315,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+21317,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+21319,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->chgQuad(c+21321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->chgQuad(c+21323,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->chgQuad(c+21325,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->chgQuad(c+21327,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->chgQuad(c+21329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->chgQuad(c+21331,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->chgQuad(c+21333,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->chgQuad(c+21335,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->chgQuad(c+21337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+21339,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+21341,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+21343,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+21569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+21585,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+21601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+21609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+21617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+21625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+21633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+21641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->chgArray(c+21646,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->chgArray(c+21651,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->chgArray(c+21656,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->chgArray(c+21661,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->chgArray(c+21666,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->chgArray(c+21671,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->chgArray(c+21676,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->chgArray(c+21681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->chgArray(c+21686,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->chgArray(c+21691,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->chgArray(c+21696,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->chgArray(c+21701,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->chgArray(c+21706,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->chgArray(c+21711,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->chgArray(c+21716,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->chgArray(c+22281,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->chgArray(c+22321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->chgBus(c+22361,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+22369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+22377,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+22385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+22393,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+22401,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+22409,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+22417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+22449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+22481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+22489,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+22497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->chgArray(c+22505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+22515,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+22525,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+22535,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+22545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->chgArray(c+22555,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->chgArray(c+22565,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->chgArray(c+22575,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->chgArray(c+23145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+23225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+23305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+23313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+23321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+23329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgArray(c+23337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); + __Vtemp1508[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][0U]; + __Vtemp1508[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][1U]; + __Vtemp1508[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][2U]; + __Vtemp1508[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][3U]; + vcdp->chgArray(c+23401,(__Vtemp1508),128); + __Vtemp1509[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][0U]; 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+ vcdp->chgBus(c+24169,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->chgBus(c+24177,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->chgBus(c+24185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+24193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+24201,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->chgArray(c+24249,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+24329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+24332,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+24335,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+24338,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+24341,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+24344,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+24347,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+24350,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+24353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+24356,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+24359,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+24362,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+24365,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+24368,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+24371,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+24374,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+24713,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->chgBus(c+24817,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+24825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+24833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+24841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+24849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+24857,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+24865,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+24873,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->chgArray(c+24881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+24884,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+24887,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+24890,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+24893,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->chgArray(c+24896,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->chgArray(c+24899,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->chgArray(c+24902,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->chgArray(c+25073,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+25097,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+25121,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+25129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+25137,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+25145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+25153,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+25161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+25168,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+25175,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+25182,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+25385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+25441,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+25497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+25505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+25513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+25521,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+25529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+25537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+25545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+25553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+25561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+25569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+25585,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+25593,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+25601,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+25609,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+25617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+25625,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+25633,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+25649,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+25657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+25665,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+25673,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+25681,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+25697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+25705,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+25713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+25721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+25729,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+25737,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+25745,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1531[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1531[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1531[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1531[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+25753,(__Vtemp1531),128); + vcdp->chgBit(c+25785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+25793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+25801,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+25809,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+25825,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+25833,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+25841,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+25849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+25857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+25865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+25873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+25881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+25889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+25897,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+25905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+25913,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+25921,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+25929,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+25937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+25945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+25953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+25955,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+25957,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+25959,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->chgQuad(c+25961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->chgQuad(c+25963,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->chgQuad(c+25965,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->chgQuad(c+25967,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->chgQuad(c+25969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->chgQuad(c+25971,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->chgQuad(c+25973,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->chgQuad(c+25975,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->chgQuad(c+25977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+25979,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+25981,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+25983,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+26209,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+26225,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+26241,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+26249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+26257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+26265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+26273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+26281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->chgArray(c+26286,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->chgArray(c+26291,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->chgArray(c+26296,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->chgArray(c+26301,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->chgArray(c+26306,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->chgArray(c+26311,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->chgArray(c+26316,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->chgArray(c+26321,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->chgArray(c+26326,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->chgArray(c+26331,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->chgArray(c+26336,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->chgArray(c+26341,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->chgArray(c+26346,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->chgArray(c+26351,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->chgArray(c+26356,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->chgArray(c+26921,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->chgArray(c+26961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->chgBus(c+27001,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+27009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+27017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+27025,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+27033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+27041,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+27049,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+27057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+27089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+27121,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+27129,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+27137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->chgArray(c+27145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+27155,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+27165,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+27175,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+27185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->chgArray(c+27195,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->chgArray(c+27205,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->chgArray(c+27215,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->chgArray(c+27785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+27865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+27945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+27953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+27961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); 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+ vcdp->chgBus(c+28564,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); + vcdp->chgBus(c+28565,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); + vcdp->chgBus(c+28566,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); + vcdp->chgBus(c+28567,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); + vcdp->chgBus(c+28568,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); + vcdp->chgBus(c+28681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0U]),16); + vcdp->chgBus(c+28689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [1U]),16); + vcdp->chgBus(c+28697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [2U]),16); + vcdp->chgBus(c+28705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [3U]),16); + vcdp->chgBus(c+28713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [4U]),16); + vcdp->chgBus(c+28721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [5U]),16); + vcdp->chgBus(c+28729,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [6U]),16); + vcdp->chgBus(c+28737,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [7U]),16); + vcdp->chgBus(c+28745,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [8U]),16); + vcdp->chgBus(c+28753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [9U]),16); + vcdp->chgBus(c+28761,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xaU]),16); + vcdp->chgBus(c+28769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xbU]),16); + vcdp->chgBus(c+28777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xcU]),16); + vcdp->chgBus(c+28785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xdU]),16); + vcdp->chgBus(c+28793,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xeU]),16); + vcdp->chgBus(c+28801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->chgBus(c+28809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->chgBus(c+28817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->chgBus(c+28825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+28833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+28841,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->chgArray(c+28889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+28969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+28972,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+28975,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+28978,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+28981,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+28984,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+28987,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+28990,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+28993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+28996,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+28999,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+29002,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+29005,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+29008,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+29011,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+29014,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+29353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->chgBus(c+29457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+29465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+29473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+29481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+29489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+29497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+29505,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+29513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->chgArray(c+29521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+29524,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+29527,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+29530,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+29533,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->chgArray(c+29536,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->chgArray(c+29539,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->chgArray(c+29542,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->chgArray(c+29713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+29737,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+29761,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+29769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+29777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+29785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+29793,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+29801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+29808,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+29815,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+29822,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+30025,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+30081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+30137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+30145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+30153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+30161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+30169,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+30177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+30185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+30193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+30201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+30209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+30225,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+30233,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+30241,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+30249,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+30257,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+30265,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+30273,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+30289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+30297,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+30305,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+30313,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+30321,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+30337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+30345,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+30353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+30361,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+30369,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+30377,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+30385,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1555[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1555[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1555[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1555[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+30393,(__Vtemp1555),128); + vcdp->chgBit(c+30425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+30433,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+30441,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+30449,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+30465,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+30473,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+30481,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+30489,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+30497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+30505,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+30513,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+30521,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+30529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+30537,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+30545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+30553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+30561,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+30569,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+30577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+30585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+30593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+30595,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+30597,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+30599,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->chgQuad(c+30601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->chgQuad(c+30603,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->chgQuad(c+30605,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->chgQuad(c+30607,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->chgQuad(c+30609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->chgQuad(c+30611,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->chgQuad(c+30613,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->chgQuad(c+30615,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->chgQuad(c+30617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+30619,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+30621,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+30623,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+30849,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+30865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+30881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+30889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+30897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+30905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+30913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+30921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->chgArray(c+30926,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->chgArray(c+30931,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->chgArray(c+30936,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->chgArray(c+30941,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->chgArray(c+30946,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->chgArray(c+30951,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->chgArray(c+30956,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->chgArray(c+30961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->chgArray(c+30966,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->chgArray(c+30971,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->chgArray(c+30976,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->chgArray(c+30981,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->chgArray(c+30986,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->chgArray(c+30991,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->chgArray(c+30996,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->chgArray(c+31561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->chgArray(c+31601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->chgBus(c+31641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+31649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+31657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); 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+ vcdp->chgBus(c+33204,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); + vcdp->chgBus(c+33205,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); + vcdp->chgBus(c+33206,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); + vcdp->chgBus(c+33207,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); + vcdp->chgBus(c+33208,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); + vcdp->chgBus(c+33321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0U]),16); + vcdp->chgBus(c+33329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [1U]),16); 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+ vcdp->chgBus(c+33449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->chgBus(c+33457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->chgBus(c+33465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+33473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+33481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->chgArray(c+33529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+33609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+33612,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+33615,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+33618,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+33621,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+33624,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+33627,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+33630,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+33633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+33636,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+33639,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+33642,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+33645,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+33648,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+33651,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+33654,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+33993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->chgBus(c+34097,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+34105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+34113,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+34121,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+34129,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+34137,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+34145,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+34153,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->chgArray(c+34161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); 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+ vcdp->chgArray(c+34377,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+34401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+34409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+34417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+34425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+34433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+34441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+34448,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+34455,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+34462,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+34665,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+34721,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+34777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+34785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+34793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+34801,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+34809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+34817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+34825,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+34833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+34841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+34849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+34865,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+34873,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+34881,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+34889,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+34897,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+34905,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+34913,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+34929,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+34937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+34945,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+34953,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+34961,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+34977,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+34985,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+34993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+35001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+35009,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+35017,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+35025,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1579[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1579[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1579[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1579[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+35033,(__Vtemp1579),128); + vcdp->chgBit(c+35065,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+35073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+35081,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+35089,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+35105,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+35113,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+35121,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+35129,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+35137,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+35145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+35153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+35161,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+35169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+35177,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+35185,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+35193,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+35201,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+35209,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+35217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+35225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+35233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+35235,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+35237,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+35239,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->chgQuad(c+35241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->chgQuad(c+35243,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->chgQuad(c+35245,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->chgQuad(c+35247,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->chgQuad(c+35249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->chgQuad(c+35251,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->chgQuad(c+35253,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->chgQuad(c+35255,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->chgQuad(c+35257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+35259,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+35261,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+35263,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+35489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+35505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+35521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+35529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+35537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+35545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+35553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+35561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->chgArray(c+35566,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->chgArray(c+35571,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->chgArray(c+35576,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->chgArray(c+35581,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); 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+ vcdp->chgArray(c+38804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+38807,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+38810,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+38813,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->chgArray(c+38816,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->chgArray(c+38819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->chgArray(c+38822,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->chgArray(c+38993,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+39017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+39041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+39049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+39057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+39065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+39073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+39081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+39088,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+39095,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+39102,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+39305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+39361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+39417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+39425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+39433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+39441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+39449,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+39457,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+39465,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+39473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+39481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+39489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+39505,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+39513,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+39521,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+39529,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+39537,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+39545,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+39553,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+39569,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+39577,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+39585,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+39593,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+39601,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+39617,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+39625,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+39633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+39641,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+39649,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+39657,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+39665,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1603[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1603[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1603[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1603[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+39673,(__Vtemp1603),128); + vcdp->chgBit(c+39705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+39713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+39721,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+39729,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+39745,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+39753,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+39761,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+39769,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+39777,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+39785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+39793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+39801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+39809,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+39817,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+39825,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+39833,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+39841,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+39849,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+39857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+39865,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+39873,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+39875,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+39877,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+39879,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); 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+ vcdp->chgQuad(c+39897,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+39899,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+39901,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+39903,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+40129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+40145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+40161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+40169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); 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+ vcdp->chgArray(c+40226,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->chgArray(c+40231,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->chgArray(c+40236,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->chgArray(c+40241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->chgArray(c+40246,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->chgArray(c+40251,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->chgArray(c+40256,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->chgArray(c+40261,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->chgArray(c+40266,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->chgArray(c+40271,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->chgArray(c+40276,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->chgArray(c+40841,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->chgArray(c+40881,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->chgBus(c+40921,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+40929,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+40937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+40945,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+40953,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+40961,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+40969,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+40977,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+41009,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+41041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+41049,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+41057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->chgArray(c+41065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+41075,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+41085,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+41095,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+41105,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->chgArray(c+41115,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->chgArray(c+41125,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->chgArray(c+41135,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->chgArray(c+41705,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+41785,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+41865,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+41873,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+41881,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); 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+ __Vtemp1605[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][1U]; + __Vtemp1605[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][2U]; + __Vtemp1605[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][3U]; + vcdp->chgArray(c+41993,(__Vtemp1605),128); + __Vtemp1606[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][0U]; + __Vtemp1606[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][1U]; + __Vtemp1606[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][2U]; + __Vtemp1606[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][3U]; 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+ vcdp->chgArray(c+42895,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+42898,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+42901,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+42904,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+42907,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+42910,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+42913,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+42916,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+42919,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+42922,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+42925,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+42928,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+42931,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+42934,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+43273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->chgBus(c+43377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+43385,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+43393,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+43401,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+43409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+43417,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+43425,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+43433,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->chgArray(c+43441,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+43444,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+43447,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+43450,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+43453,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->chgArray(c+43456,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->chgArray(c+43459,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->chgArray(c+43462,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->chgArray(c+43633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+43657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+43681,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+43689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+43697,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+43705,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+43713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+43721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+43728,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+43735,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+43742,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+43945,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+44001,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+44057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+44065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+44073,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+44081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+44089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+44097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+44105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+44113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+44121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+44129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+44145,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+44153,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+44161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+44169,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+44177,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+44185,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+44193,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+44209,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+44217,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+44225,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+44233,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+44241,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+44257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+44265,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+44273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+44281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+44289,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+44297,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+44305,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1627[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1627[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1627[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1627[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+44313,(__Vtemp1627),128); + vcdp->chgBit(c+44345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+44353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+44361,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+44369,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+44385,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+44393,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+44401,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+44409,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+44417,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+44425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+44433,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+44441,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+44449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+44457,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+44465,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+44473,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+44481,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+44489,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+44497,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+44505,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+44513,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+44515,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+44517,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+44519,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->chgQuad(c+44521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->chgQuad(c+44523,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->chgQuad(c+44525,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->chgQuad(c+44527,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->chgQuad(c+44529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->chgQuad(c+44531,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->chgQuad(c+44533,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->chgQuad(c+44535,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->chgQuad(c+44537,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+44539,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+44541,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+44543,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+44769,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+44785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+44801,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+44809,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+44817,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+44825,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+44833,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+44841,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->chgArray(c+44846,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->chgArray(c+44851,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->chgArray(c+44856,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->chgArray(c+44861,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->chgArray(c+44866,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->chgArray(c+44871,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->chgArray(c+44876,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->chgArray(c+44881,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->chgArray(c+44886,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->chgArray(c+44891,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->chgArray(c+44896,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->chgArray(c+44901,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->chgArray(c+44906,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->chgArray(c+44911,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->chgArray(c+44916,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->chgArray(c+45481,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->chgArray(c+45521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->chgBus(c+45561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+45569,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+45577,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+45585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+45593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+45601,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+45609,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+45617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+45649,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+45681,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+45689,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->chgBus(c+45697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->chgArray(c+45705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+45715,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+45725,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+45735,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+45745,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->chgArray(c+45755,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->chgArray(c+45765,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->chgArray(c+45775,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->chgArray(c+46345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+46425,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+46505,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+46513,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+46521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+46529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgArray(c+46537,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); + __Vtemp1628[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][0U]; + __Vtemp1628[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][1U]; + __Vtemp1628[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][2U]; + __Vtemp1628[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][3U]; + vcdp->chgArray(c+46601,(__Vtemp1628),128); + __Vtemp1629[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][0U]; 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+ vcdp->chgBus(c+47257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [2U]),16); + vcdp->chgBus(c+47265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [3U]),16); + vcdp->chgBus(c+47273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [4U]),16); + vcdp->chgBus(c+47281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [5U]),16); + vcdp->chgBus(c+47289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [6U]),16); + vcdp->chgBus(c+47297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [7U]),16); + vcdp->chgBus(c+47305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [8U]),16); + vcdp->chgBus(c+47313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [9U]),16); + vcdp->chgBus(c+47321,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xaU]),16); + vcdp->chgBus(c+47329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xbU]),16); + vcdp->chgBus(c+47337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xcU]),16); + vcdp->chgBus(c+47345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xdU]),16); + vcdp->chgBus(c+47353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xeU]),16); + vcdp->chgBus(c+47361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->chgBus(c+47369,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->chgBus(c+47377,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->chgBus(c+47385,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+47393,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+47401,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->chgArray(c+47449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+47529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+47532,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+47535,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+47538,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+47541,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+47544,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+47547,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+47550,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+47553,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+47556,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+47559,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+47562,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+47565,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+47568,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+47571,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+47574,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+47913,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->chgBus(c+48017,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+48025,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+48033,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+48041,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+48049,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+48057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+48065,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+48073,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->chgArray(c+48081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+48084,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+48087,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+48090,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+48093,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->chgArray(c+48096,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->chgArray(c+48099,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->chgArray(c+48102,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->chgArray(c+48273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+48297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+48321,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+48329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+48337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+48345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+48353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+48361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+48368,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+48375,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+48382,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+48585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+48641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+48697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+48705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+48713,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+48721,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+48729,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+48737,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+48745,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+48753,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+48761,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+48769,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+48785,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+48793,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+48801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+48809,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+48817,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+48825,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+48833,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+48849,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+48857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+48865,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+48873,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+48881,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+48897,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+48905,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+48913,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+48921,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+48929,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+48937,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+48945,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1651[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1651[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1651[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1651[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+48953,(__Vtemp1651),128); + vcdp->chgBit(c+48985,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+48993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+49001,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+49009,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+49025,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+49033,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+49041,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+49049,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+49057,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+49065,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+49073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+49081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+49089,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+49097,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+49105,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+49113,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+49121,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+49129,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+49137,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+49145,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+49153,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+49155,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+49157,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+49159,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->chgQuad(c+49161,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->chgQuad(c+49163,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->chgQuad(c+49165,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->chgQuad(c+49167,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->chgQuad(c+49169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->chgQuad(c+49171,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->chgQuad(c+49173,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->chgQuad(c+49175,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->chgQuad(c+49177,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+49179,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+49181,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+49183,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+49409,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+49425,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+49441,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+49449,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+49457,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+49465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+49473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+49481,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->chgArray(c+49486,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->chgArray(c+49491,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->chgArray(c+49496,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->chgArray(c+49501,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->chgArray(c+49506,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->chgArray(c+49511,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->chgArray(c+49516,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->chgArray(c+49521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->chgArray(c+49526,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->chgArray(c+49531,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->chgArray(c+49536,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->chgArray(c+49541,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->chgArray(c+49546,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->chgArray(c+49551,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->chgArray(c+49556,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->chgArray(c+50121,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->chgArray(c+50161,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->chgBus(c+50201,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+50209,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+50217,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); 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+ vcdp->chgBus(c+51764,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); + vcdp->chgBus(c+51765,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); + vcdp->chgBus(c+51766,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); + vcdp->chgBus(c+51767,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); + vcdp->chgBus(c+51768,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); + vcdp->chgBus(c+51881,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0U]),16); + vcdp->chgBus(c+51889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [1U]),16); + vcdp->chgBus(c+51897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [2U]),16); + vcdp->chgBus(c+51905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [3U]),16); + vcdp->chgBus(c+51913,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [4U]),16); + vcdp->chgBus(c+51921,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [5U]),16); + vcdp->chgBus(c+51929,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [6U]),16); + vcdp->chgBus(c+51937,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [7U]),16); + vcdp->chgBus(c+51945,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [8U]),16); + vcdp->chgBus(c+51953,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [9U]),16); + vcdp->chgBus(c+51961,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xaU]),16); + vcdp->chgBus(c+51969,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xbU]),16); + vcdp->chgBus(c+51977,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xcU]),16); + vcdp->chgBus(c+51985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xdU]),16); + vcdp->chgBus(c+51993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xeU]),16); + vcdp->chgBus(c+52001,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->chgBus(c+52009,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->chgBus(c+52017,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->chgBus(c+52025,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+52033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+52041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->chgArray(c+52089,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+52169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+52172,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+52175,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+52178,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+52181,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+52184,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+52187,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+52190,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+52193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+52196,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+52199,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+52202,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+52205,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+52208,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+52211,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+52214,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+52553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->chgBus(c+52657,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+52665,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+52673,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+52681,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+52689,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+52697,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+52705,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+52713,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->chgArray(c+52721,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+52724,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+52727,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+52730,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+52733,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->chgArray(c+52736,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->chgArray(c+52739,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->chgArray(c+52742,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->chgArray(c+52913,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+52937,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+52961,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+52969,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+52977,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+52985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+52993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+53001,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+53008,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+53015,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+53022,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+53225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+53281,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+53337,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+53345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+53353,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+53361,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+53369,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+53377,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+53385,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+53393,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+53401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+53409,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+53425,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+53433,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+53441,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->chgBus(c+53449,(((0x18fU >= (0x1ffU & + ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->chgBus(c+53457,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->chgBus(c+53465,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->chgQuad(c+53473,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->chgBus(c+53489,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->chgBit(c+53497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->chgBit(c+53505,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->chgBus(c+53513,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+53521,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->chgBit(c+53537,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->chgBus(c+53545,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->chgBit(c+53553,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->chgBit(c+53561,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->chgBus(c+53569,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->chgBus(c+53577,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->chgBus(c+53585,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1675[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1675[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1675[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1675[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->chgArray(c+53593,(__Vtemp1675),128); + vcdp->chgBit(c+53625,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->chgBit(c+53633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->chgBus(c+53641,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->chgQuad(c+53649,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->chgBus(c+53665,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->chgBit(c+53673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->chgBit(c+53681,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->chgBit(c+53689,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->chgBit(c+53697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->chgBit(c+53705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->chgBit(c+53713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->chgBit(c+53721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->chgBit(c+53729,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+53737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+53745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+53753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+53761,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->chgBus(c+53769,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->chgBit(c+53777,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->chgBus(c+53785,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->chgQuad(c+53793,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->chgQuad(c+53795,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->chgQuad(c+53797,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->chgQuad(c+53799,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->chgQuad(c+53801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->chgQuad(c+53803,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->chgQuad(c+53805,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->chgQuad(c+53807,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->chgQuad(c+53809,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->chgQuad(c+53811,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->chgQuad(c+53813,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->chgQuad(c+53815,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->chgQuad(c+53817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->chgQuad(c+53819,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->chgQuad(c+53821,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->chgQuad(c+53823,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->chgQuad(c+54049,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->chgQuad(c+54065,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->chgBus(c+54081,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+54089,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+54097,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+54105,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+54113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->chgArray(c+54121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->chgArray(c+54126,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->chgArray(c+54131,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->chgArray(c+54136,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->chgArray(c+54141,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->chgArray(c+54146,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->chgArray(c+54151,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->chgArray(c+54156,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->chgArray(c+54161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->chgArray(c+54166,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->chgArray(c+54171,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->chgArray(c+54176,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->chgArray(c+54181,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); 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+ __Vtemp1687[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xbU][3U]; + vcdp->chgArray(c+56233,(__Vtemp1687),128); + __Vtemp1688[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][0U]; + __Vtemp1688[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][1U]; + __Vtemp1688[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][2U]; + __Vtemp1688[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][3U]; + vcdp->chgArray(c+56265,(__Vtemp1688),128); + __Vtemp1689[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][0U]; + __Vtemp1689[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][1U]; + __Vtemp1689[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][2U]; + __Vtemp1689[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][3U]; + vcdp->chgArray(c+56297,(__Vtemp1689),128); + __Vtemp1690[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][0U]; + __Vtemp1690[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][1U]; + __Vtemp1690[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][2U]; + __Vtemp1690[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][3U]; + vcdp->chgArray(c+56329,(__Vtemp1690),128); + __Vtemp1691[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][0U]; + __Vtemp1691[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][1U]; + __Vtemp1691[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][2U]; + __Vtemp1691[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][3U]; + vcdp->chgArray(c+56361,(__Vtemp1691),128); + vcdp->chgBus(c+56393,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); + vcdp->chgBus(c+56394,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); + vcdp->chgBus(c+56395,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); + vcdp->chgBus(c+56396,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); + vcdp->chgBus(c+56397,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); + vcdp->chgBus(c+56398,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); + vcdp->chgBus(c+56399,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); + vcdp->chgBus(c+56400,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); + vcdp->chgBus(c+56401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); + vcdp->chgBus(c+56402,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); + vcdp->chgBus(c+56403,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); + vcdp->chgBus(c+56404,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); + vcdp->chgBus(c+56405,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); + vcdp->chgBus(c+56406,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); + vcdp->chgBus(c+56407,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); + vcdp->chgBus(c+56408,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); + vcdp->chgBus(c+56521,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0U]),16); + vcdp->chgBus(c+56529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [1U]),16); + vcdp->chgBus(c+56537,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [2U]),16); + vcdp->chgBus(c+56545,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [3U]),16); + vcdp->chgBus(c+56553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [4U]),16); + vcdp->chgBus(c+56561,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [5U]),16); + vcdp->chgBus(c+56569,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [6U]),16); + vcdp->chgBus(c+56577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [7U]),16); + vcdp->chgBus(c+56585,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [8U]),16); + vcdp->chgBus(c+56593,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [9U]),16); + vcdp->chgBus(c+56601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xaU]),16); + vcdp->chgBus(c+56609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xbU]),16); + vcdp->chgBus(c+56617,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xcU]),16); + vcdp->chgBus(c+56625,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xdU]),16); + vcdp->chgBus(c+56633,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xeU]),16); + vcdp->chgBus(c+56641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->chgBus(c+56649,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->chgBus(c+56657,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->chgBus(c+56665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+56673,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+56681,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->chgArray(c+56729,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+56809,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+56812,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+56815,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+56818,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+56821,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+56824,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+56827,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+56830,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+56833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+56836,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+56839,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+56842,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+56845,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+56848,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+56851,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+56854,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+57193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->chgBus(c+57297,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+57305,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+57313,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+57321,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+57329,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+57337,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+57345,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+57353,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->chgArray(c+57361,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+57364,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+57367,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+57370,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+57373,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->chgArray(c+57376,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->chgArray(c+57379,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->chgArray(c+57382,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->chgArray(c+57553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+57577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+57601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->chgBus(c+57609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->chgBus(c+57617,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->chgBit(c+57625,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+57633,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+57641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->chgArray(c+57648,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->chgArray(c+57655,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->chgArray(c+57662,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->chgArray(c+57865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->chgArray(c+57921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->chgBus(c+57977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+57985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+57993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+58001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + } +} + +void VVX_cache::traceChgThis__6(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->chgBit(c+58009,(vlTOPp->clk)); + vcdp->chgBit(c+58017,(vlTOPp->reset)); + vcdp->chgBus(c+58025,(vlTOPp->core_req_valid),4); + vcdp->chgBus(c+58033,(vlTOPp->core_req_rw),4); + vcdp->chgBus(c+58041,(vlTOPp->core_req_byteen),16); + vcdp->chgArray(c+58049,(vlTOPp->core_req_addr),120); + vcdp->chgArray(c+58081,(vlTOPp->core_req_data),128); + vcdp->chgQuad(c+58113,(vlTOPp->core_req_tag),42); + vcdp->chgBit(c+58129,(vlTOPp->core_req_ready)); + vcdp->chgBus(c+58137,(vlTOPp->core_rsp_valid),4); + vcdp->chgArray(c+58145,(vlTOPp->core_rsp_data),128); + vcdp->chgQuad(c+58177,(vlTOPp->core_rsp_tag),42); + vcdp->chgBit(c+58193,(vlTOPp->core_rsp_ready)); + vcdp->chgBit(c+58201,(vlTOPp->dram_req_valid)); + vcdp->chgBit(c+58209,(vlTOPp->dram_req_rw)); + vcdp->chgBus(c+58217,(vlTOPp->dram_req_byteen),16); + vcdp->chgBus(c+58225,(vlTOPp->dram_req_addr),28); + vcdp->chgArray(c+58233,(vlTOPp->dram_req_data),128); + vcdp->chgBus(c+58265,(vlTOPp->dram_req_tag),28); + vcdp->chgBit(c+58273,(vlTOPp->dram_req_ready)); + vcdp->chgBit(c+58281,(vlTOPp->dram_rsp_valid)); + vcdp->chgArray(c+58289,(vlTOPp->dram_rsp_data),128); + vcdp->chgBus(c+58321,(vlTOPp->dram_rsp_tag),28); + vcdp->chgBit(c+58329,(vlTOPp->dram_rsp_ready)); + vcdp->chgBit(c+58337,(vlTOPp->snp_req_valid)); + vcdp->chgBus(c+58345,(vlTOPp->snp_req_addr),28); + vcdp->chgBit(c+58353,(vlTOPp->snp_req_invalidate)); + vcdp->chgBus(c+58361,(vlTOPp->snp_req_tag),28); + vcdp->chgBit(c+58369,(vlTOPp->snp_req_ready)); + vcdp->chgBit(c+58377,(vlTOPp->snp_rsp_valid)); + vcdp->chgBus(c+58385,(vlTOPp->snp_rsp_tag),28); + vcdp->chgBit(c+58393,(vlTOPp->snp_rsp_ready)); + vcdp->chgBus(c+58401,(vlTOPp->snp_fwdout_valid),2); + vcdp->chgQuad(c+58409,(vlTOPp->snp_fwdout_addr),56); + vcdp->chgBus(c+58425,(vlTOPp->snp_fwdout_invalidate),2); + vcdp->chgBus(c+58433,(vlTOPp->snp_fwdout_tag),2); + vcdp->chgBus(c+58441,(vlTOPp->snp_fwdout_ready),2); + vcdp->chgBus(c+58449,(vlTOPp->snp_fwdin_valid),2); + vcdp->chgBus(c+58457,(vlTOPp->snp_fwdin_tag),2); + vcdp->chgBus(c+58465,(vlTOPp->snp_fwdin_ready),2); + vcdp->chgBit(c+58473,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58481,(((IData)(vlTOPp->dram_rsp_valid) + & (0U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBus(c+58489,((0x1ffffffU & (vlTOPp->dram_rsp_tag + >> 3U))),25); + vcdp->chgBit(c+58497,(((IData)(vlTOPp->snp_req_valid) + & (0U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBus(c+58505,((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U))),25); + vcdp->chgBit(c+58513,(((IData)(vlTOPp->dram_rsp_valid) + & (1U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+58521,(((IData)(vlTOPp->snp_req_valid) + & (1U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58529,(((IData)(vlTOPp->dram_rsp_valid) + & (2U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+58537,(((IData)(vlTOPp->snp_req_valid) + & (2U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58545,(((IData)(vlTOPp->dram_rsp_valid) + & (3U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+58553,(((IData)(vlTOPp->snp_req_valid) + & (3U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58561,(((IData)(vlTOPp->dram_rsp_valid) + & (4U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+58569,(((IData)(vlTOPp->snp_req_valid) + & (4U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58577,(((IData)(vlTOPp->dram_rsp_valid) + & (5U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+58585,(((IData)(vlTOPp->snp_req_valid) + & (5U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58593,(((IData)(vlTOPp->dram_rsp_valid) + & (6U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+58601,(((IData)(vlTOPp->snp_req_valid) + & (6U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58609,(((IData)(vlTOPp->dram_rsp_valid) + & (7U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+58617,(((IData)(vlTOPp->snp_req_valid) + & (7U == (7U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+58625,(((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))))); + vcdp->chgBit(c+58633,((((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + } +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp new file mode 100644 index 00000000..7382e434 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp @@ -0,0 +1,15246 @@ +// Verilated -*- C++ -*- +// DESCRIPTION: Verilator output: Tracing implementation internals +#include "verilated_vcd_c.h" +#include "VVX_cache__Syms.h" + + +//====================== + +void VVX_cache::trace(VerilatedVcdC* tfp, int, int) { + tfp->spTrace()->addCallback(&VVX_cache::traceInit, &VVX_cache::traceFull, &VVX_cache::traceChg, this); +} +void VVX_cache::traceInit(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->open() + VVX_cache* t = (VVX_cache*)userthis; + VVX_cache__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + if (!Verilated::calcUnusedSigs()) { + VL_FATAL_MT(__FILE__, __LINE__, __FILE__, + "Turning on wave traces requires Verilated::traceEverOn(true) call before time 0."); + } + vcdp->scopeEscape(' '); + t->traceInitThis(vlSymsp, vcdp, code); + vcdp->scopeEscape('.'); +} +void VVX_cache::traceFull(VerilatedVcd* vcdp, void* userthis, uint32_t code) { + // Callback from vcd->dump() + VVX_cache* t = (VVX_cache*)userthis; + VVX_cache__Syms* __restrict vlSymsp = t->__VlSymsp; // Setup global symbol table + t->traceFullThis(vlSymsp, vcdp, code); +} + +//====================== + + +void VVX_cache::traceInitThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + vcdp->module(vlSymsp->name()); // Setup signal names + // Body + { + vlTOPp->traceInitThis__1(vlSymsp, vcdp, code); + } +} + +void VVX_cache::traceFullThis(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vlTOPp->traceFullThis__1(vlSymsp, vcdp, code); + } + // Final + vlTOPp->__Vm_traceActivity = 0U; +} + +void VVX_cache::traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Body + { + vcdp->declBit(c+58009,"clk", false,-1); + vcdp->declBit(c+58017,"reset", false,-1); + vcdp->declBus(c+58025,"core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"core_req_tag", false,-1, 41,0); + vcdp->declBit(c+58129,"core_req_ready", false,-1); + vcdp->declBus(c+58137,"core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+58145,"core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+58177,"core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+58193,"core_rsp_ready", false,-1); + vcdp->declBit(c+58201,"dram_req_valid", false,-1); + vcdp->declBit(c+58209,"dram_req_rw", false,-1); + vcdp->declBus(c+58217,"dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+58225,"dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+58233,"dram_req_data", false,-1, 127,0); + vcdp->declBus(c+58265,"dram_req_tag", false,-1, 27,0); + vcdp->declBit(c+58273,"dram_req_ready", false,-1); + vcdp->declBit(c+58281,"dram_rsp_valid", false,-1); + vcdp->declArray(c+58289,"dram_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58321,"dram_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+58329,"dram_rsp_ready", false,-1); + vcdp->declBit(c+58337,"snp_req_valid", false,-1); + vcdp->declBus(c+58345,"snp_req_addr", false,-1, 27,0); + vcdp->declBit(c+58353,"snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+58369,"snp_req_ready", false,-1); + vcdp->declBit(c+58377,"snp_rsp_valid", false,-1); + vcdp->declBus(c+58385,"snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+58393,"snp_rsp_ready", false,-1); + vcdp->declBus(c+58401,"snp_fwdout_valid", false,-1, 1,0); + vcdp->declQuad(c+58409,"snp_fwdout_addr", false,-1, 55,0); + vcdp->declBus(c+58425,"snp_fwdout_invalidate", false,-1, 1,0); + vcdp->declBus(c+58433,"snp_fwdout_tag", false,-1, 1,0); + vcdp->declBus(c+58441,"snp_fwdout_ready", false,-1, 1,0); + vcdp->declBus(c+58449,"snp_fwdin_valid", false,-1, 1,0); + vcdp->declBus(c+58457,"snp_fwdin_tag", false,-1, 1,0); + vcdp->declBus(c+58465,"snp_fwdin_ready", false,-1, 1,0); + vcdp->declBus(c+58641,"VX_cache CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache DRAM_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58705,"VX_cache NUM_SNP_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache SNP_FWD_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache clk", false,-1); + vcdp->declBit(c+58017,"VX_cache reset", false,-1); + vcdp->declBus(c+58025,"VX_cache core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache core_req_tag", false,-1, 41,0); + vcdp->declBit(c+58129,"VX_cache core_req_ready", false,-1); + vcdp->declBus(c+58137,"VX_cache core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+58145,"VX_cache core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+58177,"VX_cache core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+58193,"VX_cache core_rsp_ready", false,-1); + vcdp->declBit(c+58201,"VX_cache dram_req_valid", false,-1); + vcdp->declBit(c+58209,"VX_cache dram_req_rw", false,-1); + vcdp->declBus(c+58217,"VX_cache dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+58225,"VX_cache dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+58233,"VX_cache dram_req_data", false,-1, 127,0); + vcdp->declBus(c+58265,"VX_cache dram_req_tag", false,-1, 27,0); + vcdp->declBit(c+58273,"VX_cache dram_req_ready", false,-1); + vcdp->declBit(c+58281,"VX_cache dram_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache dram_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58321,"VX_cache dram_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+58329,"VX_cache dram_rsp_ready", false,-1); + vcdp->declBit(c+58337,"VX_cache snp_req_valid", false,-1); + vcdp->declBus(c+58345,"VX_cache snp_req_addr", false,-1, 27,0); + vcdp->declBit(c+58353,"VX_cache snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+58369,"VX_cache snp_req_ready", false,-1); + vcdp->declBit(c+58377,"VX_cache snp_rsp_valid", false,-1); + vcdp->declBus(c+58385,"VX_cache snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+58393,"VX_cache snp_rsp_ready", false,-1); + vcdp->declBus(c+58401,"VX_cache snp_fwdout_valid", false,-1, 1,0); + vcdp->declQuad(c+58409,"VX_cache snp_fwdout_addr", false,-1, 55,0); + vcdp->declBus(c+58425,"VX_cache snp_fwdout_invalidate", false,-1, 1,0); + vcdp->declBus(c+58433,"VX_cache snp_fwdout_tag", false,-1, 1,0); + vcdp->declBus(c+58441,"VX_cache snp_fwdout_ready", false,-1, 1,0); + vcdp->declBus(c+58449,"VX_cache snp_fwdin_valid", false,-1, 1,0); + vcdp->declBus(c+58457,"VX_cache snp_fwdin_tag", false,-1, 1,0); + vcdp->declBus(c+58465,"VX_cache snp_fwdin_ready", false,-1, 1,0); + vcdp->declBus(c+1,"VX_cache per_bank_valid", false,-1, 31,0); + vcdp->declBus(c+2113,"VX_cache per_bank_core_req_ready", false,-1, 7,0); + vcdp->declBus(c+2121,"VX_cache per_bank_core_rsp_valid", false,-1, 7,0); + vcdp->declBus(c+2129,"VX_cache per_bank_core_rsp_tid", false,-1, 15,0); + vcdp->declArray(c+2137,"VX_cache per_bank_core_rsp_data", false,-1, 255,0); + vcdp->declArray(c+2201,"VX_cache per_bank_core_rsp_tag", false,-1, 335,0); + vcdp->declBus(c+9,"VX_cache per_bank_core_rsp_ready", false,-1, 7,0); + vcdp->declBus(c+2289,"VX_cache per_bank_dram_fill_req_valid", false,-1, 7,0); + vcdp->declArray(c+2297,"VX_cache per_bank_dram_fill_req_addr", false,-1, 223,0); + vcdp->declBit(c+19649,"VX_cache dram_fill_req_ready", false,-1); + vcdp->declBus(c+2353,"VX_cache per_bank_dram_fill_rsp_ready", false,-1, 7,0); + vcdp->declBus(c+17,"VX_cache per_bank_dram_wb_req_ready", false,-1, 7,0); + vcdp->declBus(c+2361,"VX_cache per_bank_dram_wb_req_valid", false,-1, 7,0); + vcdp->declArray(c+2369,"VX_cache per_bank_dram_wb_req_byteen", false,-1, 127,0); + vcdp->declArray(c+2401,"VX_cache per_bank_dram_wb_req_addr", false,-1, 223,0); + vcdp->declArray(c+2457,"VX_cache per_bank_dram_wb_req_data", false,-1, 1023,0); + vcdp->declBus(c+2713,"VX_cache per_bank_snp_req_ready", false,-1, 7,0); + vcdp->declBus(c+2721,"VX_cache per_bank_snp_rsp_valid", false,-1, 7,0); + vcdp->declArray(c+2729,"VX_cache per_bank_snp_rsp_tag", false,-1, 223,0); + vcdp->declBus(c+25,"VX_cache per_bank_snp_rsp_ready", false,-1, 7,0); + vcdp->declBit(c+58337,"VX_cache snp_req_valid_qual", false,-1); + vcdp->declBus(c+58345,"VX_cache snp_req_addr_qual", false,-1, 27,0); + vcdp->declBit(c+58353,"VX_cache snp_req_invalidate_qual", false,-1); + vcdp->declBus(c+58361,"VX_cache snp_req_tag_qual", false,-1, 27,0); + vcdp->declBit(c+58473,"VX_cache snp_req_ready_qual", false,-1); + vcdp->declBus(c+33,"VX_cache genblk5[0] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[0] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[0] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[0] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[0] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[0] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19657,"VX_cache genblk5[0] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+2785,"VX_cache genblk5[0] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+2793,"VX_cache genblk5[0] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+2801,"VX_cache genblk5[0] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+41,"VX_cache genblk5[0] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58481,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19665,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+2817,"VX_cache genblk5[0] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19673,"VX_cache genblk5[0] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[0] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+2825,"VX_cache genblk5[0] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+2833,"VX_cache genblk5[0] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+2841,"VX_cache genblk5[0] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+2849,"VX_cache genblk5[0] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+49,"VX_cache genblk5[0] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58497,"VX_cache genblk5[0] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[0] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[0] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[0] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19681,"VX_cache genblk5[0] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+2881,"VX_cache genblk5[0] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+2889,"VX_cache genblk5[0] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+57,"VX_cache genblk5[0] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19689,"VX_cache genblk5[0] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+65,"VX_cache genblk5[1] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[1] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[1] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[1] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[1] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[1] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19697,"VX_cache genblk5[1] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+2897,"VX_cache genblk5[1] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+2905,"VX_cache genblk5[1] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+2913,"VX_cache genblk5[1] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+73,"VX_cache genblk5[1] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58513,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19705,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+2929,"VX_cache genblk5[1] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19713,"VX_cache genblk5[1] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[1] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+2937,"VX_cache genblk5[1] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+2945,"VX_cache genblk5[1] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+2953,"VX_cache genblk5[1] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+2961,"VX_cache genblk5[1] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+81,"VX_cache genblk5[1] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58521,"VX_cache genblk5[1] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[1] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[1] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[1] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19721,"VX_cache genblk5[1] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+2993,"VX_cache genblk5[1] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+3001,"VX_cache genblk5[1] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+89,"VX_cache genblk5[1] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19729,"VX_cache genblk5[1] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+97,"VX_cache genblk5[2] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[2] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[2] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[2] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[2] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[2] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19737,"VX_cache genblk5[2] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+3009,"VX_cache genblk5[2] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3017,"VX_cache genblk5[2] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3025,"VX_cache genblk5[2] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+105,"VX_cache genblk5[2] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58529,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19745,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3041,"VX_cache genblk5[2] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19753,"VX_cache genblk5[2] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[2] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+3049,"VX_cache genblk5[2] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+3057,"VX_cache genblk5[2] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3065,"VX_cache genblk5[2] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3073,"VX_cache genblk5[2] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+113,"VX_cache genblk5[2] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58537,"VX_cache genblk5[2] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[2] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[2] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[2] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19761,"VX_cache genblk5[2] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+3105,"VX_cache genblk5[2] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+3113,"VX_cache genblk5[2] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+121,"VX_cache genblk5[2] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19769,"VX_cache genblk5[2] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+129,"VX_cache genblk5[3] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[3] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[3] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[3] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[3] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[3] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19777,"VX_cache genblk5[3] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+3121,"VX_cache genblk5[3] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3129,"VX_cache genblk5[3] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3137,"VX_cache genblk5[3] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+137,"VX_cache genblk5[3] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58545,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19785,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3153,"VX_cache genblk5[3] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19793,"VX_cache genblk5[3] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[3] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+3161,"VX_cache genblk5[3] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+3169,"VX_cache genblk5[3] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3177,"VX_cache genblk5[3] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3185,"VX_cache genblk5[3] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+145,"VX_cache genblk5[3] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58553,"VX_cache genblk5[3] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[3] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[3] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[3] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19801,"VX_cache genblk5[3] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+3217,"VX_cache genblk5[3] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+3225,"VX_cache genblk5[3] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+153,"VX_cache genblk5[3] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19809,"VX_cache genblk5[3] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+161,"VX_cache genblk5[4] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[4] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[4] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[4] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[4] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[4] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19817,"VX_cache genblk5[4] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+3233,"VX_cache genblk5[4] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3241,"VX_cache genblk5[4] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3249,"VX_cache genblk5[4] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+169,"VX_cache genblk5[4] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58561,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19825,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3265,"VX_cache genblk5[4] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19833,"VX_cache genblk5[4] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[4] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+3273,"VX_cache genblk5[4] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+3281,"VX_cache genblk5[4] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3289,"VX_cache genblk5[4] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3297,"VX_cache genblk5[4] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+177,"VX_cache genblk5[4] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58569,"VX_cache genblk5[4] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[4] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[4] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[4] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19841,"VX_cache genblk5[4] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+3329,"VX_cache genblk5[4] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+3337,"VX_cache genblk5[4] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+185,"VX_cache genblk5[4] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19849,"VX_cache genblk5[4] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+193,"VX_cache genblk5[5] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[5] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[5] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[5] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[5] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[5] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19857,"VX_cache genblk5[5] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+3345,"VX_cache genblk5[5] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3353,"VX_cache genblk5[5] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3361,"VX_cache genblk5[5] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+201,"VX_cache genblk5[5] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58577,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19865,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3377,"VX_cache genblk5[5] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19873,"VX_cache genblk5[5] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[5] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+3385,"VX_cache genblk5[5] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+3393,"VX_cache genblk5[5] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3401,"VX_cache genblk5[5] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3409,"VX_cache genblk5[5] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+209,"VX_cache genblk5[5] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58585,"VX_cache genblk5[5] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[5] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[5] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[5] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19881,"VX_cache genblk5[5] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+3441,"VX_cache genblk5[5] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+3449,"VX_cache genblk5[5] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+217,"VX_cache genblk5[5] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19889,"VX_cache genblk5[5] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+225,"VX_cache genblk5[6] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[6] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[6] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[6] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[6] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[6] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19897,"VX_cache genblk5[6] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+3457,"VX_cache genblk5[6] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3465,"VX_cache genblk5[6] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3473,"VX_cache genblk5[6] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+233,"VX_cache genblk5[6] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58593,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19905,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3489,"VX_cache genblk5[6] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19913,"VX_cache genblk5[6] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[6] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+3497,"VX_cache genblk5[6] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+3505,"VX_cache genblk5[6] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3513,"VX_cache genblk5[6] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3521,"VX_cache genblk5[6] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+241,"VX_cache genblk5[6] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58601,"VX_cache genblk5[6] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[6] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[6] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[6] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19921,"VX_cache genblk5[6] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+3553,"VX_cache genblk5[6] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+3561,"VX_cache genblk5[6] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+249,"VX_cache genblk5[6] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19929,"VX_cache genblk5[6] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+257,"VX_cache genblk5[7] curr_bank_core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[7] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[7] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[7] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[7] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+58081,"VX_cache genblk5[7] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+19937,"VX_cache genblk5[7] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+3569,"VX_cache genblk5[7] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3577,"VX_cache genblk5[7] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3585,"VX_cache genblk5[7] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+265,"VX_cache genblk5[7] curr_bank_core_rsp_ready", false,-1); + vcdp->declBit(c+58609,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19945,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3601,"VX_cache genblk5[7] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+19953,"VX_cache genblk5[7] curr_bank_dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[7] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+3609,"VX_cache genblk5[7] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+3617,"VX_cache genblk5[7] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3625,"VX_cache genblk5[7] curr_bank_dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3633,"VX_cache genblk5[7] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+273,"VX_cache genblk5[7] curr_bank_dram_wb_req_ready", false,-1); + vcdp->declBit(c+58617,"VX_cache genblk5[7] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[7] curr_bank_snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[7] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[7] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19961,"VX_cache genblk5[7] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+3665,"VX_cache genblk5[7] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+3673,"VX_cache genblk5[7] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+281,"VX_cache genblk5[7] curr_bank_snp_rsp_ready", false,-1); + vcdp->declBit(c+19969,"VX_cache genblk5[7] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+58657,"VX_cache cache_core_req_bank_sel BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache cache_core_req_bank_sel WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_core_req_bank_sel NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache cache_core_req_bank_sel NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58025,"VX_cache cache_core_req_bank_sel core_req_valid", false,-1, 3,0); + vcdp->declArray(c+58049,"VX_cache cache_core_req_bank_sel core_req_addr", false,-1, 119,0); + vcdp->declBus(c+2113,"VX_cache cache_core_req_bank_sel per_bank_ready", false,-1, 7,0); + vcdp->declBus(c+1,"VX_cache cache_core_req_bank_sel per_bank_valid", false,-1, 31,0); + vcdp->declBit(c+58129,"VX_cache cache_core_req_bank_sel core_req_ready", false,-1); + vcdp->declBus(c+58713,"VX_cache cache_core_req_bank_sel i", false,-1, 31,0); + vcdp->declBus(c+289,"VX_cache cache_core_req_bank_sel genblk2 per_bank_ready_sel", false,-1, 7,0); + vcdp->declBus(c+58657,"VX_cache cache_dram_req_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache cache_dram_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb reset", false,-1); + vcdp->declBus(c+2289,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_valid", false,-1, 7,0); + vcdp->declArray(c+2297,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_addr", false,-1, 223,0); + vcdp->declBit(c+19649,"VX_cache cache_dram_req_arb dram_fill_req_ready", false,-1); + vcdp->declBus(c+2361,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_valid", false,-1, 7,0); + vcdp->declArray(c+2369,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_byteen", false,-1, 127,0); + vcdp->declArray(c+2401,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_addr", false,-1, 223,0); + vcdp->declArray(c+2457,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_data", false,-1, 1023,0); + vcdp->declBus(c+17,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_ready", false,-1, 7,0); + vcdp->declBit(c+58201,"VX_cache cache_dram_req_arb dram_req_valid", false,-1); + vcdp->declBit(c+58209,"VX_cache cache_dram_req_arb dram_req_rw", false,-1); + vcdp->declBus(c+58217,"VX_cache cache_dram_req_arb dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+58225,"VX_cache cache_dram_req_arb dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+58233,"VX_cache cache_dram_req_arb dram_req_data", false,-1, 127,0); + vcdp->declBit(c+58273,"VX_cache cache_dram_req_arb dram_req_ready", false,-1); + vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb pref_pop", false,-1); + vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb pref_valid", false,-1); + vcdp->declBus(c+19977,"VX_cache cache_dram_req_arb pref_addr", false,-1, 27,0); + vcdp->declBit(c+3681,"VX_cache cache_dram_req_arb dwb_valid", false,-1); + vcdp->declBit(c+3689,"VX_cache cache_dram_req_arb dfqq_req", false,-1); + vcdp->declBus(c+3697,"VX_cache cache_dram_req_arb dfqq_req_addr", false,-1, 27,0); + vcdp->declBit(c+3705,"VX_cache cache_dram_req_arb dfqq_empty", false,-1); + vcdp->declBit(c+297,"VX_cache cache_dram_req_arb dfqq_pop", false,-1); + vcdp->declBit(c+3713,"VX_cache cache_dram_req_arb dfqq_push", false,-1); + vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dfqq_full", false,-1); + vcdp->declBus(c+3721,"VX_cache cache_dram_req_arb dwb_bank", false,-1, 2,0); + vcdp->declBus(c+58657,"VX_cache cache_dram_req_arb prfqq BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache cache_dram_req_arb prfqq WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb prfqq PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb prfqq PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb prfqq clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb prfqq reset", false,-1); + vcdp->declBit(c+58625,"VX_cache cache_dram_req_arb prfqq dram_req", false,-1); + vcdp->declBus(c+58225,"VX_cache cache_dram_req_arb prfqq dram_req_addr", false,-1, 27,0); + vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb prfqq pref_pop", false,-1); + vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb prfqq pref_valid", false,-1); + vcdp->declBus(c+19977,"VX_cache cache_dram_req_arb prfqq pref_addr", false,-1, 27,0); + vcdp->declBus(c+19993,"VX_cache cache_dram_req_arb prfqq use_valid", false,-1, 1,0); + vcdp->declBus(c+19977,"VX_cache cache_dram_req_arb prfqq use_addr", false,-1, 27,0); + vcdp->declBit(c+20001,"VX_cache cache_dram_req_arb prfqq current_valid", false,-1); + vcdp->declBus(c+20009,"VX_cache cache_dram_req_arb prfqq current_addr", false,-1, 27,0); + vcdp->declBit(c+20017,"VX_cache cache_dram_req_arb prfqq current_full", false,-1); + vcdp->declBit(c+20025,"VX_cache cache_dram_req_arb prfqq current_empty", false,-1); + vcdp->declBit(c+3729,"VX_cache cache_dram_req_arb prfqq update_use", false,-1); + vcdp->declBus(c+58697,"VX_cache cache_dram_req_arb prfqq pfq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb prfqq pfq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache cache_dram_req_arb prfqq pfq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb prfqq pfq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb prfqq pfq_queue reset", false,-1); + vcdp->declBit(c+58633,"VX_cache cache_dram_req_arb prfqq pfq_queue push", false,-1); + vcdp->declBit(c+3729,"VX_cache cache_dram_req_arb prfqq pfq_queue pop", false,-1); + vcdp->declBus(c+58225,"VX_cache cache_dram_req_arb prfqq pfq_queue data_in", false,-1, 27,0); + vcdp->declBus(c+20009,"VX_cache cache_dram_req_arb prfqq pfq_queue data_out", false,-1, 27,0); + vcdp->declBit(c+20025,"VX_cache cache_dram_req_arb prfqq pfq_queue empty", false,-1); + vcdp->declBit(c+20017,"VX_cache cache_dram_req_arb prfqq pfq_queue full", false,-1); + vcdp->declBus(c+20033,"VX_cache cache_dram_req_arb prfqq pfq_queue size", false,-1, 0,0); + vcdp->declBus(c+20033,"VX_cache cache_dram_req_arb prfqq pfq_queue size_r", false,-1, 0,0); + vcdp->declBit(c+3737,"VX_cache cache_dram_req_arb prfqq pfq_queue reading", false,-1); + vcdp->declBit(c+3745,"VX_cache cache_dram_req_arb prfqq pfq_queue writing", false,-1); + {int i; for (i=0; i<2; i++) { + vcdp->declBus(c+20041+i*1,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 data", true,(i+-1), 27,0);}} + vcdp->declBus(c+20057,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 head_r", false,-1, 27,0); + vcdp->declBus(c+20065,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 curr_r", false,-1, 27,0); + vcdp->declBus(c+20073,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 wr_ptr_r", false,-1, 0,0); + vcdp->declBus(c+20081,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 rd_ptr_r", false,-1, 0,0); + vcdp->declBus(c+20089,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 0,0); + vcdp->declBit(c+20025,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+20017,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+20097,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58657,"VX_cache cache_dram_req_arb dram_fill_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb DFQQ_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb dram_fill_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb dram_fill_arb reset", false,-1); + vcdp->declBit(c+3713,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_push", false,-1); + vcdp->declBus(c+2289,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_valid", false,-1, 7,0); + vcdp->declArray(c+2297,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_addr", false,-1, 223,0); + vcdp->declBit(c+297,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_pop", false,-1); + vcdp->declBit(c+3689,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req", false,-1); + vcdp->declBus(c+3697,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req_addr", false,-1, 27,0); + vcdp->declBit(c+3705,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_empty", false,-1); + vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_full", false,-1); + vcdp->declBus(c+20105,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_valid", false,-1, 7,0); + vcdp->declArray(c+20113,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_addr", false,-1, 223,0); + vcdp->declBus(c+3753,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_valid", false,-1, 7,0); + vcdp->declArray(c+3761,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_addr", false,-1, 223,0); + vcdp->declBus(c+3817,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bqual_bank_dram_fill_req_valid", false,-1, 7,0); + vcdp->declArray(c+3825,"VX_cache cache_dram_req_arb dram_fill_arb qual_bank_dram_fill_req_addr", false,-1, 223,0); + vcdp->declBus(c+3881,"VX_cache cache_dram_req_arb dram_fill_arb updated_bank_dram_fill_req_valid", false,-1, 7,0); + vcdp->declBit(c+20169,"VX_cache cache_dram_req_arb dram_fill_arb o_empty", false,-1); + vcdp->declBit(c+20177,"VX_cache cache_dram_req_arb dram_fill_arb use_empty", false,-1); + vcdp->declBit(c+3889,"VX_cache cache_dram_req_arb dram_fill_arb out_empty", false,-1); + vcdp->declBit(c+3897,"VX_cache cache_dram_req_arb dram_fill_arb push_qual", false,-1); + vcdp->declBit(c+1849,"VX_cache cache_dram_req_arb dram_fill_arb pop_qual", false,-1); + vcdp->declBus(c+3905,"VX_cache cache_dram_req_arb dram_fill_arb qual_request_index", false,-1, 2,0); + vcdp->declBit(c+3913,"VX_cache cache_dram_req_arb dram_fill_arb qual_has_request", false,-1); + vcdp->declBus(c+58729,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reset", false,-1); + vcdp->declBit(c+3897,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue push", false,-1); + vcdp->declBit(c+1849,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue pop", false,-1); + vcdp->declArray(c+3921,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_in", false,-1, 231,0); + vcdp->declArray(c+3985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_out", false,-1, 231,0); + vcdp->declBit(c+20169,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue empty", false,-1); + vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue full", false,-1); + vcdp->declBus(c+20185,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size", false,-1, 3,0); + vcdp->declBus(c+20185,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+305,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reading", false,-1); + vcdp->declBit(c+4049,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+20193+i*8,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 data", true,(i+0), 231,0);}} + vcdp->declArray(c+20705,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 head_r", false,-1, 231,0); + vcdp->declArray(c+20769,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 curr_r", false,-1, 231,0); + vcdp->declBus(c+20833,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+20841,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+20849,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+20169,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+20857,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank reset", false,-1); + vcdp->declBus(c+3817,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank requests", false,-1, 7,0); + vcdp->declBus(c+3905,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_index", false,-1, 2,0); + vcdp->declBus(c+4057,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_onehot", false,-1, 7,0); + vcdp->declBit(c+3913,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+4057,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 grant_onehot_r", false,-1, 7,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+3817,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_in", false,-1, 7,0); + vcdp->declBus(c+3905,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_out", false,-1, 2,0); + vcdp->declBit(c+3913,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+4065,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb sel_dwb N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb sel_dwb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb sel_dwb reset", false,-1); + vcdp->declBus(c+2361,"VX_cache cache_dram_req_arb sel_dwb requests", false,-1, 7,0); + vcdp->declBus(c+3721,"VX_cache cache_dram_req_arb sel_dwb grant_index", false,-1, 2,0); + vcdp->declBus(c+4073,"VX_cache cache_dram_req_arb sel_dwb grant_onehot", false,-1, 7,0); + vcdp->declBit(c+3681,"VX_cache cache_dram_req_arb sel_dwb grant_valid", false,-1); + vcdp->declBus(c+4073,"VX_cache cache_dram_req_arb sel_dwb genblk2 grant_onehot_r", false,-1, 7,0); + vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+2361,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_in", false,-1, 7,0); + vcdp->declBus(c+3721,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_out", false,-1, 2,0); + vcdp->declBit(c+3681,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+4081,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache cache_core_rsp_merge WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache cache_core_rsp_merge NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache cache_core_rsp_merge CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_core_rsp_merge clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_core_rsp_merge reset", false,-1); + vcdp->declBus(c+2129,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tid", false,-1, 15,0); + vcdp->declBus(c+2121,"VX_cache cache_core_rsp_merge per_bank_core_rsp_valid", false,-1, 7,0); + vcdp->declArray(c+2137,"VX_cache cache_core_rsp_merge per_bank_core_rsp_data", false,-1, 255,0); + vcdp->declArray(c+2201,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tag", false,-1, 335,0); + vcdp->declBus(c+9,"VX_cache cache_core_rsp_merge per_bank_core_rsp_ready", false,-1, 7,0); + vcdp->declBus(c+58137,"VX_cache cache_core_rsp_merge core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+4089,"VX_cache cache_core_rsp_merge core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+4121,"VX_cache cache_core_rsp_merge core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+58193,"VX_cache cache_core_rsp_merge core_rsp_ready", false,-1); + vcdp->declBus(c+4137,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 7,0); + vcdp->declBus(c+4145,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 2,0); + vcdp->declBit(c+4153,"VX_cache cache_core_rsp_merge grant_valid", false,-1); + vcdp->declBus(c+58737,"VX_cache cache_core_rsp_merge i", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache cache_core_rsp_merge sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache cache_core_rsp_merge sel_bank reset", false,-1); + vcdp->declBus(c+2121,"VX_cache cache_core_rsp_merge sel_bank requests", false,-1, 7,0); + vcdp->declBus(c+4145,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 2,0); + vcdp->declBus(c+4161,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 7,0); + vcdp->declBit(c+4153,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1); + vcdp->declBus(c+20865,"VX_cache cache_core_rsp_merge sel_bank genblk2 requests_use", false,-1, 7,0); + vcdp->declBus(c+4169,"VX_cache cache_core_rsp_merge sel_bank genblk2 update_value", false,-1, 7,0); + vcdp->declBus(c+4177,"VX_cache cache_core_rsp_merge sel_bank genblk2 late_value", false,-1, 7,0); + vcdp->declBit(c+20873,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill", false,-1); + vcdp->declBus(c+2121,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_value", false,-1, 7,0); + vcdp->declBus(c+20881,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_original", false,-1, 7,0); + vcdp->declBus(c+4161,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 7,0); + vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+20865,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_in", false,-1, 7,0); + vcdp->declBus(c+4145,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 2,0); + vcdp->declBit(c+4153,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+4185,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache snp_rsp_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache snp_rsp_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache snp_rsp_arb SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache snp_rsp_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache snp_rsp_arb reset", false,-1); + vcdp->declBus(c+2721,"VX_cache snp_rsp_arb per_bank_snp_rsp_valid", false,-1, 7,0); + vcdp->declArray(c+2729,"VX_cache snp_rsp_arb per_bank_snp_rsp_tag", false,-1, 223,0); + vcdp->declBus(c+25,"VX_cache snp_rsp_arb per_bank_snp_rsp_ready", false,-1, 7,0); + vcdp->declBit(c+58377,"VX_cache snp_rsp_arb snp_rsp_valid", false,-1); + vcdp->declBus(c+58385,"VX_cache snp_rsp_arb snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+58393,"VX_cache snp_rsp_arb snp_rsp_ready", false,-1); + vcdp->declBus(c+4193,"VX_cache snp_rsp_arb fsq_bank", false,-1, 2,0); + vcdp->declBit(c+4201,"VX_cache snp_rsp_arb fsq_valid", false,-1); + vcdp->declBus(c+58665,"VX_cache snp_rsp_arb sel_ffsq N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache snp_rsp_arb sel_ffsq clk", false,-1); + vcdp->declBit(c+58017,"VX_cache snp_rsp_arb sel_ffsq reset", false,-1); + vcdp->declBus(c+2721,"VX_cache snp_rsp_arb sel_ffsq requests", false,-1, 7,0); + vcdp->declBus(c+4193,"VX_cache snp_rsp_arb sel_ffsq grant_index", false,-1, 2,0); + vcdp->declBus(c+4209,"VX_cache snp_rsp_arb sel_ffsq grant_onehot", false,-1, 7,0); + vcdp->declBit(c+4201,"VX_cache snp_rsp_arb sel_ffsq grant_valid", false,-1); + vcdp->declBus(c+4209,"VX_cache snp_rsp_arb sel_ffsq genblk2 grant_onehot_r", false,-1, 7,0); + vcdp->declBus(c+58665,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+2721,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_in", false,-1, 7,0); + vcdp->declBus(c+4193,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_out", false,-1, 2,0); + vcdp->declBit(c+4201,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+4217,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[0] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58745,"VX_cache genblk5[0] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[0] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[0] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[0] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[0] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank reset", false,-1); + vcdp->declBus(c+33,"VX_cache genblk5[0] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[0] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[0] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[0] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[0] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[0] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19689,"VX_cache genblk5[0] bank core_req_ready", false,-1); + vcdp->declBit(c+19657,"VX_cache genblk5[0] bank core_rsp_valid", false,-1); + vcdp->declBus(c+2785,"VX_cache genblk5[0] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+2793,"VX_cache genblk5[0] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+2801,"VX_cache genblk5[0] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+41,"VX_cache genblk5[0] bank core_rsp_ready", false,-1); + vcdp->declBit(c+2817,"VX_cache genblk5[0] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19673,"VX_cache genblk5[0] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[0] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58481,"VX_cache genblk5[0] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[0] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[0] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19665,"VX_cache genblk5[0] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+2825,"VX_cache genblk5[0] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+2833,"VX_cache genblk5[0] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+2841,"VX_cache genblk5[0] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+2849,"VX_cache genblk5[0] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+49,"VX_cache genblk5[0] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58497,"VX_cache genblk5[0] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[0] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[0] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[0] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19681,"VX_cache genblk5[0] bank snp_req_ready", false,-1); + vcdp->declBit(c+2881,"VX_cache genblk5[0] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+2889,"VX_cache genblk5[0] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+57,"VX_cache genblk5[0] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+4225,"VX_cache genblk5[0] bank snrq_pop", false,-1); + vcdp->declBit(c+20889,"VX_cache genblk5[0] bank snrq_empty", false,-1); + vcdp->declBit(c+20897,"VX_cache genblk5[0] bank snrq_full", false,-1); + vcdp->declBus(c+4233,"VX_cache genblk5[0] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+4241,"VX_cache genblk5[0] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+4249,"VX_cache genblk5[0] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+4257,"VX_cache genblk5[0] bank dfpq_pop", false,-1); + vcdp->declBit(c+20905,"VX_cache genblk5[0] bank dfpq_empty", false,-1); + vcdp->declBit(c+20913,"VX_cache genblk5[0] bank dfpq_full", false,-1); + vcdp->declBus(c+4265,"VX_cache genblk5[0] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+4273,"VX_cache genblk5[0] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+4305,"VX_cache genblk5[0] bank reqq_pop", false,-1); + vcdp->declBit(c+1857,"VX_cache genblk5[0] bank reqq_push", false,-1); + vcdp->declBit(c+4313,"VX_cache genblk5[0] bank reqq_empty", false,-1); + vcdp->declBit(c+20921,"VX_cache genblk5[0] bank reqq_full", false,-1); + vcdp->declBit(c+4321,"VX_cache genblk5[0] bank reqq_req_st0", false,-1); + vcdp->declBus(c+4329,"VX_cache genblk5[0] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+4337,"VX_cache genblk5[0] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+4345,"VX_cache genblk5[0] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+4353,"VX_cache genblk5[0] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+4361,"VX_cache genblk5[0] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4369,"VX_cache genblk5[0] bank mrvq_pop", false,-1); + vcdp->declBit(c+20945,"VX_cache genblk5[0] bank mrvq_full", false,-1); + vcdp->declBit(c+20953,"VX_cache genblk5[0] bank mrvq_stop", false,-1); + vcdp->declBit(c+4377,"VX_cache genblk5[0] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+20961,"VX_cache genblk5[0] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+20969,"VX_cache genblk5[0] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+20977,"VX_cache genblk5[0] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+20985,"VX_cache genblk5[0] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+20993,"VX_cache genblk5[0] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4385,"VX_cache genblk5[0] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+21009,"VX_cache genblk5[0] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+21017,"VX_cache genblk5[0] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[0] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+4393,"VX_cache genblk5[0] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+4401,"VX_cache genblk5[0] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+4409,"VX_cache genblk5[0] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+21033,"VX_cache genblk5[0] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+21041,"VX_cache genblk5[0] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+21057,"VX_cache genblk5[0] bank miss_add_rw", false,-1); + vcdp->declBus(c+21065,"VX_cache genblk5[0] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19673,"VX_cache genblk5[0] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+21073,"VX_cache genblk5[0] bank is_fill_st2", false,-1); + vcdp->declBit(c+4417,"VX_cache genblk5[0] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+4425,"VX_cache genblk5[0] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+4433,"VX_cache genblk5[0] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+4441,"VX_cache genblk5[0] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+4449,"VX_cache genblk5[0] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[0] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+4465,"VX_cache genblk5[0] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4473+i*1,"VX_cache genblk5[0] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4481+i*1,"VX_cache genblk5[0] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[0] bank j", false,-1, 31,0); + vcdp->declBit(c+4377,"VX_cache genblk5[0] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+4489,"VX_cache genblk5[0] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+4497,"VX_cache genblk5[0] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+4505,"VX_cache genblk5[0] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+4489,"VX_cache genblk5[0] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[0] bank qual_valid_st0", false,-1); + vcdp->declBus(c+4521,"VX_cache genblk5[0] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+4529,"VX_cache genblk5[0] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+4377,"VX_cache genblk5[0] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+4537,"VX_cache genblk5[0] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+4545,"VX_cache genblk5[0] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+4577,"VX_cache genblk5[0] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+4593,"VX_cache genblk5[0] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+4601,"VX_cache genblk5[0] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+4609,"VX_cache genblk5[0] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4617+i*1,"VX_cache genblk5[0] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+4625+i*1,"VX_cache genblk5[0] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+4633+i*1,"VX_cache genblk5[0] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+4641+i*1,"VX_cache genblk5[0] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+4649+i*2,"VX_cache genblk5[0] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+4665+i*4,"VX_cache genblk5[0] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4697+i*1,"VX_cache genblk5[0] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4705+i*1,"VX_cache genblk5[0] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+4713+i*1,"VX_cache genblk5[0] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+4721,"VX_cache genblk5[0] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+4729,"VX_cache genblk5[0] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+4761,"VX_cache genblk5[0] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+4769,"VX_cache genblk5[0] bank miss_st1e", false,-1); + vcdp->declBit(c+4777,"VX_cache genblk5[0] bank dirty_st1e", false,-1); + vcdp->declBus(c+4785,"VX_cache genblk5[0] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+4793,"VX_cache genblk5[0] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+4809,"VX_cache genblk5[0] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+4817,"VX_cache genblk5[0] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+4825,"VX_cache genblk5[0] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+4833,"VX_cache genblk5[0] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+4841,"VX_cache genblk5[0] bank is_snp_st1e", false,-1); + vcdp->declBit(c+4849,"VX_cache genblk5[0] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+4857,"VX_cache genblk5[0] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+4865,"VX_cache genblk5[0] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+4873,"VX_cache genblk5[0] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+4881,"VX_cache genblk5[0] bank valid_st1e", false,-1); + vcdp->declBit(c+4889,"VX_cache genblk5[0] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+4897,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+4905,"VX_cache genblk5[0] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+4913,"VX_cache genblk5[0] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+4889,"VX_cache genblk5[0] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+21081,"VX_cache genblk5[0] bank valid_st2", false,-1); + vcdp->declBus(c+21089,"VX_cache genblk5[0] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+21097,"VX_cache genblk5[0] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+21105,"VX_cache genblk5[0] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+21113,"VX_cache genblk5[0] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+21145,"VX_cache genblk5[0] bank miss_st2", false,-1); + vcdp->declBit(c+21153,"VX_cache genblk5[0] bank dirty_st2", false,-1); + vcdp->declBus(c+21161,"VX_cache genblk5[0] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+21169,"VX_cache genblk5[0] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+21185,"VX_cache genblk5[0] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+21193,"VX_cache genblk5[0] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+21201,"VX_cache genblk5[0] bank is_snp_st2", false,-1); + vcdp->declBit(c+21209,"VX_cache genblk5[0] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+21217,"VX_cache genblk5[0] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+21225,"VX_cache genblk5[0] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+4921,"VX_cache genblk5[0] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+21233,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+21241,"VX_cache genblk5[0] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+4929,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+4937,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+21217,"VX_cache genblk5[0] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+4945,"VX_cache genblk5[0] bank miss_add_unqual", false,-1); + vcdp->declBit(c+4953,"VX_cache genblk5[0] bank miss_add", false,-1); + vcdp->declBus(c+19673,"VX_cache genblk5[0] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+21089,"VX_cache genblk5[0] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+21097,"VX_cache genblk5[0] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+21201,"VX_cache genblk5[0] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+21209,"VX_cache genblk5[0] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+4961,"VX_cache genblk5[0] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+4969,"VX_cache genblk5[0] bank cwbq_push", false,-1); + vcdp->declBit(c+1865,"VX_cache genblk5[0] bank cwbq_pop", false,-1); + vcdp->declBit(c+21249,"VX_cache genblk5[0] bank cwbq_empty", false,-1); + vcdp->declBit(c+21257,"VX_cache genblk5[0] bank cwbq_full", false,-1); + vcdp->declBit(c+4977,"VX_cache genblk5[0] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+21105,"VX_cache genblk5[0] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+21033,"VX_cache genblk5[0] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+21041,"VX_cache genblk5[0] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+4945,"VX_cache genblk5[0] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+4985,"VX_cache genblk5[0] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+4993,"VX_cache genblk5[0] bank dwbq_push", false,-1); + vcdp->declBit(c+1873,"VX_cache genblk5[0] bank dwbq_pop", false,-1); + vcdp->declBit(c+21265,"VX_cache genblk5[0] bank dwbq_empty", false,-1); + vcdp->declBit(c+21273,"VX_cache genblk5[0] bank dwbq_full", false,-1); + vcdp->declBit(c+5001,"VX_cache genblk5[0] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+5009,"VX_cache genblk5[0] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+5017,"VX_cache genblk5[0] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+5025,"VX_cache genblk5[0] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+5033,"VX_cache genblk5[0] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+21281,"VX_cache genblk5[0] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+21289,"VX_cache genblk5[0] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+313,"VX_cache genblk5[0] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+321,"VX_cache genblk5[0] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+21297,"VX_cache genblk5[0] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[0] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58497,"VX_cache genblk5[0] bank snp_req_queue push", false,-1); + vcdp->declBit(c+4225,"VX_cache genblk5[0] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+329,"VX_cache genblk5[0] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+5041,"VX_cache genblk5[0] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+20889,"VX_cache genblk5[0] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+20897,"VX_cache genblk5[0] bank snp_req_queue full", false,-1); + vcdp->declBus(c+21305,"VX_cache genblk5[0] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+21305,"VX_cache genblk5[0] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+5057,"VX_cache genblk5[0] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+345,"VX_cache genblk5[0] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+21313+i*2,"VX_cache genblk5[0] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+21569,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+21585,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+21601,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+21609,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+21617,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+20889,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+20897,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+21625,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[0] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58481,"VX_cache genblk5[0] bank dfp_queue push", false,-1); + vcdp->declBit(c+4257,"VX_cache genblk5[0] bank dfp_queue pop", false,-1); + vcdp->declArray(c+353,"VX_cache genblk5[0] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+5065,"VX_cache genblk5[0] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+20905,"VX_cache genblk5[0] bank dfp_queue empty", false,-1); + vcdp->declBit(c+20913,"VX_cache genblk5[0] bank dfp_queue full", false,-1); + vcdp->declBus(c+21633,"VX_cache genblk5[0] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+21633,"VX_cache genblk5[0] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+5105,"VX_cache genblk5[0] bank dfp_queue reading", false,-1); + vcdp->declBit(c+393,"VX_cache genblk5[0] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+21641+i*5,"VX_cache genblk5[0] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+22281,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+22321,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+22361,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+22369,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+22377,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+20905,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+20913,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+22385,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1857,"VX_cache genblk5[0] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+33,"VX_cache genblk5[0] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[0] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[0] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[0] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[0] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[0] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+4305,"VX_cache genblk5[0] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+4337,"VX_cache genblk5[0] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+4345,"VX_cache genblk5[0] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+4353,"VX_cache genblk5[0] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+4361,"VX_cache genblk5[0] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4313,"VX_cache genblk5[0] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+20921,"VX_cache genblk5[0] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+5113,"VX_cache genblk5[0] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+5121,"VX_cache genblk5[0] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+5129,"VX_cache genblk5[0] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+5137,"VX_cache genblk5[0] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+5169,"VX_cache genblk5[0] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+5201,"VX_cache genblk5[0] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+22401,"VX_cache genblk5[0] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+22409,"VX_cache genblk5[0] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+22417,"VX_cache genblk5[0] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+22449,"VX_cache genblk5[0] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+22401,"VX_cache genblk5[0] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+22409,"VX_cache genblk5[0] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+22417,"VX_cache genblk5[0] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+22449,"VX_cache genblk5[0] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+22481,"VX_cache genblk5[0] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+22489,"VX_cache genblk5[0] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+5217,"VX_cache genblk5[0] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1881,"VX_cache genblk5[0] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+5225,"VX_cache genblk5[0] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+5233,"VX_cache genblk5[0] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[0] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1881,"VX_cache genblk5[0] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+5225,"VX_cache genblk5[0] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+401,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+5241,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+22481,"VX_cache genblk5[0] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+20921,"VX_cache genblk5[0] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+22497,"VX_cache genblk5[0] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+22497,"VX_cache genblk5[0] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+5321,"VX_cache genblk5[0] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+481,"VX_cache genblk5[0] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+22505+i*10,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+23145,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+23225,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+23305,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+23313,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+23321,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+22481,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+20921,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+23329,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+5329,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+5329,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+5337,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[0] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[0] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[0] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[0] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+5345,"VX_cache genblk5[0] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+23337,"VX_cache genblk5[0] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+23337,"VX_cache genblk5[0] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[0] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank tag_data_access reset", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access stall", false,-1); + vcdp->declBit(c+4841,"VX_cache genblk5[0] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+4849,"VX_cache genblk5[0] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+4409,"VX_cache genblk5[0] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+4905,"VX_cache genblk5[0] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+4881,"VX_cache genblk5[0] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+5417,"VX_cache genblk5[0] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+5425,"VX_cache genblk5[0] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+5433,"VX_cache genblk5[0] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+4817,"VX_cache genblk5[0] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+4825,"VX_cache genblk5[0] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+5465,"VX_cache genblk5[0] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+4721,"VX_cache genblk5[0] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+4729,"VX_cache genblk5[0] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+4761,"VX_cache genblk5[0] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+4769,"VX_cache genblk5[0] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+4777,"VX_cache genblk5[0] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+4785,"VX_cache genblk5[0] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+4833,"VX_cache genblk5[0] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+4857,"VX_cache genblk5[0] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+4865,"VX_cache genblk5[0] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+5473+i*1,"VX_cache genblk5[0] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+5481+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+5489+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+5497+i*1,"VX_cache genblk5[0] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+5505+i*4,"VX_cache genblk5[0] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+5537,"VX_cache genblk5[0] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+5545,"VX_cache genblk5[0] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+5553,"VX_cache genblk5[0] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+5561,"VX_cache genblk5[0] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+5569,"VX_cache genblk5[0] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+5601,"VX_cache genblk5[0] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+5609,"VX_cache genblk5[0] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+4785,"VX_cache genblk5[0] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+4761,"VX_cache genblk5[0] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+4729,"VX_cache genblk5[0] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+5617,"VX_cache genblk5[0] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+5625,"VX_cache genblk5[0] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+4769,"VX_cache genblk5[0] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+5657,"VX_cache genblk5[0] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+5665,"VX_cache genblk5[0] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+5673,"VX_cache genblk5[0] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+5681,"VX_cache genblk5[0] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+5689,"VX_cache genblk5[0] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+5625,"VX_cache genblk5[0] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+5697,"VX_cache genblk5[0] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+5657,"VX_cache genblk5[0] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+5705,"VX_cache genblk5[0] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+5713,"VX_cache genblk5[0] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+5721,"VX_cache genblk5[0] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+5729,"VX_cache genblk5[0] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+5737,"VX_cache genblk5[0] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+5745,"VX_cache genblk5[0] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+5753,"VX_cache genblk5[0] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+5761,"VX_cache genblk5[0] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[0] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+5537,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+5545,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+5553,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+5561,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+5569,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+5657,"VX_cache genblk5[0] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+5617,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+5673,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+5681,"VX_cache genblk5[0] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+5625,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+4769,"VX_cache genblk5[0] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+23401,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+23433,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+23465,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+23497,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+23529,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+23561,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+23593,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+23625,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+23657,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+23689,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+23721,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+23753,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+23785,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+23817,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+23849,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+23881,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+23913+i*1,"VX_cache genblk5[0] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+24041,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+24049,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+24057,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+24065,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+24073,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+24081,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+24089,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+24097,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+24105,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+24113,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+24121,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+24129,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+24137,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+24145,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+24153,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+24161,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+24169,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+24177,"VX_cache genblk5[0] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+5769,"VX_cache genblk5[0] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+24185,"VX_cache genblk5[0] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+24193,"VX_cache genblk5[0] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+5777,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+5777,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+24201,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[0] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[0] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[0] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[0] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+5825,"VX_cache genblk5[0] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+24249,"VX_cache genblk5[0] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+24249,"VX_cache genblk5[0] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[0] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58745,"VX_cache genblk5[0] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[0] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[0] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[0] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+4953,"VX_cache genblk5[0] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+4961,"VX_cache genblk5[0] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19673,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+21089,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+21097,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+21033,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+21041,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+21057,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+21065,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+4921,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+21201,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+21209,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+20945,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+20953,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+5417,"VX_cache genblk5[0] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+4905,"VX_cache genblk5[0] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+4393,"VX_cache genblk5[0] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+4369,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+4377,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+20969,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+20977,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+20985,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+20961,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+20993,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4385,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+21009,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+21017,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+24329+i*3,"VX_cache genblk5[0] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+24713,"VX_cache genblk5[0] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+24817,"VX_cache genblk5[0] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+24825,"VX_cache genblk5[0] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+24833,"VX_cache genblk5[0] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+24841,"VX_cache genblk5[0] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+24849,"VX_cache genblk5[0] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+24857,"VX_cache genblk5[0] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+24865,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+24849,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+5905,"VX_cache genblk5[0] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+5913,"VX_cache genblk5[0] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+5921,"VX_cache genblk5[0] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+4377,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+24833,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+5929,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+5937,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+5945,"VX_cache genblk5[0] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+5953,"VX_cache genblk5[0] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+5961,"VX_cache genblk5[0] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+5969,"VX_cache genblk5[0] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[0] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[0] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank cwb_queue reset", false,-1); + vcdp->declBit(c+4969,"VX_cache genblk5[0] bank cwb_queue push", false,-1); + vcdp->declBit(c+1865,"VX_cache genblk5[0] bank cwb_queue pop", false,-1); + vcdp->declArray(c+5977,"VX_cache genblk5[0] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+6001,"VX_cache genblk5[0] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+21249,"VX_cache genblk5[0] bank cwb_queue empty", false,-1); + vcdp->declBit(c+21257,"VX_cache genblk5[0] bank cwb_queue full", false,-1); + vcdp->declBus(c+24873,"VX_cache genblk5[0] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+24873,"VX_cache genblk5[0] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+489,"VX_cache genblk5[0] bank cwb_queue reading", false,-1); + vcdp->declBit(c+6025,"VX_cache genblk5[0] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+24881+i*3,"VX_cache genblk5[0] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+25073,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+25097,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+25121,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+25129,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+25137,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+21249,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21257,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+25145,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[0] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[0] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[0] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[0] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[0] bank dwb_queue reset", false,-1); + vcdp->declBit(c+4993,"VX_cache genblk5[0] bank dwb_queue push", false,-1); + vcdp->declBit(c+1873,"VX_cache genblk5[0] bank dwb_queue pop", false,-1); + vcdp->declArray(c+6033,"VX_cache genblk5[0] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+6089,"VX_cache genblk5[0] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+21265,"VX_cache genblk5[0] bank dwb_queue empty", false,-1); + vcdp->declBit(c+21273,"VX_cache genblk5[0] bank dwb_queue full", false,-1); + vcdp->declBus(c+25153,"VX_cache genblk5[0] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+25153,"VX_cache genblk5[0] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+497,"VX_cache genblk5[0] bank dwb_queue reading", false,-1); + vcdp->declBit(c+6145,"VX_cache genblk5[0] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+25161+i*7,"VX_cache genblk5[0] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+25385,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+25441,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+25497,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+25505,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+25513,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+21265,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21273,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+25521,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58641,"VX_cache genblk5[1] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58753,"VX_cache genblk5[1] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[1] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[1] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[1] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[1] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank reset", false,-1); + vcdp->declBus(c+65,"VX_cache genblk5[1] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[1] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[1] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[1] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[1] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[1] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19729,"VX_cache genblk5[1] bank core_req_ready", false,-1); + vcdp->declBit(c+19697,"VX_cache genblk5[1] bank core_rsp_valid", false,-1); + vcdp->declBus(c+2897,"VX_cache genblk5[1] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+2905,"VX_cache genblk5[1] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+2913,"VX_cache genblk5[1] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+73,"VX_cache genblk5[1] bank core_rsp_ready", false,-1); + vcdp->declBit(c+2929,"VX_cache genblk5[1] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19713,"VX_cache genblk5[1] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[1] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58513,"VX_cache genblk5[1] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[1] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[1] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19705,"VX_cache genblk5[1] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+2937,"VX_cache genblk5[1] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+2945,"VX_cache genblk5[1] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+2953,"VX_cache genblk5[1] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+2961,"VX_cache genblk5[1] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+81,"VX_cache genblk5[1] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58521,"VX_cache genblk5[1] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[1] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[1] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[1] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19721,"VX_cache genblk5[1] bank snp_req_ready", false,-1); + vcdp->declBit(c+2993,"VX_cache genblk5[1] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+3001,"VX_cache genblk5[1] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+89,"VX_cache genblk5[1] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+6153,"VX_cache genblk5[1] bank snrq_pop", false,-1); + vcdp->declBit(c+25529,"VX_cache genblk5[1] bank snrq_empty", false,-1); + vcdp->declBit(c+25537,"VX_cache genblk5[1] bank snrq_full", false,-1); + vcdp->declBus(c+6161,"VX_cache genblk5[1] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+6169,"VX_cache genblk5[1] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+6177,"VX_cache genblk5[1] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+6185,"VX_cache genblk5[1] bank dfpq_pop", false,-1); + vcdp->declBit(c+25545,"VX_cache genblk5[1] bank dfpq_empty", false,-1); + vcdp->declBit(c+25553,"VX_cache genblk5[1] bank dfpq_full", false,-1); + vcdp->declBus(c+6193,"VX_cache genblk5[1] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+6201,"VX_cache genblk5[1] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+6233,"VX_cache genblk5[1] bank reqq_pop", false,-1); + vcdp->declBit(c+1889,"VX_cache genblk5[1] bank reqq_push", false,-1); + vcdp->declBit(c+6241,"VX_cache genblk5[1] bank reqq_empty", false,-1); + vcdp->declBit(c+25561,"VX_cache genblk5[1] bank reqq_full", false,-1); + vcdp->declBit(c+6249,"VX_cache genblk5[1] bank reqq_req_st0", false,-1); + vcdp->declBus(c+6257,"VX_cache genblk5[1] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+6265,"VX_cache genblk5[1] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+6273,"VX_cache genblk5[1] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+6281,"VX_cache genblk5[1] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+6289,"VX_cache genblk5[1] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6297,"VX_cache genblk5[1] bank mrvq_pop", false,-1); + vcdp->declBit(c+25585,"VX_cache genblk5[1] bank mrvq_full", false,-1); + vcdp->declBit(c+25593,"VX_cache genblk5[1] bank mrvq_stop", false,-1); + vcdp->declBit(c+6305,"VX_cache genblk5[1] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+25601,"VX_cache genblk5[1] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+25609,"VX_cache genblk5[1] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+25617,"VX_cache genblk5[1] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+25625,"VX_cache genblk5[1] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+25633,"VX_cache genblk5[1] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6313,"VX_cache genblk5[1] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+25649,"VX_cache genblk5[1] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+25657,"VX_cache genblk5[1] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+25665,"VX_cache genblk5[1] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+6321,"VX_cache genblk5[1] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+6329,"VX_cache genblk5[1] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+6337,"VX_cache genblk5[1] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+25673,"VX_cache genblk5[1] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+25681,"VX_cache genblk5[1] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+25697,"VX_cache genblk5[1] bank miss_add_rw", false,-1); + vcdp->declBus(c+25705,"VX_cache genblk5[1] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19713,"VX_cache genblk5[1] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+25713,"VX_cache genblk5[1] bank is_fill_st2", false,-1); + vcdp->declBit(c+6345,"VX_cache genblk5[1] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+6353,"VX_cache genblk5[1] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+6361,"VX_cache genblk5[1] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+6369,"VX_cache genblk5[1] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+6377,"VX_cache genblk5[1] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[1] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+6393,"VX_cache genblk5[1] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6401+i*1,"VX_cache genblk5[1] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6409+i*1,"VX_cache genblk5[1] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[1] bank j", false,-1, 31,0); + vcdp->declBit(c+6305,"VX_cache genblk5[1] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+6417,"VX_cache genblk5[1] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+6425,"VX_cache genblk5[1] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+6433,"VX_cache genblk5[1] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+6417,"VX_cache genblk5[1] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[1] bank qual_valid_st0", false,-1); + vcdp->declBus(c+6449,"VX_cache genblk5[1] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+6457,"VX_cache genblk5[1] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+6305,"VX_cache genblk5[1] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+6465,"VX_cache genblk5[1] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+6473,"VX_cache genblk5[1] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+6505,"VX_cache genblk5[1] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+6521,"VX_cache genblk5[1] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+6529,"VX_cache genblk5[1] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+6537,"VX_cache genblk5[1] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6545+i*1,"VX_cache genblk5[1] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+6553+i*1,"VX_cache genblk5[1] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+6561+i*1,"VX_cache genblk5[1] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+6569+i*1,"VX_cache genblk5[1] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+6577+i*2,"VX_cache genblk5[1] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+6593+i*4,"VX_cache genblk5[1] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6625+i*1,"VX_cache genblk5[1] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6633+i*1,"VX_cache genblk5[1] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+6641+i*1,"VX_cache genblk5[1] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+6649,"VX_cache genblk5[1] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+6657,"VX_cache genblk5[1] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+6689,"VX_cache genblk5[1] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+6697,"VX_cache genblk5[1] bank miss_st1e", false,-1); + vcdp->declBit(c+6705,"VX_cache genblk5[1] bank dirty_st1e", false,-1); + vcdp->declBus(c+6713,"VX_cache genblk5[1] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+6721,"VX_cache genblk5[1] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+6737,"VX_cache genblk5[1] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+6745,"VX_cache genblk5[1] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+6753,"VX_cache genblk5[1] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+6761,"VX_cache genblk5[1] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+6769,"VX_cache genblk5[1] bank is_snp_st1e", false,-1); + vcdp->declBit(c+6777,"VX_cache genblk5[1] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+6785,"VX_cache genblk5[1] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+6793,"VX_cache genblk5[1] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+6801,"VX_cache genblk5[1] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+6809,"VX_cache genblk5[1] bank valid_st1e", false,-1); + vcdp->declBit(c+6817,"VX_cache genblk5[1] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+6825,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+6833,"VX_cache genblk5[1] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+6841,"VX_cache genblk5[1] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+6817,"VX_cache genblk5[1] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+25721,"VX_cache genblk5[1] bank valid_st2", false,-1); + vcdp->declBus(c+25729,"VX_cache genblk5[1] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+25737,"VX_cache genblk5[1] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+25745,"VX_cache genblk5[1] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+25753,"VX_cache genblk5[1] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+25785,"VX_cache genblk5[1] bank miss_st2", false,-1); + vcdp->declBit(c+25793,"VX_cache genblk5[1] bank dirty_st2", false,-1); + vcdp->declBus(c+25801,"VX_cache genblk5[1] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+25809,"VX_cache genblk5[1] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+25825,"VX_cache genblk5[1] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+25833,"VX_cache genblk5[1] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+25841,"VX_cache genblk5[1] bank is_snp_st2", false,-1); + vcdp->declBit(c+25849,"VX_cache genblk5[1] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+25857,"VX_cache genblk5[1] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+25865,"VX_cache genblk5[1] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+6849,"VX_cache genblk5[1] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+25873,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+25881,"VX_cache genblk5[1] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+6857,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+6865,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+25857,"VX_cache genblk5[1] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+6873,"VX_cache genblk5[1] bank miss_add_unqual", false,-1); + vcdp->declBit(c+6881,"VX_cache genblk5[1] bank miss_add", false,-1); + vcdp->declBus(c+19713,"VX_cache genblk5[1] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+25729,"VX_cache genblk5[1] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+25737,"VX_cache genblk5[1] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+25841,"VX_cache genblk5[1] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+25849,"VX_cache genblk5[1] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+6889,"VX_cache genblk5[1] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+6897,"VX_cache genblk5[1] bank cwbq_push", false,-1); + vcdp->declBit(c+1897,"VX_cache genblk5[1] bank cwbq_pop", false,-1); + vcdp->declBit(c+25889,"VX_cache genblk5[1] bank cwbq_empty", false,-1); + vcdp->declBit(c+25897,"VX_cache genblk5[1] bank cwbq_full", false,-1); + vcdp->declBit(c+6905,"VX_cache genblk5[1] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+25745,"VX_cache genblk5[1] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+25673,"VX_cache genblk5[1] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+25681,"VX_cache genblk5[1] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+6873,"VX_cache genblk5[1] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+6913,"VX_cache genblk5[1] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+6921,"VX_cache genblk5[1] bank dwbq_push", false,-1); + vcdp->declBit(c+1905,"VX_cache genblk5[1] bank dwbq_pop", false,-1); + vcdp->declBit(c+25905,"VX_cache genblk5[1] bank dwbq_empty", false,-1); + vcdp->declBit(c+25913,"VX_cache genblk5[1] bank dwbq_full", false,-1); + vcdp->declBit(c+6929,"VX_cache genblk5[1] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+6937,"VX_cache genblk5[1] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+6945,"VX_cache genblk5[1] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+6953,"VX_cache genblk5[1] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+6961,"VX_cache genblk5[1] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+25921,"VX_cache genblk5[1] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+25929,"VX_cache genblk5[1] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+505,"VX_cache genblk5[1] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+513,"VX_cache genblk5[1] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+25937,"VX_cache genblk5[1] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[1] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58521,"VX_cache genblk5[1] bank snp_req_queue push", false,-1); + vcdp->declBit(c+6153,"VX_cache genblk5[1] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+521,"VX_cache genblk5[1] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+6969,"VX_cache genblk5[1] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+25529,"VX_cache genblk5[1] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+25537,"VX_cache genblk5[1] bank snp_req_queue full", false,-1); + vcdp->declBus(c+25945,"VX_cache genblk5[1] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+25945,"VX_cache genblk5[1] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+6985,"VX_cache genblk5[1] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+537,"VX_cache genblk5[1] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+25953+i*2,"VX_cache genblk5[1] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+26209,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+26225,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+26241,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+26249,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+26257,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+25529,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+25537,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+26265,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[1] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58513,"VX_cache genblk5[1] bank dfp_queue push", false,-1); + vcdp->declBit(c+6185,"VX_cache genblk5[1] bank dfp_queue pop", false,-1); + vcdp->declArray(c+545,"VX_cache genblk5[1] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+6993,"VX_cache genblk5[1] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+25545,"VX_cache genblk5[1] bank dfp_queue empty", false,-1); + vcdp->declBit(c+25553,"VX_cache genblk5[1] bank dfp_queue full", false,-1); + vcdp->declBus(c+26273,"VX_cache genblk5[1] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+26273,"VX_cache genblk5[1] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+7033,"VX_cache genblk5[1] bank dfp_queue reading", false,-1); + vcdp->declBit(c+585,"VX_cache genblk5[1] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+26281+i*5,"VX_cache genblk5[1] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+26921,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+26961,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+27001,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+27009,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+27017,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+25545,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+25553,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+27025,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1889,"VX_cache genblk5[1] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+65,"VX_cache genblk5[1] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[1] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[1] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[1] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[1] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[1] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+6233,"VX_cache genblk5[1] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+6265,"VX_cache genblk5[1] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+6273,"VX_cache genblk5[1] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+6281,"VX_cache genblk5[1] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+6289,"VX_cache genblk5[1] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6241,"VX_cache genblk5[1] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+25561,"VX_cache genblk5[1] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+7041,"VX_cache genblk5[1] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+7049,"VX_cache genblk5[1] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+7057,"VX_cache genblk5[1] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+7065,"VX_cache genblk5[1] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+7097,"VX_cache genblk5[1] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+7129,"VX_cache genblk5[1] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+27041,"VX_cache genblk5[1] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+27049,"VX_cache genblk5[1] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+27057,"VX_cache genblk5[1] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+27089,"VX_cache genblk5[1] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+27041,"VX_cache genblk5[1] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+27049,"VX_cache genblk5[1] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+27057,"VX_cache genblk5[1] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+27089,"VX_cache genblk5[1] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+27121,"VX_cache genblk5[1] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+27129,"VX_cache genblk5[1] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+7145,"VX_cache genblk5[1] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1913,"VX_cache genblk5[1] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+7153,"VX_cache genblk5[1] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+7161,"VX_cache genblk5[1] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[1] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1913,"VX_cache genblk5[1] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+7153,"VX_cache genblk5[1] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+593,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+7169,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+27121,"VX_cache genblk5[1] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+25561,"VX_cache genblk5[1] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+27137,"VX_cache genblk5[1] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+27137,"VX_cache genblk5[1] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+7249,"VX_cache genblk5[1] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+673,"VX_cache genblk5[1] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+27145+i*10,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+27785,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+27865,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+27945,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+27953,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+27961,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+27121,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+25561,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+27969,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+7257,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+7257,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+7265,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[1] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[1] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[1] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[1] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+7273,"VX_cache genblk5[1] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+27977,"VX_cache genblk5[1] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+27977,"VX_cache genblk5[1] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[1] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank tag_data_access reset", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access stall", false,-1); + vcdp->declBit(c+6769,"VX_cache genblk5[1] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+6777,"VX_cache genblk5[1] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+6337,"VX_cache genblk5[1] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+6833,"VX_cache genblk5[1] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+6809,"VX_cache genblk5[1] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+7345,"VX_cache genblk5[1] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+7353,"VX_cache genblk5[1] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+7361,"VX_cache genblk5[1] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+6745,"VX_cache genblk5[1] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+6753,"VX_cache genblk5[1] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+7393,"VX_cache genblk5[1] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+6649,"VX_cache genblk5[1] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+6657,"VX_cache genblk5[1] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+6689,"VX_cache genblk5[1] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+6697,"VX_cache genblk5[1] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+6705,"VX_cache genblk5[1] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+6713,"VX_cache genblk5[1] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+6761,"VX_cache genblk5[1] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+6785,"VX_cache genblk5[1] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+6793,"VX_cache genblk5[1] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+7401+i*1,"VX_cache genblk5[1] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+7409+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+7417+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+7425+i*1,"VX_cache genblk5[1] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+7433+i*4,"VX_cache genblk5[1] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+7465,"VX_cache genblk5[1] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+7473,"VX_cache genblk5[1] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+7481,"VX_cache genblk5[1] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+7489,"VX_cache genblk5[1] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+7497,"VX_cache genblk5[1] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+7529,"VX_cache genblk5[1] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+7537,"VX_cache genblk5[1] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+6713,"VX_cache genblk5[1] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+6689,"VX_cache genblk5[1] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+6657,"VX_cache genblk5[1] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+7545,"VX_cache genblk5[1] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+7553,"VX_cache genblk5[1] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+6697,"VX_cache genblk5[1] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+7585,"VX_cache genblk5[1] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+7593,"VX_cache genblk5[1] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+7601,"VX_cache genblk5[1] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+7609,"VX_cache genblk5[1] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+7617,"VX_cache genblk5[1] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+7553,"VX_cache genblk5[1] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+7625,"VX_cache genblk5[1] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+7585,"VX_cache genblk5[1] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+7633,"VX_cache genblk5[1] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+7641,"VX_cache genblk5[1] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+7649,"VX_cache genblk5[1] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+7657,"VX_cache genblk5[1] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+7665,"VX_cache genblk5[1] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+7673,"VX_cache genblk5[1] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+7681,"VX_cache genblk5[1] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+7689,"VX_cache genblk5[1] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[1] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+7465,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+7473,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+7481,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+7489,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+7497,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+7585,"VX_cache genblk5[1] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+7545,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+7601,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+7609,"VX_cache genblk5[1] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+7553,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+6697,"VX_cache genblk5[1] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+28041,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+28073,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+28105,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+28137,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+28169,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+28201,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+28233,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+28265,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+28297,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+28329,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+28361,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+28393,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+28425,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+28457,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+28489,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+28521,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+28553+i*1,"VX_cache genblk5[1] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+28681,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+28689,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+28697,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+28705,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+28713,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+28721,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+28729,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+28737,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+28745,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+28753,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+28761,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+28769,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+28777,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+28785,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+28793,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+28801,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+28809,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+28817,"VX_cache genblk5[1] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+7697,"VX_cache genblk5[1] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+28825,"VX_cache genblk5[1] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+28833,"VX_cache genblk5[1] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+7705,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+7705,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+28841,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[1] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[1] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[1] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[1] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+7753,"VX_cache genblk5[1] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+28889,"VX_cache genblk5[1] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+28889,"VX_cache genblk5[1] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[1] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58753,"VX_cache genblk5[1] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[1] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[1] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[1] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+6881,"VX_cache genblk5[1] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+6889,"VX_cache genblk5[1] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19713,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+25729,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+25737,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+25673,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+25681,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+25697,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+25705,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+6849,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+25841,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+25849,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+25585,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+25593,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+7345,"VX_cache genblk5[1] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+6833,"VX_cache genblk5[1] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+6321,"VX_cache genblk5[1] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+6297,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+6305,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+25609,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+25617,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+25625,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+25601,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+25633,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6313,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+25649,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+25657,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+25665,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+28969+i*3,"VX_cache genblk5[1] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+29353,"VX_cache genblk5[1] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+29457,"VX_cache genblk5[1] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+29465,"VX_cache genblk5[1] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+29473,"VX_cache genblk5[1] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+29481,"VX_cache genblk5[1] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+29489,"VX_cache genblk5[1] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+29497,"VX_cache genblk5[1] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+29505,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+29489,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+7833,"VX_cache genblk5[1] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+7841,"VX_cache genblk5[1] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+7849,"VX_cache genblk5[1] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+6305,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+29473,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+7857,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+7865,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+7873,"VX_cache genblk5[1] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+7881,"VX_cache genblk5[1] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+7889,"VX_cache genblk5[1] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+7897,"VX_cache genblk5[1] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[1] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[1] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank cwb_queue reset", false,-1); + vcdp->declBit(c+6897,"VX_cache genblk5[1] bank cwb_queue push", false,-1); + vcdp->declBit(c+1897,"VX_cache genblk5[1] bank cwb_queue pop", false,-1); + vcdp->declArray(c+7905,"VX_cache genblk5[1] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+7929,"VX_cache genblk5[1] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+25889,"VX_cache genblk5[1] bank cwb_queue empty", false,-1); + vcdp->declBit(c+25897,"VX_cache genblk5[1] bank cwb_queue full", false,-1); + vcdp->declBus(c+29513,"VX_cache genblk5[1] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+29513,"VX_cache genblk5[1] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+681,"VX_cache genblk5[1] bank cwb_queue reading", false,-1); + vcdp->declBit(c+7953,"VX_cache genblk5[1] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+29521+i*3,"VX_cache genblk5[1] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+29713,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+29737,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+29761,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+29769,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+29777,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+25889,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+25897,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+29785,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[1] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[1] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[1] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[1] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[1] bank dwb_queue reset", false,-1); + vcdp->declBit(c+6921,"VX_cache genblk5[1] bank dwb_queue push", false,-1); + vcdp->declBit(c+1905,"VX_cache genblk5[1] bank dwb_queue pop", false,-1); + vcdp->declArray(c+7961,"VX_cache genblk5[1] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+8017,"VX_cache genblk5[1] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+25905,"VX_cache genblk5[1] bank dwb_queue empty", false,-1); + vcdp->declBit(c+25913,"VX_cache genblk5[1] bank dwb_queue full", false,-1); + vcdp->declBus(c+29793,"VX_cache genblk5[1] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+29793,"VX_cache genblk5[1] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+689,"VX_cache genblk5[1] bank dwb_queue reading", false,-1); + vcdp->declBit(c+8073,"VX_cache genblk5[1] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+29801+i*7,"VX_cache genblk5[1] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+30025,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+30081,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+30137,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+30145,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+30153,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+25905,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+25913,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+30161,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58641,"VX_cache genblk5[2] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58825,"VX_cache genblk5[2] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[2] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[2] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[2] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[2] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank reset", false,-1); + vcdp->declBus(c+97,"VX_cache genblk5[2] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[2] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[2] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[2] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[2] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[2] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19769,"VX_cache genblk5[2] bank core_req_ready", false,-1); + vcdp->declBit(c+19737,"VX_cache genblk5[2] bank core_rsp_valid", false,-1); + vcdp->declBus(c+3009,"VX_cache genblk5[2] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3017,"VX_cache genblk5[2] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3025,"VX_cache genblk5[2] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+105,"VX_cache genblk5[2] bank core_rsp_ready", false,-1); + vcdp->declBit(c+3041,"VX_cache genblk5[2] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19753,"VX_cache genblk5[2] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[2] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58529,"VX_cache genblk5[2] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[2] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[2] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19745,"VX_cache genblk5[2] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3049,"VX_cache genblk5[2] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+3057,"VX_cache genblk5[2] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3065,"VX_cache genblk5[2] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3073,"VX_cache genblk5[2] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+113,"VX_cache genblk5[2] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58537,"VX_cache genblk5[2] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[2] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[2] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[2] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19761,"VX_cache genblk5[2] bank snp_req_ready", false,-1); + vcdp->declBit(c+3105,"VX_cache genblk5[2] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+3113,"VX_cache genblk5[2] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+121,"VX_cache genblk5[2] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+8081,"VX_cache genblk5[2] bank snrq_pop", false,-1); + vcdp->declBit(c+30169,"VX_cache genblk5[2] bank snrq_empty", false,-1); + vcdp->declBit(c+30177,"VX_cache genblk5[2] bank snrq_full", false,-1); + vcdp->declBus(c+8089,"VX_cache genblk5[2] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+8097,"VX_cache genblk5[2] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+8105,"VX_cache genblk5[2] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+8113,"VX_cache genblk5[2] bank dfpq_pop", false,-1); + vcdp->declBit(c+30185,"VX_cache genblk5[2] bank dfpq_empty", false,-1); + vcdp->declBit(c+30193,"VX_cache genblk5[2] bank dfpq_full", false,-1); + vcdp->declBus(c+8121,"VX_cache genblk5[2] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+8129,"VX_cache genblk5[2] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+8161,"VX_cache genblk5[2] bank reqq_pop", false,-1); + vcdp->declBit(c+1921,"VX_cache genblk5[2] bank reqq_push", false,-1); + vcdp->declBit(c+8169,"VX_cache genblk5[2] bank reqq_empty", false,-1); + vcdp->declBit(c+30201,"VX_cache genblk5[2] bank reqq_full", false,-1); + vcdp->declBit(c+8177,"VX_cache genblk5[2] bank reqq_req_st0", false,-1); + vcdp->declBus(c+8185,"VX_cache genblk5[2] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+8193,"VX_cache genblk5[2] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+8201,"VX_cache genblk5[2] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+8209,"VX_cache genblk5[2] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+8217,"VX_cache genblk5[2] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8225,"VX_cache genblk5[2] bank mrvq_pop", false,-1); + vcdp->declBit(c+30225,"VX_cache genblk5[2] bank mrvq_full", false,-1); + vcdp->declBit(c+30233,"VX_cache genblk5[2] bank mrvq_stop", false,-1); + vcdp->declBit(c+8233,"VX_cache genblk5[2] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+30241,"VX_cache genblk5[2] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+30249,"VX_cache genblk5[2] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+30257,"VX_cache genblk5[2] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+30265,"VX_cache genblk5[2] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+30273,"VX_cache genblk5[2] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8241,"VX_cache genblk5[2] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+30289,"VX_cache genblk5[2] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+30297,"VX_cache genblk5[2] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+30305,"VX_cache genblk5[2] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+8249,"VX_cache genblk5[2] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+8257,"VX_cache genblk5[2] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+8265,"VX_cache genblk5[2] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+30313,"VX_cache genblk5[2] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+30321,"VX_cache genblk5[2] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+30337,"VX_cache genblk5[2] bank miss_add_rw", false,-1); + vcdp->declBus(c+30345,"VX_cache genblk5[2] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19753,"VX_cache genblk5[2] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+30353,"VX_cache genblk5[2] bank is_fill_st2", false,-1); + vcdp->declBit(c+8273,"VX_cache genblk5[2] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+8281,"VX_cache genblk5[2] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+8289,"VX_cache genblk5[2] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+8297,"VX_cache genblk5[2] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+8305,"VX_cache genblk5[2] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[2] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+8321,"VX_cache genblk5[2] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8329+i*1,"VX_cache genblk5[2] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8337+i*1,"VX_cache genblk5[2] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[2] bank j", false,-1, 31,0); + vcdp->declBit(c+8233,"VX_cache genblk5[2] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+8345,"VX_cache genblk5[2] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+8353,"VX_cache genblk5[2] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+8361,"VX_cache genblk5[2] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+8345,"VX_cache genblk5[2] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[2] bank qual_valid_st0", false,-1); + vcdp->declBus(c+8377,"VX_cache genblk5[2] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+8385,"VX_cache genblk5[2] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+8233,"VX_cache genblk5[2] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+8393,"VX_cache genblk5[2] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+8401,"VX_cache genblk5[2] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+8433,"VX_cache genblk5[2] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+8449,"VX_cache genblk5[2] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+8457,"VX_cache genblk5[2] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+8465,"VX_cache genblk5[2] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8473+i*1,"VX_cache genblk5[2] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+8481+i*1,"VX_cache genblk5[2] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+8489+i*1,"VX_cache genblk5[2] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+8497+i*1,"VX_cache genblk5[2] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+8505+i*2,"VX_cache genblk5[2] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+8521+i*4,"VX_cache genblk5[2] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8553+i*1,"VX_cache genblk5[2] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8561+i*1,"VX_cache genblk5[2] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+8569+i*1,"VX_cache genblk5[2] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+8577,"VX_cache genblk5[2] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+8585,"VX_cache genblk5[2] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+8617,"VX_cache genblk5[2] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+8625,"VX_cache genblk5[2] bank miss_st1e", false,-1); + vcdp->declBit(c+8633,"VX_cache genblk5[2] bank dirty_st1e", false,-1); + vcdp->declBus(c+8641,"VX_cache genblk5[2] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+8649,"VX_cache genblk5[2] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+8665,"VX_cache genblk5[2] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+8673,"VX_cache genblk5[2] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+8681,"VX_cache genblk5[2] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+8689,"VX_cache genblk5[2] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+8697,"VX_cache genblk5[2] bank is_snp_st1e", false,-1); + vcdp->declBit(c+8705,"VX_cache genblk5[2] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+8713,"VX_cache genblk5[2] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+8721,"VX_cache genblk5[2] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+8729,"VX_cache genblk5[2] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+8737,"VX_cache genblk5[2] bank valid_st1e", false,-1); + vcdp->declBit(c+8745,"VX_cache genblk5[2] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+8753,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+8761,"VX_cache genblk5[2] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+8769,"VX_cache genblk5[2] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+8745,"VX_cache genblk5[2] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+30361,"VX_cache genblk5[2] bank valid_st2", false,-1); + vcdp->declBus(c+30369,"VX_cache genblk5[2] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+30377,"VX_cache genblk5[2] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+30385,"VX_cache genblk5[2] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+30393,"VX_cache genblk5[2] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+30425,"VX_cache genblk5[2] bank miss_st2", false,-1); + vcdp->declBit(c+30433,"VX_cache genblk5[2] bank dirty_st2", false,-1); + vcdp->declBus(c+30441,"VX_cache genblk5[2] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+30449,"VX_cache genblk5[2] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+30465,"VX_cache genblk5[2] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+30473,"VX_cache genblk5[2] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+30481,"VX_cache genblk5[2] bank is_snp_st2", false,-1); + vcdp->declBit(c+30489,"VX_cache genblk5[2] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+30497,"VX_cache genblk5[2] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+30505,"VX_cache genblk5[2] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+8777,"VX_cache genblk5[2] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+30513,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+30521,"VX_cache genblk5[2] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+8785,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+8793,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+30497,"VX_cache genblk5[2] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+8801,"VX_cache genblk5[2] bank miss_add_unqual", false,-1); + vcdp->declBit(c+8809,"VX_cache genblk5[2] bank miss_add", false,-1); + vcdp->declBus(c+19753,"VX_cache genblk5[2] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+30369,"VX_cache genblk5[2] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+30377,"VX_cache genblk5[2] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+30481,"VX_cache genblk5[2] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+30489,"VX_cache genblk5[2] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+8817,"VX_cache genblk5[2] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+8825,"VX_cache genblk5[2] bank cwbq_push", false,-1); + vcdp->declBit(c+1929,"VX_cache genblk5[2] bank cwbq_pop", false,-1); + vcdp->declBit(c+30529,"VX_cache genblk5[2] bank cwbq_empty", false,-1); + vcdp->declBit(c+30537,"VX_cache genblk5[2] bank cwbq_full", false,-1); + vcdp->declBit(c+8833,"VX_cache genblk5[2] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+30385,"VX_cache genblk5[2] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+30313,"VX_cache genblk5[2] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+30321,"VX_cache genblk5[2] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+8801,"VX_cache genblk5[2] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+8841,"VX_cache genblk5[2] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+8849,"VX_cache genblk5[2] bank dwbq_push", false,-1); + vcdp->declBit(c+1937,"VX_cache genblk5[2] bank dwbq_pop", false,-1); + vcdp->declBit(c+30545,"VX_cache genblk5[2] bank dwbq_empty", false,-1); + vcdp->declBit(c+30553,"VX_cache genblk5[2] bank dwbq_full", false,-1); + vcdp->declBit(c+8857,"VX_cache genblk5[2] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+8865,"VX_cache genblk5[2] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+8873,"VX_cache genblk5[2] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+8881,"VX_cache genblk5[2] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+8889,"VX_cache genblk5[2] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+30561,"VX_cache genblk5[2] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+30569,"VX_cache genblk5[2] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+697,"VX_cache genblk5[2] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+705,"VX_cache genblk5[2] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+30577,"VX_cache genblk5[2] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[2] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58537,"VX_cache genblk5[2] bank snp_req_queue push", false,-1); + vcdp->declBit(c+8081,"VX_cache genblk5[2] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+713,"VX_cache genblk5[2] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+8897,"VX_cache genblk5[2] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+30169,"VX_cache genblk5[2] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+30177,"VX_cache genblk5[2] bank snp_req_queue full", false,-1); + vcdp->declBus(c+30585,"VX_cache genblk5[2] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+30585,"VX_cache genblk5[2] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+8913,"VX_cache genblk5[2] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+729,"VX_cache genblk5[2] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+30593+i*2,"VX_cache genblk5[2] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+30849,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+30865,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+30881,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+30889,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+30897,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+30169,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+30177,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+30905,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[2] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58529,"VX_cache genblk5[2] bank dfp_queue push", false,-1); + vcdp->declBit(c+8113,"VX_cache genblk5[2] bank dfp_queue pop", false,-1); + vcdp->declArray(c+737,"VX_cache genblk5[2] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+8921,"VX_cache genblk5[2] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+30185,"VX_cache genblk5[2] bank dfp_queue empty", false,-1); + vcdp->declBit(c+30193,"VX_cache genblk5[2] bank dfp_queue full", false,-1); + vcdp->declBus(c+30913,"VX_cache genblk5[2] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+30913,"VX_cache genblk5[2] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+8961,"VX_cache genblk5[2] bank dfp_queue reading", false,-1); + vcdp->declBit(c+777,"VX_cache genblk5[2] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+30921+i*5,"VX_cache genblk5[2] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+31561,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+31601,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+31641,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+31649,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+31657,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+30185,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+30193,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+31665,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1921,"VX_cache genblk5[2] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+97,"VX_cache genblk5[2] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[2] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[2] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[2] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[2] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[2] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+8161,"VX_cache genblk5[2] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+8193,"VX_cache genblk5[2] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+8201,"VX_cache genblk5[2] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+8209,"VX_cache genblk5[2] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+8217,"VX_cache genblk5[2] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8169,"VX_cache genblk5[2] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+30201,"VX_cache genblk5[2] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+8969,"VX_cache genblk5[2] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+8977,"VX_cache genblk5[2] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+8985,"VX_cache genblk5[2] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+8993,"VX_cache genblk5[2] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+9025,"VX_cache genblk5[2] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+9057,"VX_cache genblk5[2] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+31681,"VX_cache genblk5[2] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+31689,"VX_cache genblk5[2] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+31697,"VX_cache genblk5[2] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+31729,"VX_cache genblk5[2] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+31681,"VX_cache genblk5[2] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+31689,"VX_cache genblk5[2] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+31697,"VX_cache genblk5[2] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+31729,"VX_cache genblk5[2] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+31761,"VX_cache genblk5[2] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+31769,"VX_cache genblk5[2] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+9073,"VX_cache genblk5[2] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1945,"VX_cache genblk5[2] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+9081,"VX_cache genblk5[2] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+9089,"VX_cache genblk5[2] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[2] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1945,"VX_cache genblk5[2] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+9081,"VX_cache genblk5[2] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+785,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+9097,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+31761,"VX_cache genblk5[2] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+30201,"VX_cache genblk5[2] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+31777,"VX_cache genblk5[2] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+31777,"VX_cache genblk5[2] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+9177,"VX_cache genblk5[2] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+865,"VX_cache genblk5[2] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+31785+i*10,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+32425,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+32505,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+32585,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+32593,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+32601,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+31761,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+30201,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+32609,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+9185,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+9185,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+9193,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[2] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[2] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[2] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[2] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+9201,"VX_cache genblk5[2] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+32617,"VX_cache genblk5[2] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+32617,"VX_cache genblk5[2] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[2] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank tag_data_access reset", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access stall", false,-1); + vcdp->declBit(c+8697,"VX_cache genblk5[2] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+8705,"VX_cache genblk5[2] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+8265,"VX_cache genblk5[2] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+8761,"VX_cache genblk5[2] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+8737,"VX_cache genblk5[2] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+9273,"VX_cache genblk5[2] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+9281,"VX_cache genblk5[2] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+9289,"VX_cache genblk5[2] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+8673,"VX_cache genblk5[2] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+8681,"VX_cache genblk5[2] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+9321,"VX_cache genblk5[2] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+8577,"VX_cache genblk5[2] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+8585,"VX_cache genblk5[2] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+8617,"VX_cache genblk5[2] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+8625,"VX_cache genblk5[2] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+8633,"VX_cache genblk5[2] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+8641,"VX_cache genblk5[2] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+8689,"VX_cache genblk5[2] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+8713,"VX_cache genblk5[2] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+8721,"VX_cache genblk5[2] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+9329+i*1,"VX_cache genblk5[2] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+9337+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+9345+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+9353+i*1,"VX_cache genblk5[2] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+9361+i*4,"VX_cache genblk5[2] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+9393,"VX_cache genblk5[2] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+9401,"VX_cache genblk5[2] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+9409,"VX_cache genblk5[2] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+9417,"VX_cache genblk5[2] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+9425,"VX_cache genblk5[2] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+9457,"VX_cache genblk5[2] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+9465,"VX_cache genblk5[2] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+8641,"VX_cache genblk5[2] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+8617,"VX_cache genblk5[2] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+8585,"VX_cache genblk5[2] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+9473,"VX_cache genblk5[2] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+9481,"VX_cache genblk5[2] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+8625,"VX_cache genblk5[2] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+9513,"VX_cache genblk5[2] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+9521,"VX_cache genblk5[2] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+9529,"VX_cache genblk5[2] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+9537,"VX_cache genblk5[2] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+9545,"VX_cache genblk5[2] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+9481,"VX_cache genblk5[2] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+9553,"VX_cache genblk5[2] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+9513,"VX_cache genblk5[2] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+9561,"VX_cache genblk5[2] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+9569,"VX_cache genblk5[2] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+9577,"VX_cache genblk5[2] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+9585,"VX_cache genblk5[2] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+9593,"VX_cache genblk5[2] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+9601,"VX_cache genblk5[2] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+9609,"VX_cache genblk5[2] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+9617,"VX_cache genblk5[2] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[2] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+9393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+9401,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+9409,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+9417,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+9425,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+9513,"VX_cache genblk5[2] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+9473,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+9529,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+9537,"VX_cache genblk5[2] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+9481,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+8625,"VX_cache genblk5[2] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+32681,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+32713,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+32745,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+32777,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+32809,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+32841,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+32873,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+32905,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+32937,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+32969,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+33001,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+33033,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+33065,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+33097,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+33129,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+33161,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+33193+i*1,"VX_cache genblk5[2] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+33321,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+33329,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+33337,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+33345,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+33353,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+33361,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+33369,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+33377,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+33385,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+33393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+33401,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+33409,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+33417,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+33425,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+33433,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+33441,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+33449,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+33457,"VX_cache genblk5[2] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+9625,"VX_cache genblk5[2] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+33465,"VX_cache genblk5[2] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+33473,"VX_cache genblk5[2] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+9633,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+9633,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+33481,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[2] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[2] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[2] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[2] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+9681,"VX_cache genblk5[2] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+33529,"VX_cache genblk5[2] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+33529,"VX_cache genblk5[2] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[2] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58825,"VX_cache genblk5[2] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[2] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[2] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[2] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+8809,"VX_cache genblk5[2] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+8817,"VX_cache genblk5[2] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19753,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+30369,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+30377,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+30313,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+30321,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+30337,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+30345,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+8777,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+30481,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+30489,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+30225,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+30233,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+9273,"VX_cache genblk5[2] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+8761,"VX_cache genblk5[2] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+8249,"VX_cache genblk5[2] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+8225,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+8233,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+30249,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+30257,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+30265,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+30241,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+30273,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8241,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+30289,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+30297,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+30305,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+33609+i*3,"VX_cache genblk5[2] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+33993,"VX_cache genblk5[2] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+34097,"VX_cache genblk5[2] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+34105,"VX_cache genblk5[2] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+34113,"VX_cache genblk5[2] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+34121,"VX_cache genblk5[2] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+34129,"VX_cache genblk5[2] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+34137,"VX_cache genblk5[2] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+34145,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+34129,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+9761,"VX_cache genblk5[2] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+9769,"VX_cache genblk5[2] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+9777,"VX_cache genblk5[2] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+8233,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+34113,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+9785,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+9793,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+9801,"VX_cache genblk5[2] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+9809,"VX_cache genblk5[2] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+9817,"VX_cache genblk5[2] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+9825,"VX_cache genblk5[2] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[2] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[2] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank cwb_queue reset", false,-1); + vcdp->declBit(c+8825,"VX_cache genblk5[2] bank cwb_queue push", false,-1); + vcdp->declBit(c+1929,"VX_cache genblk5[2] bank cwb_queue pop", false,-1); + vcdp->declArray(c+9833,"VX_cache genblk5[2] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+9857,"VX_cache genblk5[2] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+30529,"VX_cache genblk5[2] bank cwb_queue empty", false,-1); + vcdp->declBit(c+30537,"VX_cache genblk5[2] bank cwb_queue full", false,-1); + vcdp->declBus(c+34153,"VX_cache genblk5[2] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+34153,"VX_cache genblk5[2] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+873,"VX_cache genblk5[2] bank cwb_queue reading", false,-1); + vcdp->declBit(c+9881,"VX_cache genblk5[2] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+34161+i*3,"VX_cache genblk5[2] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+34353,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+34377,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+34401,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+34409,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+34417,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+30529,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+30537,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+34425,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[2] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[2] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[2] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[2] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[2] bank dwb_queue reset", false,-1); + vcdp->declBit(c+8849,"VX_cache genblk5[2] bank dwb_queue push", false,-1); + vcdp->declBit(c+1937,"VX_cache genblk5[2] bank dwb_queue pop", false,-1); + vcdp->declArray(c+9889,"VX_cache genblk5[2] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+9945,"VX_cache genblk5[2] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+30545,"VX_cache genblk5[2] bank dwb_queue empty", false,-1); + vcdp->declBit(c+30553,"VX_cache genblk5[2] bank dwb_queue full", false,-1); + vcdp->declBus(c+34433,"VX_cache genblk5[2] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+34433,"VX_cache genblk5[2] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+881,"VX_cache genblk5[2] bank dwb_queue reading", false,-1); + vcdp->declBit(c+10001,"VX_cache genblk5[2] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+34441+i*7,"VX_cache genblk5[2] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+34665,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+34721,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+34777,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+34785,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+34793,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+30545,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+30553,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+34801,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58641,"VX_cache genblk5[3] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58833,"VX_cache genblk5[3] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[3] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[3] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[3] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[3] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank reset", false,-1); + vcdp->declBus(c+129,"VX_cache genblk5[3] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[3] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[3] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[3] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[3] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[3] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19809,"VX_cache genblk5[3] bank core_req_ready", false,-1); + vcdp->declBit(c+19777,"VX_cache genblk5[3] bank core_rsp_valid", false,-1); + vcdp->declBus(c+3121,"VX_cache genblk5[3] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3129,"VX_cache genblk5[3] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3137,"VX_cache genblk5[3] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+137,"VX_cache genblk5[3] bank core_rsp_ready", false,-1); + vcdp->declBit(c+3153,"VX_cache genblk5[3] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19793,"VX_cache genblk5[3] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[3] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58545,"VX_cache genblk5[3] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[3] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[3] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19785,"VX_cache genblk5[3] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3161,"VX_cache genblk5[3] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+3169,"VX_cache genblk5[3] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3177,"VX_cache genblk5[3] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3185,"VX_cache genblk5[3] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+145,"VX_cache genblk5[3] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58553,"VX_cache genblk5[3] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[3] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[3] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[3] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19801,"VX_cache genblk5[3] bank snp_req_ready", false,-1); + vcdp->declBit(c+3217,"VX_cache genblk5[3] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+3225,"VX_cache genblk5[3] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+153,"VX_cache genblk5[3] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+10009,"VX_cache genblk5[3] bank snrq_pop", false,-1); + vcdp->declBit(c+34809,"VX_cache genblk5[3] bank snrq_empty", false,-1); + vcdp->declBit(c+34817,"VX_cache genblk5[3] bank snrq_full", false,-1); + vcdp->declBus(c+10017,"VX_cache genblk5[3] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+10025,"VX_cache genblk5[3] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+10033,"VX_cache genblk5[3] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+10041,"VX_cache genblk5[3] bank dfpq_pop", false,-1); + vcdp->declBit(c+34825,"VX_cache genblk5[3] bank dfpq_empty", false,-1); + vcdp->declBit(c+34833,"VX_cache genblk5[3] bank dfpq_full", false,-1); + vcdp->declBus(c+10049,"VX_cache genblk5[3] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+10057,"VX_cache genblk5[3] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+10089,"VX_cache genblk5[3] bank reqq_pop", false,-1); + vcdp->declBit(c+1953,"VX_cache genblk5[3] bank reqq_push", false,-1); + vcdp->declBit(c+10097,"VX_cache genblk5[3] bank reqq_empty", false,-1); + vcdp->declBit(c+34841,"VX_cache genblk5[3] bank reqq_full", false,-1); + vcdp->declBit(c+10105,"VX_cache genblk5[3] bank reqq_req_st0", false,-1); + vcdp->declBus(c+10113,"VX_cache genblk5[3] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+10121,"VX_cache genblk5[3] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[3] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+10137,"VX_cache genblk5[3] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+10145,"VX_cache genblk5[3] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+10153,"VX_cache genblk5[3] bank mrvq_pop", false,-1); + vcdp->declBit(c+34865,"VX_cache genblk5[3] bank mrvq_full", false,-1); + vcdp->declBit(c+34873,"VX_cache genblk5[3] bank mrvq_stop", false,-1); + vcdp->declBit(c+10161,"VX_cache genblk5[3] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+34881,"VX_cache genblk5[3] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+34889,"VX_cache genblk5[3] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+34897,"VX_cache genblk5[3] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+34905,"VX_cache genblk5[3] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+34913,"VX_cache genblk5[3] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+10169,"VX_cache genblk5[3] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+34929,"VX_cache genblk5[3] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+34937,"VX_cache genblk5[3] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+34945,"VX_cache genblk5[3] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+10177,"VX_cache genblk5[3] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+10185,"VX_cache genblk5[3] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+10193,"VX_cache genblk5[3] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+34953,"VX_cache genblk5[3] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+34961,"VX_cache genblk5[3] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+34977,"VX_cache genblk5[3] bank miss_add_rw", false,-1); + vcdp->declBus(c+34985,"VX_cache genblk5[3] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19793,"VX_cache genblk5[3] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+34993,"VX_cache genblk5[3] bank is_fill_st2", false,-1); + vcdp->declBit(c+10201,"VX_cache genblk5[3] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+10209,"VX_cache genblk5[3] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+10217,"VX_cache genblk5[3] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+10225,"VX_cache genblk5[3] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+10233,"VX_cache genblk5[3] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+10241,"VX_cache genblk5[3] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+10249,"VX_cache genblk5[3] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+10257+i*1,"VX_cache genblk5[3] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+10265+i*1,"VX_cache genblk5[3] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[3] bank j", false,-1, 31,0); + vcdp->declBit(c+10161,"VX_cache genblk5[3] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+10273,"VX_cache genblk5[3] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+10281,"VX_cache genblk5[3] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+10289,"VX_cache genblk5[3] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+10273,"VX_cache genblk5[3] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+10297,"VX_cache genblk5[3] bank qual_valid_st0", false,-1); + vcdp->declBus(c+10305,"VX_cache genblk5[3] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+10313,"VX_cache genblk5[3] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+10161,"VX_cache genblk5[3] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+10321,"VX_cache genblk5[3] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+10329,"VX_cache genblk5[3] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+10361,"VX_cache genblk5[3] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+10377,"VX_cache genblk5[3] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+10385,"VX_cache genblk5[3] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+10393,"VX_cache genblk5[3] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+10401+i*1,"VX_cache genblk5[3] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+10409+i*1,"VX_cache genblk5[3] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+10417+i*1,"VX_cache genblk5[3] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+10425+i*1,"VX_cache genblk5[3] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+10433+i*2,"VX_cache genblk5[3] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+10449+i*4,"VX_cache genblk5[3] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+10481+i*1,"VX_cache genblk5[3] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+10489+i*1,"VX_cache genblk5[3] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+10497+i*1,"VX_cache genblk5[3] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+10505,"VX_cache genblk5[3] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+10513,"VX_cache genblk5[3] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+10545,"VX_cache genblk5[3] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+10553,"VX_cache genblk5[3] bank miss_st1e", false,-1); + vcdp->declBit(c+10561,"VX_cache genblk5[3] bank dirty_st1e", false,-1); + vcdp->declBus(c+10569,"VX_cache genblk5[3] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+10577,"VX_cache genblk5[3] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+10593,"VX_cache genblk5[3] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+10601,"VX_cache genblk5[3] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+10609,"VX_cache genblk5[3] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+10617,"VX_cache genblk5[3] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[3] bank is_snp_st1e", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[3] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+10641,"VX_cache genblk5[3] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+10649,"VX_cache genblk5[3] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+10657,"VX_cache genblk5[3] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+10665,"VX_cache genblk5[3] bank valid_st1e", false,-1); + vcdp->declBit(c+10673,"VX_cache genblk5[3] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+10681,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+10689,"VX_cache genblk5[3] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+10697,"VX_cache genblk5[3] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+10673,"VX_cache genblk5[3] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+35001,"VX_cache genblk5[3] bank valid_st2", false,-1); + vcdp->declBus(c+35009,"VX_cache genblk5[3] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+35017,"VX_cache genblk5[3] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+35025,"VX_cache genblk5[3] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+35033,"VX_cache genblk5[3] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+35065,"VX_cache genblk5[3] bank miss_st2", false,-1); + vcdp->declBit(c+35073,"VX_cache genblk5[3] bank dirty_st2", false,-1); + vcdp->declBus(c+35081,"VX_cache genblk5[3] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+35089,"VX_cache genblk5[3] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+35105,"VX_cache genblk5[3] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+35113,"VX_cache genblk5[3] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+35121,"VX_cache genblk5[3] bank is_snp_st2", false,-1); + vcdp->declBit(c+35129,"VX_cache genblk5[3] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+35137,"VX_cache genblk5[3] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+35145,"VX_cache genblk5[3] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+10705,"VX_cache genblk5[3] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+35153,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+35161,"VX_cache genblk5[3] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+10713,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+10721,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+35137,"VX_cache genblk5[3] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+10729,"VX_cache genblk5[3] bank miss_add_unqual", false,-1); + vcdp->declBit(c+10737,"VX_cache genblk5[3] bank miss_add", false,-1); + vcdp->declBus(c+19793,"VX_cache genblk5[3] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+35009,"VX_cache genblk5[3] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+35017,"VX_cache genblk5[3] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+35121,"VX_cache genblk5[3] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+35129,"VX_cache genblk5[3] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+10745,"VX_cache genblk5[3] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+10753,"VX_cache genblk5[3] bank cwbq_push", false,-1); + vcdp->declBit(c+1961,"VX_cache genblk5[3] bank cwbq_pop", false,-1); + vcdp->declBit(c+35169,"VX_cache genblk5[3] bank cwbq_empty", false,-1); + vcdp->declBit(c+35177,"VX_cache genblk5[3] bank cwbq_full", false,-1); + vcdp->declBit(c+10761,"VX_cache genblk5[3] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+35025,"VX_cache genblk5[3] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+34953,"VX_cache genblk5[3] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+34961,"VX_cache genblk5[3] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+10729,"VX_cache genblk5[3] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+10769,"VX_cache genblk5[3] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+10777,"VX_cache genblk5[3] bank dwbq_push", false,-1); + vcdp->declBit(c+1969,"VX_cache genblk5[3] bank dwbq_pop", false,-1); + vcdp->declBit(c+35185,"VX_cache genblk5[3] bank dwbq_empty", false,-1); + vcdp->declBit(c+35193,"VX_cache genblk5[3] bank dwbq_full", false,-1); + vcdp->declBit(c+10785,"VX_cache genblk5[3] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+10793,"VX_cache genblk5[3] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+10801,"VX_cache genblk5[3] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+10809,"VX_cache genblk5[3] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+10817,"VX_cache genblk5[3] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+35201,"VX_cache genblk5[3] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+35209,"VX_cache genblk5[3] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+889,"VX_cache genblk5[3] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+897,"VX_cache genblk5[3] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+35217,"VX_cache genblk5[3] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[3] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58553,"VX_cache genblk5[3] bank snp_req_queue push", false,-1); + vcdp->declBit(c+10009,"VX_cache genblk5[3] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+905,"VX_cache genblk5[3] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+10825,"VX_cache genblk5[3] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+34809,"VX_cache genblk5[3] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+34817,"VX_cache genblk5[3] bank snp_req_queue full", false,-1); + vcdp->declBus(c+35225,"VX_cache genblk5[3] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+35225,"VX_cache genblk5[3] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+10841,"VX_cache genblk5[3] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+921,"VX_cache genblk5[3] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+35233+i*2,"VX_cache genblk5[3] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+35489,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+35505,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+35521,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+35529,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+35537,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+34809,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+34817,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+35545,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[3] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58545,"VX_cache genblk5[3] bank dfp_queue push", false,-1); + vcdp->declBit(c+10041,"VX_cache genblk5[3] bank dfp_queue pop", false,-1); + vcdp->declArray(c+929,"VX_cache genblk5[3] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+10849,"VX_cache genblk5[3] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+34825,"VX_cache genblk5[3] bank dfp_queue empty", false,-1); + vcdp->declBit(c+34833,"VX_cache genblk5[3] bank dfp_queue full", false,-1); + vcdp->declBus(c+35553,"VX_cache genblk5[3] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+35553,"VX_cache genblk5[3] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+10889,"VX_cache genblk5[3] bank dfp_queue reading", false,-1); + vcdp->declBit(c+969,"VX_cache genblk5[3] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+35561+i*5,"VX_cache genblk5[3] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+36201,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+36241,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+36281,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+36289,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+36297,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+34825,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+34833,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+36305,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1953,"VX_cache genblk5[3] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+129,"VX_cache genblk5[3] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[3] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[3] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[3] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[3] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[3] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+10089,"VX_cache genblk5[3] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+10121,"VX_cache genblk5[3] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[3] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+10137,"VX_cache genblk5[3] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+10145,"VX_cache genblk5[3] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+10097,"VX_cache genblk5[3] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+34841,"VX_cache genblk5[3] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+10897,"VX_cache genblk5[3] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+10905,"VX_cache genblk5[3] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+10913,"VX_cache genblk5[3] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+10921,"VX_cache genblk5[3] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+10953,"VX_cache genblk5[3] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+10985,"VX_cache genblk5[3] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+36321,"VX_cache genblk5[3] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+36329,"VX_cache genblk5[3] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+36337,"VX_cache genblk5[3] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+36369,"VX_cache genblk5[3] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+36321,"VX_cache genblk5[3] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+36329,"VX_cache genblk5[3] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+36337,"VX_cache genblk5[3] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+36369,"VX_cache genblk5[3] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+36401,"VX_cache genblk5[3] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+36409,"VX_cache genblk5[3] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+11001,"VX_cache genblk5[3] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1977,"VX_cache genblk5[3] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+11009,"VX_cache genblk5[3] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+11017,"VX_cache genblk5[3] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[3] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1977,"VX_cache genblk5[3] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+11009,"VX_cache genblk5[3] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+977,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+11025,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+36401,"VX_cache genblk5[3] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+34841,"VX_cache genblk5[3] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+36417,"VX_cache genblk5[3] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+36417,"VX_cache genblk5[3] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+11105,"VX_cache genblk5[3] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+1057,"VX_cache genblk5[3] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+36425+i*10,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+37065,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+37145,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+37225,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+37233,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+37241,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+36401,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+34841,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+37249,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+11113,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+11113,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+11121,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[3] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[3] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+10241,"VX_cache genblk5[3] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[3] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+11129,"VX_cache genblk5[3] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+37257,"VX_cache genblk5[3] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+37257,"VX_cache genblk5[3] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[3] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank tag_data_access reset", false,-1); + vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access stall", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[3] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[3] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+10193,"VX_cache genblk5[3] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+10689,"VX_cache genblk5[3] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+10665,"VX_cache genblk5[3] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+11201,"VX_cache genblk5[3] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+11209,"VX_cache genblk5[3] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+11217,"VX_cache genblk5[3] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+10601,"VX_cache genblk5[3] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+10609,"VX_cache genblk5[3] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+11249,"VX_cache genblk5[3] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+10505,"VX_cache genblk5[3] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+10513,"VX_cache genblk5[3] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+10545,"VX_cache genblk5[3] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+10553,"VX_cache genblk5[3] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+10561,"VX_cache genblk5[3] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+10569,"VX_cache genblk5[3] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+10617,"VX_cache genblk5[3] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+10641,"VX_cache genblk5[3] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+10649,"VX_cache genblk5[3] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+11257+i*1,"VX_cache genblk5[3] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+11265+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+11273+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+11281+i*1,"VX_cache genblk5[3] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+11289+i*4,"VX_cache genblk5[3] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+11321,"VX_cache genblk5[3] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+11329,"VX_cache genblk5[3] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+11337,"VX_cache genblk5[3] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+11345,"VX_cache genblk5[3] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+11353,"VX_cache genblk5[3] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+11385,"VX_cache genblk5[3] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+11393,"VX_cache genblk5[3] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+10569,"VX_cache genblk5[3] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+10545,"VX_cache genblk5[3] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+10513,"VX_cache genblk5[3] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+11401,"VX_cache genblk5[3] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+11409,"VX_cache genblk5[3] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+10553,"VX_cache genblk5[3] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+11441,"VX_cache genblk5[3] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+11449,"VX_cache genblk5[3] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+11457,"VX_cache genblk5[3] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+11465,"VX_cache genblk5[3] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+11473,"VX_cache genblk5[3] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+11409,"VX_cache genblk5[3] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+11481,"VX_cache genblk5[3] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+11441,"VX_cache genblk5[3] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+11489,"VX_cache genblk5[3] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+11497,"VX_cache genblk5[3] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+11505,"VX_cache genblk5[3] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+11513,"VX_cache genblk5[3] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+11521,"VX_cache genblk5[3] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+11529,"VX_cache genblk5[3] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+11537,"VX_cache genblk5[3] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+11545,"VX_cache genblk5[3] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[3] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+11321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+11329,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+11337,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+11345,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+11353,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+11441,"VX_cache genblk5[3] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+11401,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+11457,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+11465,"VX_cache genblk5[3] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+11409,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+10553,"VX_cache genblk5[3] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+37321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+37353,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+37385,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+37417,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+37449,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+37481,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+37513,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+37545,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+37577,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+37609,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+37641,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+37673,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+37705,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+37737,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+37769,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+37801,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+37833+i*1,"VX_cache genblk5[3] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+37961,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+37969,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+37977,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+37985,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+37993,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+38001,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+38009,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+38017,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+38025,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+38033,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+38041,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+38049,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+38057,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+38065,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+38073,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+38081,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+38089,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+38097,"VX_cache genblk5[3] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+11553,"VX_cache genblk5[3] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+38105,"VX_cache genblk5[3] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+38113,"VX_cache genblk5[3] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+11561,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+11561,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+38121,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[3] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[3] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+10241,"VX_cache genblk5[3] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[3] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+11609,"VX_cache genblk5[3] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+38169,"VX_cache genblk5[3] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+38169,"VX_cache genblk5[3] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[3] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58833,"VX_cache genblk5[3] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[3] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[3] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[3] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+10737,"VX_cache genblk5[3] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+10745,"VX_cache genblk5[3] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19793,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+35009,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+35017,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+34953,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+34961,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+34977,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+34985,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+10705,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+35121,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+35129,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+34865,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+34873,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+11201,"VX_cache genblk5[3] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+10689,"VX_cache genblk5[3] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+10177,"VX_cache genblk5[3] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+10153,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+10161,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+34889,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+34897,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+34905,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+34881,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+34913,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+10169,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+34929,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+34937,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+34945,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+38249+i*3,"VX_cache genblk5[3] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+38633,"VX_cache genblk5[3] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+38737,"VX_cache genblk5[3] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+38745,"VX_cache genblk5[3] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+38753,"VX_cache genblk5[3] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+38761,"VX_cache genblk5[3] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+38769,"VX_cache genblk5[3] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+38777,"VX_cache genblk5[3] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+38785,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+38769,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+11689,"VX_cache genblk5[3] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+11697,"VX_cache genblk5[3] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+11705,"VX_cache genblk5[3] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+10161,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+38753,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+11713,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+11721,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+11729,"VX_cache genblk5[3] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+11737,"VX_cache genblk5[3] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+11745,"VX_cache genblk5[3] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+11753,"VX_cache genblk5[3] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[3] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[3] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank cwb_queue reset", false,-1); + vcdp->declBit(c+10753,"VX_cache genblk5[3] bank cwb_queue push", false,-1); + vcdp->declBit(c+1961,"VX_cache genblk5[3] bank cwb_queue pop", false,-1); + vcdp->declArray(c+11761,"VX_cache genblk5[3] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+11785,"VX_cache genblk5[3] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+35169,"VX_cache genblk5[3] bank cwb_queue empty", false,-1); + vcdp->declBit(c+35177,"VX_cache genblk5[3] bank cwb_queue full", false,-1); + vcdp->declBus(c+38793,"VX_cache genblk5[3] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+38793,"VX_cache genblk5[3] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+1065,"VX_cache genblk5[3] bank cwb_queue reading", false,-1); + vcdp->declBit(c+11809,"VX_cache genblk5[3] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+38801+i*3,"VX_cache genblk5[3] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+38993,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+39017,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+39041,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+39049,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+39057,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+35169,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+35177,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+39065,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[3] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[3] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[3] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[3] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[3] bank dwb_queue reset", false,-1); + vcdp->declBit(c+10777,"VX_cache genblk5[3] bank dwb_queue push", false,-1); + vcdp->declBit(c+1969,"VX_cache genblk5[3] bank dwb_queue pop", false,-1); + vcdp->declArray(c+11817,"VX_cache genblk5[3] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+11873,"VX_cache genblk5[3] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+35185,"VX_cache genblk5[3] bank dwb_queue empty", false,-1); + vcdp->declBit(c+35193,"VX_cache genblk5[3] bank dwb_queue full", false,-1); + vcdp->declBus(c+39073,"VX_cache genblk5[3] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+39073,"VX_cache genblk5[3] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+1073,"VX_cache genblk5[3] bank dwb_queue reading", false,-1); + vcdp->declBit(c+11929,"VX_cache genblk5[3] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+39081+i*7,"VX_cache genblk5[3] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+39305,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+39361,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+39417,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+39425,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+39433,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+35185,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+35193,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+39441,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58641,"VX_cache genblk5[4] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58713,"VX_cache genblk5[4] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[4] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[4] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[4] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[4] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank reset", false,-1); + vcdp->declBus(c+161,"VX_cache genblk5[4] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[4] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[4] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[4] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[4] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[4] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19849,"VX_cache genblk5[4] bank core_req_ready", false,-1); + vcdp->declBit(c+19817,"VX_cache genblk5[4] bank core_rsp_valid", false,-1); + vcdp->declBus(c+3233,"VX_cache genblk5[4] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3241,"VX_cache genblk5[4] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3249,"VX_cache genblk5[4] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+169,"VX_cache genblk5[4] bank core_rsp_ready", false,-1); + vcdp->declBit(c+3265,"VX_cache genblk5[4] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19833,"VX_cache genblk5[4] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[4] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58561,"VX_cache genblk5[4] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[4] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[4] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19825,"VX_cache genblk5[4] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3273,"VX_cache genblk5[4] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+3281,"VX_cache genblk5[4] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3289,"VX_cache genblk5[4] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3297,"VX_cache genblk5[4] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+177,"VX_cache genblk5[4] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58569,"VX_cache genblk5[4] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[4] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[4] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[4] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19841,"VX_cache genblk5[4] bank snp_req_ready", false,-1); + vcdp->declBit(c+3329,"VX_cache genblk5[4] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+3337,"VX_cache genblk5[4] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+185,"VX_cache genblk5[4] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+11937,"VX_cache genblk5[4] bank snrq_pop", false,-1); + vcdp->declBit(c+39449,"VX_cache genblk5[4] bank snrq_empty", false,-1); + vcdp->declBit(c+39457,"VX_cache genblk5[4] bank snrq_full", false,-1); + vcdp->declBus(c+11945,"VX_cache genblk5[4] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+11953,"VX_cache genblk5[4] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+11961,"VX_cache genblk5[4] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+11969,"VX_cache genblk5[4] bank dfpq_pop", false,-1); + vcdp->declBit(c+39465,"VX_cache genblk5[4] bank dfpq_empty", false,-1); + vcdp->declBit(c+39473,"VX_cache genblk5[4] bank dfpq_full", false,-1); + vcdp->declBus(c+11977,"VX_cache genblk5[4] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+11985,"VX_cache genblk5[4] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+12017,"VX_cache genblk5[4] bank reqq_pop", false,-1); + vcdp->declBit(c+1985,"VX_cache genblk5[4] bank reqq_push", false,-1); + vcdp->declBit(c+12025,"VX_cache genblk5[4] bank reqq_empty", false,-1); + vcdp->declBit(c+39481,"VX_cache genblk5[4] bank reqq_full", false,-1); + vcdp->declBit(c+12033,"VX_cache genblk5[4] bank reqq_req_st0", false,-1); + vcdp->declBus(c+12041,"VX_cache genblk5[4] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+12049,"VX_cache genblk5[4] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+12057,"VX_cache genblk5[4] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+12065,"VX_cache genblk5[4] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+12073,"VX_cache genblk5[4] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+12081,"VX_cache genblk5[4] bank mrvq_pop", false,-1); + vcdp->declBit(c+39505,"VX_cache genblk5[4] bank mrvq_full", false,-1); + vcdp->declBit(c+39513,"VX_cache genblk5[4] bank mrvq_stop", false,-1); + vcdp->declBit(c+12089,"VX_cache genblk5[4] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+39521,"VX_cache genblk5[4] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+39529,"VX_cache genblk5[4] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+39537,"VX_cache genblk5[4] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+39545,"VX_cache genblk5[4] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+39553,"VX_cache genblk5[4] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+12097,"VX_cache genblk5[4] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+39569,"VX_cache genblk5[4] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+39577,"VX_cache genblk5[4] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+39585,"VX_cache genblk5[4] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+12105,"VX_cache genblk5[4] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+12113,"VX_cache genblk5[4] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+12121,"VX_cache genblk5[4] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+39593,"VX_cache genblk5[4] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+39601,"VX_cache genblk5[4] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+39617,"VX_cache genblk5[4] bank miss_add_rw", false,-1); + vcdp->declBus(c+39625,"VX_cache genblk5[4] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19833,"VX_cache genblk5[4] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+39633,"VX_cache genblk5[4] bank is_fill_st2", false,-1); + vcdp->declBit(c+12129,"VX_cache genblk5[4] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+12137,"VX_cache genblk5[4] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+12145,"VX_cache genblk5[4] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+12153,"VX_cache genblk5[4] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+12161,"VX_cache genblk5[4] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+12169,"VX_cache genblk5[4] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+12177,"VX_cache genblk5[4] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+12185+i*1,"VX_cache genblk5[4] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+12193+i*1,"VX_cache genblk5[4] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[4] bank j", false,-1, 31,0); + vcdp->declBit(c+12089,"VX_cache genblk5[4] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+12201,"VX_cache genblk5[4] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+12209,"VX_cache genblk5[4] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+12217,"VX_cache genblk5[4] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+12201,"VX_cache genblk5[4] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+12225,"VX_cache genblk5[4] bank qual_valid_st0", false,-1); + vcdp->declBus(c+12233,"VX_cache genblk5[4] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+12241,"VX_cache genblk5[4] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+12089,"VX_cache genblk5[4] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+12249,"VX_cache genblk5[4] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+12257,"VX_cache genblk5[4] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+12289,"VX_cache genblk5[4] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+12305,"VX_cache genblk5[4] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+12313,"VX_cache genblk5[4] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+12321,"VX_cache genblk5[4] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+12329+i*1,"VX_cache genblk5[4] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+12337+i*1,"VX_cache genblk5[4] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+12345+i*1,"VX_cache genblk5[4] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+12353+i*1,"VX_cache genblk5[4] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+12361+i*2,"VX_cache genblk5[4] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+12377+i*4,"VX_cache genblk5[4] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+12409+i*1,"VX_cache genblk5[4] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+12417+i*1,"VX_cache genblk5[4] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+12425+i*1,"VX_cache genblk5[4] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+12433,"VX_cache genblk5[4] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+12441,"VX_cache genblk5[4] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+12473,"VX_cache genblk5[4] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+12481,"VX_cache genblk5[4] bank miss_st1e", false,-1); + vcdp->declBit(c+12489,"VX_cache genblk5[4] bank dirty_st1e", false,-1); + vcdp->declBus(c+12497,"VX_cache genblk5[4] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+12505,"VX_cache genblk5[4] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+12521,"VX_cache genblk5[4] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+12529,"VX_cache genblk5[4] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+12537,"VX_cache genblk5[4] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+12545,"VX_cache genblk5[4] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+12553,"VX_cache genblk5[4] bank is_snp_st1e", false,-1); + vcdp->declBit(c+12561,"VX_cache genblk5[4] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+12569,"VX_cache genblk5[4] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+12577,"VX_cache genblk5[4] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+12585,"VX_cache genblk5[4] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+12593,"VX_cache genblk5[4] bank valid_st1e", false,-1); + vcdp->declBit(c+12601,"VX_cache genblk5[4] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+12609,"VX_cache genblk5[4] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+12617,"VX_cache genblk5[4] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+12625,"VX_cache genblk5[4] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+12601,"VX_cache genblk5[4] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+39641,"VX_cache genblk5[4] bank valid_st2", false,-1); + vcdp->declBus(c+39649,"VX_cache genblk5[4] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+39657,"VX_cache genblk5[4] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+39665,"VX_cache genblk5[4] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+39673,"VX_cache genblk5[4] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+39705,"VX_cache genblk5[4] bank miss_st2", false,-1); + vcdp->declBit(c+39713,"VX_cache genblk5[4] bank dirty_st2", false,-1); + vcdp->declBus(c+39721,"VX_cache genblk5[4] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+39729,"VX_cache genblk5[4] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+39745,"VX_cache genblk5[4] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+39753,"VX_cache genblk5[4] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+39761,"VX_cache genblk5[4] bank is_snp_st2", false,-1); + vcdp->declBit(c+39769,"VX_cache genblk5[4] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+39777,"VX_cache genblk5[4] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+39785,"VX_cache genblk5[4] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+12633,"VX_cache genblk5[4] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+39793,"VX_cache genblk5[4] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+39801,"VX_cache genblk5[4] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+12641,"VX_cache genblk5[4] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+12649,"VX_cache genblk5[4] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+39777,"VX_cache genblk5[4] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+12657,"VX_cache genblk5[4] bank miss_add_unqual", false,-1); + vcdp->declBit(c+12665,"VX_cache genblk5[4] bank miss_add", false,-1); + vcdp->declBus(c+19833,"VX_cache genblk5[4] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+39649,"VX_cache genblk5[4] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+39657,"VX_cache genblk5[4] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+39761,"VX_cache genblk5[4] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+39769,"VX_cache genblk5[4] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+12673,"VX_cache genblk5[4] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+12681,"VX_cache genblk5[4] bank cwbq_push", false,-1); + vcdp->declBit(c+1993,"VX_cache genblk5[4] bank cwbq_pop", false,-1); + vcdp->declBit(c+39809,"VX_cache genblk5[4] bank cwbq_empty", false,-1); + vcdp->declBit(c+39817,"VX_cache genblk5[4] bank cwbq_full", false,-1); + vcdp->declBit(c+12689,"VX_cache genblk5[4] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+39665,"VX_cache genblk5[4] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+39593,"VX_cache genblk5[4] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+39601,"VX_cache genblk5[4] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+12657,"VX_cache genblk5[4] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+12697,"VX_cache genblk5[4] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+12705,"VX_cache genblk5[4] bank dwbq_push", false,-1); + vcdp->declBit(c+2001,"VX_cache genblk5[4] bank dwbq_pop", false,-1); + vcdp->declBit(c+39825,"VX_cache genblk5[4] bank dwbq_empty", false,-1); + vcdp->declBit(c+39833,"VX_cache genblk5[4] bank dwbq_full", false,-1); + vcdp->declBit(c+12713,"VX_cache genblk5[4] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+12721,"VX_cache genblk5[4] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+12729,"VX_cache genblk5[4] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+12737,"VX_cache genblk5[4] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+12745,"VX_cache genblk5[4] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+39841,"VX_cache genblk5[4] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+39849,"VX_cache genblk5[4] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+1081,"VX_cache genblk5[4] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+1089,"VX_cache genblk5[4] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+39857,"VX_cache genblk5[4] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[4] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58569,"VX_cache genblk5[4] bank snp_req_queue push", false,-1); + vcdp->declBit(c+11937,"VX_cache genblk5[4] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+1097,"VX_cache genblk5[4] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+12753,"VX_cache genblk5[4] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+39449,"VX_cache genblk5[4] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+39457,"VX_cache genblk5[4] bank snp_req_queue full", false,-1); + vcdp->declBus(c+39865,"VX_cache genblk5[4] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+39865,"VX_cache genblk5[4] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+12769,"VX_cache genblk5[4] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+1113,"VX_cache genblk5[4] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+39873+i*2,"VX_cache genblk5[4] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+40129,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+40145,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+40161,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+40169,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+40177,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+39449,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+39457,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+40185,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[4] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58561,"VX_cache genblk5[4] bank dfp_queue push", false,-1); + vcdp->declBit(c+11969,"VX_cache genblk5[4] bank dfp_queue pop", false,-1); + vcdp->declArray(c+1121,"VX_cache genblk5[4] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+12777,"VX_cache genblk5[4] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+39465,"VX_cache genblk5[4] bank dfp_queue empty", false,-1); + vcdp->declBit(c+39473,"VX_cache genblk5[4] bank dfp_queue full", false,-1); + vcdp->declBus(c+40193,"VX_cache genblk5[4] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+40193,"VX_cache genblk5[4] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+12817,"VX_cache genblk5[4] bank dfp_queue reading", false,-1); + vcdp->declBit(c+1161,"VX_cache genblk5[4] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+40201+i*5,"VX_cache genblk5[4] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+40841,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+40881,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+40921,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+40929,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+40937,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+39465,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+39473,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+40945,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[4] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1985,"VX_cache genblk5[4] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+161,"VX_cache genblk5[4] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[4] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[4] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[4] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[4] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[4] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+12017,"VX_cache genblk5[4] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+12049,"VX_cache genblk5[4] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+12057,"VX_cache genblk5[4] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+12065,"VX_cache genblk5[4] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+12073,"VX_cache genblk5[4] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+12025,"VX_cache genblk5[4] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+39481,"VX_cache genblk5[4] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+12825,"VX_cache genblk5[4] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+12833,"VX_cache genblk5[4] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+12841,"VX_cache genblk5[4] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+12849,"VX_cache genblk5[4] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+12881,"VX_cache genblk5[4] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+12913,"VX_cache genblk5[4] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+40961,"VX_cache genblk5[4] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+40969,"VX_cache genblk5[4] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+40977,"VX_cache genblk5[4] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+41009,"VX_cache genblk5[4] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+40961,"VX_cache genblk5[4] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+40969,"VX_cache genblk5[4] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+40977,"VX_cache genblk5[4] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+41009,"VX_cache genblk5[4] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+41041,"VX_cache genblk5[4] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+41049,"VX_cache genblk5[4] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+12929,"VX_cache genblk5[4] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+2009,"VX_cache genblk5[4] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+12937,"VX_cache genblk5[4] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+12945,"VX_cache genblk5[4] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[4] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+2009,"VX_cache genblk5[4] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+12937,"VX_cache genblk5[4] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+1169,"VX_cache genblk5[4] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+12953,"VX_cache genblk5[4] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+41041,"VX_cache genblk5[4] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+39481,"VX_cache genblk5[4] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+41057,"VX_cache genblk5[4] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+41057,"VX_cache genblk5[4] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+13033,"VX_cache genblk5[4] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+1249,"VX_cache genblk5[4] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+41065+i*10,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+41705,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+41785,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+41865,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+41873,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+41881,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+41041,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+39481,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+41889,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+13041,"VX_cache genblk5[4] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+13041,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+13049,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[4] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[4] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+12169,"VX_cache genblk5[4] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[4] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+13057,"VX_cache genblk5[4] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+41897,"VX_cache genblk5[4] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+41897,"VX_cache genblk5[4] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[4] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank tag_data_access reset", false,-1); + vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access stall", false,-1); + vcdp->declBit(c+12553,"VX_cache genblk5[4] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+12561,"VX_cache genblk5[4] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+12121,"VX_cache genblk5[4] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+12617,"VX_cache genblk5[4] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+12593,"VX_cache genblk5[4] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+13129,"VX_cache genblk5[4] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+13137,"VX_cache genblk5[4] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+13145,"VX_cache genblk5[4] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+12529,"VX_cache genblk5[4] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+12537,"VX_cache genblk5[4] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+13177,"VX_cache genblk5[4] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+12433,"VX_cache genblk5[4] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+12441,"VX_cache genblk5[4] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+12473,"VX_cache genblk5[4] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+12481,"VX_cache genblk5[4] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+12489,"VX_cache genblk5[4] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+12497,"VX_cache genblk5[4] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+12545,"VX_cache genblk5[4] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+12569,"VX_cache genblk5[4] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+12577,"VX_cache genblk5[4] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+13185+i*1,"VX_cache genblk5[4] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+13193+i*1,"VX_cache genblk5[4] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+13201+i*1,"VX_cache genblk5[4] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+13209+i*1,"VX_cache genblk5[4] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+13217+i*4,"VX_cache genblk5[4] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+13249,"VX_cache genblk5[4] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+13257,"VX_cache genblk5[4] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+13265,"VX_cache genblk5[4] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+13273,"VX_cache genblk5[4] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+13281,"VX_cache genblk5[4] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+13313,"VX_cache genblk5[4] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+13321,"VX_cache genblk5[4] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+12497,"VX_cache genblk5[4] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+12473,"VX_cache genblk5[4] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+12441,"VX_cache genblk5[4] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+13329,"VX_cache genblk5[4] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+13337,"VX_cache genblk5[4] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+12481,"VX_cache genblk5[4] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+13369,"VX_cache genblk5[4] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+13377,"VX_cache genblk5[4] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+13385,"VX_cache genblk5[4] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+13393,"VX_cache genblk5[4] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+13401,"VX_cache genblk5[4] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+13337,"VX_cache genblk5[4] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+13409,"VX_cache genblk5[4] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+13369,"VX_cache genblk5[4] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+13417,"VX_cache genblk5[4] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+13425,"VX_cache genblk5[4] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+13433,"VX_cache genblk5[4] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+13441,"VX_cache genblk5[4] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+13449,"VX_cache genblk5[4] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+13457,"VX_cache genblk5[4] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+13465,"VX_cache genblk5[4] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+13473,"VX_cache genblk5[4] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[4] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+13249,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+13257,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+13265,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+13273,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+13281,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+13369,"VX_cache genblk5[4] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+13329,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+13385,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+13393,"VX_cache genblk5[4] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+13337,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+12481,"VX_cache genblk5[4] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+41961,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+41993,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+42025,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+42057,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+42089,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+42121,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+42153,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+42185,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+42217,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+42249,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+42281,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+42313,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+42345,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+42377,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+42409,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+42441,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+42473+i*1,"VX_cache genblk5[4] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+42601,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+42609,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+42617,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+42625,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+42633,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+42641,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+42649,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+42657,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+42665,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+42673,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+42681,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+42689,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+42697,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+42705,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+42713,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+42721,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+42729,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+42737,"VX_cache genblk5[4] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+13481,"VX_cache genblk5[4] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+42745,"VX_cache genblk5[4] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+42753,"VX_cache genblk5[4] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+13489,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+13489,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+42761,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[4] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[4] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+12169,"VX_cache genblk5[4] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[4] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+13537,"VX_cache genblk5[4] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+42809,"VX_cache genblk5[4] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+42809,"VX_cache genblk5[4] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[4] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58713,"VX_cache genblk5[4] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[4] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[4] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[4] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+12665,"VX_cache genblk5[4] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+12673,"VX_cache genblk5[4] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19833,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+39649,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+39657,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+39593,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+39601,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+39617,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+39625,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+12633,"VX_cache genblk5[4] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+39761,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+39769,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+39505,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+39513,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+13129,"VX_cache genblk5[4] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+12617,"VX_cache genblk5[4] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+12105,"VX_cache genblk5[4] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+12081,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+12089,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+39529,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+39537,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+39545,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+39521,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+39553,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+12097,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+39569,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+39577,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+39585,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+42889+i*3,"VX_cache genblk5[4] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+43273,"VX_cache genblk5[4] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+43377,"VX_cache genblk5[4] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+43385,"VX_cache genblk5[4] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+43393,"VX_cache genblk5[4] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+43401,"VX_cache genblk5[4] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+43409,"VX_cache genblk5[4] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+43417,"VX_cache genblk5[4] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+43425,"VX_cache genblk5[4] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+43409,"VX_cache genblk5[4] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+13617,"VX_cache genblk5[4] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+13625,"VX_cache genblk5[4] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+13633,"VX_cache genblk5[4] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+12089,"VX_cache genblk5[4] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+43393,"VX_cache genblk5[4] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+13641,"VX_cache genblk5[4] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+13649,"VX_cache genblk5[4] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+13657,"VX_cache genblk5[4] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+13665,"VX_cache genblk5[4] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+13673,"VX_cache genblk5[4] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+13681,"VX_cache genblk5[4] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[4] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[4] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank cwb_queue reset", false,-1); + vcdp->declBit(c+12681,"VX_cache genblk5[4] bank cwb_queue push", false,-1); + vcdp->declBit(c+1993,"VX_cache genblk5[4] bank cwb_queue pop", false,-1); + vcdp->declArray(c+13689,"VX_cache genblk5[4] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+13713,"VX_cache genblk5[4] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+39809,"VX_cache genblk5[4] bank cwb_queue empty", false,-1); + vcdp->declBit(c+39817,"VX_cache genblk5[4] bank cwb_queue full", false,-1); + vcdp->declBus(c+43433,"VX_cache genblk5[4] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+43433,"VX_cache genblk5[4] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+1257,"VX_cache genblk5[4] bank cwb_queue reading", false,-1); + vcdp->declBit(c+13737,"VX_cache genblk5[4] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+43441+i*3,"VX_cache genblk5[4] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+43633,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+43657,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+43681,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+43689,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+43697,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+39809,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+39817,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+43705,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[4] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[4] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[4] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[4] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[4] bank dwb_queue reset", false,-1); + vcdp->declBit(c+12705,"VX_cache genblk5[4] bank dwb_queue push", false,-1); + vcdp->declBit(c+2001,"VX_cache genblk5[4] bank dwb_queue pop", false,-1); + vcdp->declArray(c+13745,"VX_cache genblk5[4] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+13801,"VX_cache genblk5[4] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+39825,"VX_cache genblk5[4] bank dwb_queue empty", false,-1); + vcdp->declBit(c+39833,"VX_cache genblk5[4] bank dwb_queue full", false,-1); + vcdp->declBus(c+43713,"VX_cache genblk5[4] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+43713,"VX_cache genblk5[4] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+1265,"VX_cache genblk5[4] bank dwb_queue reading", false,-1); + vcdp->declBit(c+13857,"VX_cache genblk5[4] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+43721+i*7,"VX_cache genblk5[4] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+43945,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+44001,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+44057,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+44065,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+44073,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+39825,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+39833,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+44081,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58641,"VX_cache genblk5[5] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58841,"VX_cache genblk5[5] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[5] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[5] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[5] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[5] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank reset", false,-1); + vcdp->declBus(c+193,"VX_cache genblk5[5] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[5] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[5] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[5] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[5] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[5] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19889,"VX_cache genblk5[5] bank core_req_ready", false,-1); + vcdp->declBit(c+19857,"VX_cache genblk5[5] bank core_rsp_valid", false,-1); + vcdp->declBus(c+3345,"VX_cache genblk5[5] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3353,"VX_cache genblk5[5] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3361,"VX_cache genblk5[5] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+201,"VX_cache genblk5[5] bank core_rsp_ready", false,-1); + vcdp->declBit(c+3377,"VX_cache genblk5[5] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19873,"VX_cache genblk5[5] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[5] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58577,"VX_cache genblk5[5] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[5] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[5] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19865,"VX_cache genblk5[5] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3385,"VX_cache genblk5[5] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+3393,"VX_cache genblk5[5] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3401,"VX_cache genblk5[5] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3409,"VX_cache genblk5[5] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+209,"VX_cache genblk5[5] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58585,"VX_cache genblk5[5] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[5] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[5] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[5] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19881,"VX_cache genblk5[5] bank snp_req_ready", false,-1); + vcdp->declBit(c+3441,"VX_cache genblk5[5] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+3449,"VX_cache genblk5[5] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+217,"VX_cache genblk5[5] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+13865,"VX_cache genblk5[5] bank snrq_pop", false,-1); + vcdp->declBit(c+44089,"VX_cache genblk5[5] bank snrq_empty", false,-1); + vcdp->declBit(c+44097,"VX_cache genblk5[5] bank snrq_full", false,-1); + vcdp->declBus(c+13873,"VX_cache genblk5[5] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+13881,"VX_cache genblk5[5] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+13889,"VX_cache genblk5[5] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+13897,"VX_cache genblk5[5] bank dfpq_pop", false,-1); + vcdp->declBit(c+44105,"VX_cache genblk5[5] bank dfpq_empty", false,-1); + vcdp->declBit(c+44113,"VX_cache genblk5[5] bank dfpq_full", false,-1); + vcdp->declBus(c+13905,"VX_cache genblk5[5] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+13913,"VX_cache genblk5[5] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+13945,"VX_cache genblk5[5] bank reqq_pop", false,-1); + vcdp->declBit(c+2017,"VX_cache genblk5[5] bank reqq_push", false,-1); + vcdp->declBit(c+13953,"VX_cache genblk5[5] bank reqq_empty", false,-1); + vcdp->declBit(c+44121,"VX_cache genblk5[5] bank reqq_full", false,-1); + vcdp->declBit(c+13961,"VX_cache genblk5[5] bank reqq_req_st0", false,-1); + vcdp->declBus(c+13969,"VX_cache genblk5[5] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+13977,"VX_cache genblk5[5] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+13985,"VX_cache genblk5[5] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+13993,"VX_cache genblk5[5] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+14001,"VX_cache genblk5[5] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+14009,"VX_cache genblk5[5] bank mrvq_pop", false,-1); + vcdp->declBit(c+44145,"VX_cache genblk5[5] bank mrvq_full", false,-1); + vcdp->declBit(c+44153,"VX_cache genblk5[5] bank mrvq_stop", false,-1); + vcdp->declBit(c+14017,"VX_cache genblk5[5] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+44161,"VX_cache genblk5[5] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+44169,"VX_cache genblk5[5] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+44177,"VX_cache genblk5[5] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+44185,"VX_cache genblk5[5] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+44193,"VX_cache genblk5[5] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+14025,"VX_cache genblk5[5] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+44209,"VX_cache genblk5[5] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+44217,"VX_cache genblk5[5] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+44225,"VX_cache genblk5[5] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+14033,"VX_cache genblk5[5] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+14041,"VX_cache genblk5[5] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+14049,"VX_cache genblk5[5] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+44233,"VX_cache genblk5[5] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+44241,"VX_cache genblk5[5] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+44257,"VX_cache genblk5[5] bank miss_add_rw", false,-1); + vcdp->declBus(c+44265,"VX_cache genblk5[5] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19873,"VX_cache genblk5[5] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+44273,"VX_cache genblk5[5] bank is_fill_st2", false,-1); + vcdp->declBit(c+14057,"VX_cache genblk5[5] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+14065,"VX_cache genblk5[5] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+14073,"VX_cache genblk5[5] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+14081,"VX_cache genblk5[5] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+14089,"VX_cache genblk5[5] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[5] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[5] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+14113+i*1,"VX_cache genblk5[5] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+14121+i*1,"VX_cache genblk5[5] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[5] bank j", false,-1, 31,0); + vcdp->declBit(c+14017,"VX_cache genblk5[5] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+14129,"VX_cache genblk5[5] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+14137,"VX_cache genblk5[5] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+14145,"VX_cache genblk5[5] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+14129,"VX_cache genblk5[5] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+14153,"VX_cache genblk5[5] bank qual_valid_st0", false,-1); + vcdp->declBus(c+14161,"VX_cache genblk5[5] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+14169,"VX_cache genblk5[5] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+14017,"VX_cache genblk5[5] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+14177,"VX_cache genblk5[5] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+14185,"VX_cache genblk5[5] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+14217,"VX_cache genblk5[5] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+14233,"VX_cache genblk5[5] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+14241,"VX_cache genblk5[5] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+14249,"VX_cache genblk5[5] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+14257+i*1,"VX_cache genblk5[5] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+14265+i*1,"VX_cache genblk5[5] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+14273+i*1,"VX_cache genblk5[5] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+14281+i*1,"VX_cache genblk5[5] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+14289+i*2,"VX_cache genblk5[5] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+14305+i*4,"VX_cache genblk5[5] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+14337+i*1,"VX_cache genblk5[5] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+14345+i*1,"VX_cache genblk5[5] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+14353+i*1,"VX_cache genblk5[5] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+14361,"VX_cache genblk5[5] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+14369,"VX_cache genblk5[5] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+14401,"VX_cache genblk5[5] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+14409,"VX_cache genblk5[5] bank miss_st1e", false,-1); + vcdp->declBit(c+14417,"VX_cache genblk5[5] bank dirty_st1e", false,-1); + vcdp->declBus(c+14425,"VX_cache genblk5[5] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+14433,"VX_cache genblk5[5] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+14449,"VX_cache genblk5[5] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+14457,"VX_cache genblk5[5] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+14465,"VX_cache genblk5[5] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+14473,"VX_cache genblk5[5] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+14481,"VX_cache genblk5[5] bank is_snp_st1e", false,-1); + vcdp->declBit(c+14489,"VX_cache genblk5[5] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+14497,"VX_cache genblk5[5] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+14505,"VX_cache genblk5[5] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+14513,"VX_cache genblk5[5] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+14521,"VX_cache genblk5[5] bank valid_st1e", false,-1); + vcdp->declBit(c+14529,"VX_cache genblk5[5] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+14537,"VX_cache genblk5[5] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+14545,"VX_cache genblk5[5] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+14553,"VX_cache genblk5[5] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+14529,"VX_cache genblk5[5] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+44281,"VX_cache genblk5[5] bank valid_st2", false,-1); + vcdp->declBus(c+44289,"VX_cache genblk5[5] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+44297,"VX_cache genblk5[5] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+44305,"VX_cache genblk5[5] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+44313,"VX_cache genblk5[5] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+44345,"VX_cache genblk5[5] bank miss_st2", false,-1); + vcdp->declBit(c+44353,"VX_cache genblk5[5] bank dirty_st2", false,-1); + vcdp->declBus(c+44361,"VX_cache genblk5[5] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+44369,"VX_cache genblk5[5] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+44385,"VX_cache genblk5[5] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+44393,"VX_cache genblk5[5] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+44401,"VX_cache genblk5[5] bank is_snp_st2", false,-1); + vcdp->declBit(c+44409,"VX_cache genblk5[5] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+44417,"VX_cache genblk5[5] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+44425,"VX_cache genblk5[5] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+14561,"VX_cache genblk5[5] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+44433,"VX_cache genblk5[5] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+44441,"VX_cache genblk5[5] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+14569,"VX_cache genblk5[5] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+14577,"VX_cache genblk5[5] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+44417,"VX_cache genblk5[5] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+14585,"VX_cache genblk5[5] bank miss_add_unqual", false,-1); + vcdp->declBit(c+14593,"VX_cache genblk5[5] bank miss_add", false,-1); + vcdp->declBus(c+19873,"VX_cache genblk5[5] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+44289,"VX_cache genblk5[5] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+44297,"VX_cache genblk5[5] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+44401,"VX_cache genblk5[5] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+44409,"VX_cache genblk5[5] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+14601,"VX_cache genblk5[5] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+14609,"VX_cache genblk5[5] bank cwbq_push", false,-1); + vcdp->declBit(c+2025,"VX_cache genblk5[5] bank cwbq_pop", false,-1); + vcdp->declBit(c+44449,"VX_cache genblk5[5] bank cwbq_empty", false,-1); + vcdp->declBit(c+44457,"VX_cache genblk5[5] bank cwbq_full", false,-1); + vcdp->declBit(c+14617,"VX_cache genblk5[5] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+44305,"VX_cache genblk5[5] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+44233,"VX_cache genblk5[5] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+44241,"VX_cache genblk5[5] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+14585,"VX_cache genblk5[5] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+14625,"VX_cache genblk5[5] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+14633,"VX_cache genblk5[5] bank dwbq_push", false,-1); + vcdp->declBit(c+2033,"VX_cache genblk5[5] bank dwbq_pop", false,-1); + vcdp->declBit(c+44465,"VX_cache genblk5[5] bank dwbq_empty", false,-1); + vcdp->declBit(c+44473,"VX_cache genblk5[5] bank dwbq_full", false,-1); + vcdp->declBit(c+14641,"VX_cache genblk5[5] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+14649,"VX_cache genblk5[5] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+14657,"VX_cache genblk5[5] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+14665,"VX_cache genblk5[5] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+14673,"VX_cache genblk5[5] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+44481,"VX_cache genblk5[5] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+44489,"VX_cache genblk5[5] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+1273,"VX_cache genblk5[5] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+1281,"VX_cache genblk5[5] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+44497,"VX_cache genblk5[5] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[5] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58585,"VX_cache genblk5[5] bank snp_req_queue push", false,-1); + vcdp->declBit(c+13865,"VX_cache genblk5[5] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+1289,"VX_cache genblk5[5] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+14681,"VX_cache genblk5[5] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+44089,"VX_cache genblk5[5] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+44097,"VX_cache genblk5[5] bank snp_req_queue full", false,-1); + vcdp->declBus(c+44505,"VX_cache genblk5[5] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+44505,"VX_cache genblk5[5] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+14697,"VX_cache genblk5[5] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+1305,"VX_cache genblk5[5] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+44513+i*2,"VX_cache genblk5[5] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+44769,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+44785,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+44801,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+44809,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+44817,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+44089,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+44097,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+44825,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[5] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58577,"VX_cache genblk5[5] bank dfp_queue push", false,-1); + vcdp->declBit(c+13897,"VX_cache genblk5[5] bank dfp_queue pop", false,-1); + vcdp->declArray(c+1313,"VX_cache genblk5[5] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+14705,"VX_cache genblk5[5] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+44105,"VX_cache genblk5[5] bank dfp_queue empty", false,-1); + vcdp->declBit(c+44113,"VX_cache genblk5[5] bank dfp_queue full", false,-1); + vcdp->declBus(c+44833,"VX_cache genblk5[5] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+44833,"VX_cache genblk5[5] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+14745,"VX_cache genblk5[5] bank dfp_queue reading", false,-1); + vcdp->declBit(c+1353,"VX_cache genblk5[5] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+44841+i*5,"VX_cache genblk5[5] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+45481,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+45521,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+45561,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+45569,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+45577,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+44105,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+44113,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+45585,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[5] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank core_req_arb reset", false,-1); + vcdp->declBit(c+2017,"VX_cache genblk5[5] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+193,"VX_cache genblk5[5] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[5] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[5] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[5] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[5] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[5] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+13945,"VX_cache genblk5[5] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+13977,"VX_cache genblk5[5] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+13985,"VX_cache genblk5[5] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+13993,"VX_cache genblk5[5] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+14001,"VX_cache genblk5[5] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+13953,"VX_cache genblk5[5] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+44121,"VX_cache genblk5[5] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+14753,"VX_cache genblk5[5] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+14761,"VX_cache genblk5[5] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+14769,"VX_cache genblk5[5] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+14777,"VX_cache genblk5[5] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+14809,"VX_cache genblk5[5] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+14841,"VX_cache genblk5[5] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+45601,"VX_cache genblk5[5] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+45609,"VX_cache genblk5[5] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+45617,"VX_cache genblk5[5] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+45649,"VX_cache genblk5[5] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+45601,"VX_cache genblk5[5] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+45609,"VX_cache genblk5[5] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+45617,"VX_cache genblk5[5] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+45649,"VX_cache genblk5[5] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+45681,"VX_cache genblk5[5] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+45689,"VX_cache genblk5[5] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+14857,"VX_cache genblk5[5] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+2041,"VX_cache genblk5[5] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+14865,"VX_cache genblk5[5] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+14873,"VX_cache genblk5[5] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[5] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+2041,"VX_cache genblk5[5] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+14865,"VX_cache genblk5[5] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+1361,"VX_cache genblk5[5] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+14881,"VX_cache genblk5[5] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+45681,"VX_cache genblk5[5] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+44121,"VX_cache genblk5[5] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+45697,"VX_cache genblk5[5] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+45697,"VX_cache genblk5[5] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+14961,"VX_cache genblk5[5] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+1441,"VX_cache genblk5[5] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+45705+i*10,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+46345,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+46425,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+46505,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+46513,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+46521,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+45681,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+44121,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+46529,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+14969,"VX_cache genblk5[5] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+14969,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+14977,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[5] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[5] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[5] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[5] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+14985,"VX_cache genblk5[5] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+46537,"VX_cache genblk5[5] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+46537,"VX_cache genblk5[5] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[5] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank tag_data_access reset", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access stall", false,-1); + vcdp->declBit(c+14481,"VX_cache genblk5[5] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+14489,"VX_cache genblk5[5] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+14049,"VX_cache genblk5[5] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+14545,"VX_cache genblk5[5] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+14521,"VX_cache genblk5[5] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+15057,"VX_cache genblk5[5] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+15065,"VX_cache genblk5[5] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+15073,"VX_cache genblk5[5] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+14457,"VX_cache genblk5[5] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+14465,"VX_cache genblk5[5] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+15105,"VX_cache genblk5[5] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+14361,"VX_cache genblk5[5] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+14369,"VX_cache genblk5[5] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+14401,"VX_cache genblk5[5] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+14409,"VX_cache genblk5[5] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+14417,"VX_cache genblk5[5] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+14425,"VX_cache genblk5[5] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+14473,"VX_cache genblk5[5] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+14497,"VX_cache genblk5[5] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+14505,"VX_cache genblk5[5] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+15113+i*1,"VX_cache genblk5[5] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+15121+i*1,"VX_cache genblk5[5] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+15129+i*1,"VX_cache genblk5[5] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+15137+i*1,"VX_cache genblk5[5] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+15145+i*4,"VX_cache genblk5[5] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+15177,"VX_cache genblk5[5] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+15185,"VX_cache genblk5[5] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+15193,"VX_cache genblk5[5] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+15201,"VX_cache genblk5[5] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+15209,"VX_cache genblk5[5] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+15241,"VX_cache genblk5[5] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+15249,"VX_cache genblk5[5] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+14425,"VX_cache genblk5[5] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+14401,"VX_cache genblk5[5] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+14369,"VX_cache genblk5[5] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+15257,"VX_cache genblk5[5] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+15265,"VX_cache genblk5[5] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+14409,"VX_cache genblk5[5] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+15297,"VX_cache genblk5[5] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+15305,"VX_cache genblk5[5] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+15313,"VX_cache genblk5[5] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+15321,"VX_cache genblk5[5] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+15329,"VX_cache genblk5[5] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+15265,"VX_cache genblk5[5] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+15337,"VX_cache genblk5[5] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+15297,"VX_cache genblk5[5] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+15345,"VX_cache genblk5[5] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+15353,"VX_cache genblk5[5] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+15361,"VX_cache genblk5[5] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+15369,"VX_cache genblk5[5] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+15377,"VX_cache genblk5[5] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+15385,"VX_cache genblk5[5] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+15393,"VX_cache genblk5[5] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+15401,"VX_cache genblk5[5] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[5] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+15177,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+15185,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+15193,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+15201,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+15209,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+15297,"VX_cache genblk5[5] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+15257,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+15313,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+15321,"VX_cache genblk5[5] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+15265,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+14409,"VX_cache genblk5[5] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+46601,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+46633,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+46665,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+46697,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+46729,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+46761,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+46793,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+46825,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+46857,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+46889,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+46921,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+46953,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+46985,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+47017,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+47049,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+47081,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+47113+i*1,"VX_cache genblk5[5] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+47241,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+47249,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+47257,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+47265,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+47273,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+47281,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+47289,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+47297,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+47305,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+47313,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+47321,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+47329,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+47337,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+47345,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+47353,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+47361,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+47369,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+47377,"VX_cache genblk5[5] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+15409,"VX_cache genblk5[5] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+47385,"VX_cache genblk5[5] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+47393,"VX_cache genblk5[5] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+15417,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+15417,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+47401,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[5] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[5] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[5] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[5] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+15465,"VX_cache genblk5[5] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+47449,"VX_cache genblk5[5] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+47449,"VX_cache genblk5[5] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[5] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58841,"VX_cache genblk5[5] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[5] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[5] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[5] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+14593,"VX_cache genblk5[5] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+14601,"VX_cache genblk5[5] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19873,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+44289,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+44297,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+44233,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+44241,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+44257,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+44265,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+14561,"VX_cache genblk5[5] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+44401,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+44409,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+44145,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+44153,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+15057,"VX_cache genblk5[5] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+14545,"VX_cache genblk5[5] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+14033,"VX_cache genblk5[5] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+14009,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+14017,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+44169,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+44177,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+44185,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+44161,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+44193,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+14025,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+44209,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+44217,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+44225,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+47529+i*3,"VX_cache genblk5[5] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+47913,"VX_cache genblk5[5] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+48017,"VX_cache genblk5[5] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+48025,"VX_cache genblk5[5] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+48033,"VX_cache genblk5[5] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+48041,"VX_cache genblk5[5] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+48049,"VX_cache genblk5[5] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+48057,"VX_cache genblk5[5] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+48065,"VX_cache genblk5[5] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+48049,"VX_cache genblk5[5] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+15545,"VX_cache genblk5[5] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+15553,"VX_cache genblk5[5] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+15561,"VX_cache genblk5[5] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+14017,"VX_cache genblk5[5] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+48033,"VX_cache genblk5[5] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+15569,"VX_cache genblk5[5] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+15577,"VX_cache genblk5[5] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+15585,"VX_cache genblk5[5] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+15593,"VX_cache genblk5[5] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+15601,"VX_cache genblk5[5] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+15609,"VX_cache genblk5[5] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[5] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[5] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank cwb_queue reset", false,-1); + vcdp->declBit(c+14609,"VX_cache genblk5[5] bank cwb_queue push", false,-1); + vcdp->declBit(c+2025,"VX_cache genblk5[5] bank cwb_queue pop", false,-1); + vcdp->declArray(c+15617,"VX_cache genblk5[5] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+15641,"VX_cache genblk5[5] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+44449,"VX_cache genblk5[5] bank cwb_queue empty", false,-1); + vcdp->declBit(c+44457,"VX_cache genblk5[5] bank cwb_queue full", false,-1); + vcdp->declBus(c+48073,"VX_cache genblk5[5] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+48073,"VX_cache genblk5[5] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+1449,"VX_cache genblk5[5] bank cwb_queue reading", false,-1); + vcdp->declBit(c+15665,"VX_cache genblk5[5] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+48081+i*3,"VX_cache genblk5[5] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+48273,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+48297,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+48321,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+48329,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+48337,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+44449,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+44457,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+48345,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[5] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[5] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[5] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[5] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[5] bank dwb_queue reset", false,-1); + vcdp->declBit(c+14633,"VX_cache genblk5[5] bank dwb_queue push", false,-1); + vcdp->declBit(c+2033,"VX_cache genblk5[5] bank dwb_queue pop", false,-1); + vcdp->declArray(c+15673,"VX_cache genblk5[5] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+15729,"VX_cache genblk5[5] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+44465,"VX_cache genblk5[5] bank dwb_queue empty", false,-1); + vcdp->declBit(c+44473,"VX_cache genblk5[5] bank dwb_queue full", false,-1); + vcdp->declBus(c+48353,"VX_cache genblk5[5] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+48353,"VX_cache genblk5[5] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+1457,"VX_cache genblk5[5] bank dwb_queue reading", false,-1); + vcdp->declBit(c+15785,"VX_cache genblk5[5] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+48361+i*7,"VX_cache genblk5[5] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+48585,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+48641,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+48697,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+48705,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+48713,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+44465,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+44473,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+48721,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58641,"VX_cache genblk5[6] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58849,"VX_cache genblk5[6] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[6] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[6] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[6] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[6] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank reset", false,-1); + vcdp->declBus(c+225,"VX_cache genblk5[6] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[6] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[6] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[6] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[6] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[6] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19929,"VX_cache genblk5[6] bank core_req_ready", false,-1); + vcdp->declBit(c+19897,"VX_cache genblk5[6] bank core_rsp_valid", false,-1); + vcdp->declBus(c+3457,"VX_cache genblk5[6] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3465,"VX_cache genblk5[6] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3473,"VX_cache genblk5[6] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+233,"VX_cache genblk5[6] bank core_rsp_ready", false,-1); + vcdp->declBit(c+3489,"VX_cache genblk5[6] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19913,"VX_cache genblk5[6] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[6] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58593,"VX_cache genblk5[6] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[6] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[6] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19905,"VX_cache genblk5[6] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3497,"VX_cache genblk5[6] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+3505,"VX_cache genblk5[6] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3513,"VX_cache genblk5[6] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3521,"VX_cache genblk5[6] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+241,"VX_cache genblk5[6] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58601,"VX_cache genblk5[6] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[6] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[6] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[6] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19921,"VX_cache genblk5[6] bank snp_req_ready", false,-1); + vcdp->declBit(c+3553,"VX_cache genblk5[6] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+3561,"VX_cache genblk5[6] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+249,"VX_cache genblk5[6] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+15793,"VX_cache genblk5[6] bank snrq_pop", false,-1); + vcdp->declBit(c+48729,"VX_cache genblk5[6] bank snrq_empty", false,-1); + vcdp->declBit(c+48737,"VX_cache genblk5[6] bank snrq_full", false,-1); + vcdp->declBus(c+15801,"VX_cache genblk5[6] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+15809,"VX_cache genblk5[6] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+15817,"VX_cache genblk5[6] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+15825,"VX_cache genblk5[6] bank dfpq_pop", false,-1); + vcdp->declBit(c+48745,"VX_cache genblk5[6] bank dfpq_empty", false,-1); + vcdp->declBit(c+48753,"VX_cache genblk5[6] bank dfpq_full", false,-1); + vcdp->declBus(c+15833,"VX_cache genblk5[6] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+15841,"VX_cache genblk5[6] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+15873,"VX_cache genblk5[6] bank reqq_pop", false,-1); + vcdp->declBit(c+2049,"VX_cache genblk5[6] bank reqq_push", false,-1); + vcdp->declBit(c+15881,"VX_cache genblk5[6] bank reqq_empty", false,-1); + vcdp->declBit(c+48761,"VX_cache genblk5[6] bank reqq_full", false,-1); + vcdp->declBit(c+15889,"VX_cache genblk5[6] bank reqq_req_st0", false,-1); + vcdp->declBus(c+15897,"VX_cache genblk5[6] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+15905,"VX_cache genblk5[6] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+15913,"VX_cache genblk5[6] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+15921,"VX_cache genblk5[6] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+15929,"VX_cache genblk5[6] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+15937,"VX_cache genblk5[6] bank mrvq_pop", false,-1); + vcdp->declBit(c+48785,"VX_cache genblk5[6] bank mrvq_full", false,-1); + vcdp->declBit(c+48793,"VX_cache genblk5[6] bank mrvq_stop", false,-1); + vcdp->declBit(c+15945,"VX_cache genblk5[6] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+48801,"VX_cache genblk5[6] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+48809,"VX_cache genblk5[6] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+48817,"VX_cache genblk5[6] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+48825,"VX_cache genblk5[6] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+48833,"VX_cache genblk5[6] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+15953,"VX_cache genblk5[6] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+48849,"VX_cache genblk5[6] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+48857,"VX_cache genblk5[6] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+48865,"VX_cache genblk5[6] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+15961,"VX_cache genblk5[6] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+15969,"VX_cache genblk5[6] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+15977,"VX_cache genblk5[6] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+48873,"VX_cache genblk5[6] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+48881,"VX_cache genblk5[6] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+48897,"VX_cache genblk5[6] bank miss_add_rw", false,-1); + vcdp->declBus(c+48905,"VX_cache genblk5[6] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19913,"VX_cache genblk5[6] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+48913,"VX_cache genblk5[6] bank is_fill_st2", false,-1); + vcdp->declBit(c+15985,"VX_cache genblk5[6] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+15993,"VX_cache genblk5[6] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+16001,"VX_cache genblk5[6] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+16009,"VX_cache genblk5[6] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+16017,"VX_cache genblk5[6] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+16025,"VX_cache genblk5[6] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+16033,"VX_cache genblk5[6] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+16041+i*1,"VX_cache genblk5[6] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+16049+i*1,"VX_cache genblk5[6] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[6] bank j", false,-1, 31,0); + vcdp->declBit(c+15945,"VX_cache genblk5[6] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+16057,"VX_cache genblk5[6] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+16065,"VX_cache genblk5[6] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+16073,"VX_cache genblk5[6] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+16057,"VX_cache genblk5[6] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+16081,"VX_cache genblk5[6] bank qual_valid_st0", false,-1); + vcdp->declBus(c+16089,"VX_cache genblk5[6] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+16097,"VX_cache genblk5[6] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+15945,"VX_cache genblk5[6] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+16105,"VX_cache genblk5[6] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+16113,"VX_cache genblk5[6] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+16145,"VX_cache genblk5[6] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+16161,"VX_cache genblk5[6] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+16169,"VX_cache genblk5[6] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+16177,"VX_cache genblk5[6] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+16185+i*1,"VX_cache genblk5[6] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+16193+i*1,"VX_cache genblk5[6] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+16201+i*1,"VX_cache genblk5[6] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+16209+i*1,"VX_cache genblk5[6] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+16217+i*2,"VX_cache genblk5[6] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+16233+i*4,"VX_cache genblk5[6] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+16265+i*1,"VX_cache genblk5[6] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+16273+i*1,"VX_cache genblk5[6] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+16281+i*1,"VX_cache genblk5[6] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+16289,"VX_cache genblk5[6] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+16297,"VX_cache genblk5[6] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+16329,"VX_cache genblk5[6] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+16337,"VX_cache genblk5[6] bank miss_st1e", false,-1); + vcdp->declBit(c+16345,"VX_cache genblk5[6] bank dirty_st1e", false,-1); + vcdp->declBus(c+16353,"VX_cache genblk5[6] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+16361,"VX_cache genblk5[6] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+16377,"VX_cache genblk5[6] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+16385,"VX_cache genblk5[6] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+16393,"VX_cache genblk5[6] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+16401,"VX_cache genblk5[6] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+16409,"VX_cache genblk5[6] bank is_snp_st1e", false,-1); + vcdp->declBit(c+16417,"VX_cache genblk5[6] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+16425,"VX_cache genblk5[6] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+16433,"VX_cache genblk5[6] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+16441,"VX_cache genblk5[6] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+16449,"VX_cache genblk5[6] bank valid_st1e", false,-1); + vcdp->declBit(c+16457,"VX_cache genblk5[6] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+16465,"VX_cache genblk5[6] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+16473,"VX_cache genblk5[6] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+16481,"VX_cache genblk5[6] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+16457,"VX_cache genblk5[6] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+48921,"VX_cache genblk5[6] bank valid_st2", false,-1); + vcdp->declBus(c+48929,"VX_cache genblk5[6] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+48937,"VX_cache genblk5[6] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+48945,"VX_cache genblk5[6] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+48953,"VX_cache genblk5[6] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+48985,"VX_cache genblk5[6] bank miss_st2", false,-1); + vcdp->declBit(c+48993,"VX_cache genblk5[6] bank dirty_st2", false,-1); + vcdp->declBus(c+49001,"VX_cache genblk5[6] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+49009,"VX_cache genblk5[6] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+49025,"VX_cache genblk5[6] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+49033,"VX_cache genblk5[6] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+49041,"VX_cache genblk5[6] bank is_snp_st2", false,-1); + vcdp->declBit(c+49049,"VX_cache genblk5[6] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+49057,"VX_cache genblk5[6] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+49065,"VX_cache genblk5[6] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+16489,"VX_cache genblk5[6] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+49073,"VX_cache genblk5[6] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+49081,"VX_cache genblk5[6] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+16497,"VX_cache genblk5[6] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+16505,"VX_cache genblk5[6] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+49057,"VX_cache genblk5[6] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+16513,"VX_cache genblk5[6] bank miss_add_unqual", false,-1); + vcdp->declBit(c+16521,"VX_cache genblk5[6] bank miss_add", false,-1); + vcdp->declBus(c+19913,"VX_cache genblk5[6] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+48929,"VX_cache genblk5[6] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+48937,"VX_cache genblk5[6] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+49041,"VX_cache genblk5[6] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+49049,"VX_cache genblk5[6] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+16529,"VX_cache genblk5[6] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+16537,"VX_cache genblk5[6] bank cwbq_push", false,-1); + vcdp->declBit(c+2057,"VX_cache genblk5[6] bank cwbq_pop", false,-1); + vcdp->declBit(c+49089,"VX_cache genblk5[6] bank cwbq_empty", false,-1); + vcdp->declBit(c+49097,"VX_cache genblk5[6] bank cwbq_full", false,-1); + vcdp->declBit(c+16545,"VX_cache genblk5[6] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+48945,"VX_cache genblk5[6] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+48873,"VX_cache genblk5[6] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+48881,"VX_cache genblk5[6] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+16513,"VX_cache genblk5[6] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+16553,"VX_cache genblk5[6] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+16561,"VX_cache genblk5[6] bank dwbq_push", false,-1); + vcdp->declBit(c+2065,"VX_cache genblk5[6] bank dwbq_pop", false,-1); + vcdp->declBit(c+49105,"VX_cache genblk5[6] bank dwbq_empty", false,-1); + vcdp->declBit(c+49113,"VX_cache genblk5[6] bank dwbq_full", false,-1); + vcdp->declBit(c+16569,"VX_cache genblk5[6] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+16577,"VX_cache genblk5[6] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+16585,"VX_cache genblk5[6] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+16593,"VX_cache genblk5[6] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+16601,"VX_cache genblk5[6] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+49121,"VX_cache genblk5[6] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+49129,"VX_cache genblk5[6] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+1465,"VX_cache genblk5[6] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+1473,"VX_cache genblk5[6] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+49137,"VX_cache genblk5[6] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[6] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58601,"VX_cache genblk5[6] bank snp_req_queue push", false,-1); + vcdp->declBit(c+15793,"VX_cache genblk5[6] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+1481,"VX_cache genblk5[6] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+16609,"VX_cache genblk5[6] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+48729,"VX_cache genblk5[6] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+48737,"VX_cache genblk5[6] bank snp_req_queue full", false,-1); + vcdp->declBus(c+49145,"VX_cache genblk5[6] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+49145,"VX_cache genblk5[6] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+16625,"VX_cache genblk5[6] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+1497,"VX_cache genblk5[6] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+49153+i*2,"VX_cache genblk5[6] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+49409,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+49425,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+49441,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+49449,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+49457,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+48729,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+48737,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+49465,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[6] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58593,"VX_cache genblk5[6] bank dfp_queue push", false,-1); + vcdp->declBit(c+15825,"VX_cache genblk5[6] bank dfp_queue pop", false,-1); + vcdp->declArray(c+1505,"VX_cache genblk5[6] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+16633,"VX_cache genblk5[6] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+48745,"VX_cache genblk5[6] bank dfp_queue empty", false,-1); + vcdp->declBit(c+48753,"VX_cache genblk5[6] bank dfp_queue full", false,-1); + vcdp->declBus(c+49473,"VX_cache genblk5[6] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+49473,"VX_cache genblk5[6] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+16673,"VX_cache genblk5[6] bank dfp_queue reading", false,-1); + vcdp->declBit(c+1545,"VX_cache genblk5[6] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+49481+i*5,"VX_cache genblk5[6] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+50121,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+50161,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+50201,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+50209,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+50217,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+48745,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+48753,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+50225,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[6] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank core_req_arb reset", false,-1); + vcdp->declBit(c+2049,"VX_cache genblk5[6] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+225,"VX_cache genblk5[6] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[6] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[6] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[6] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[6] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[6] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+15873,"VX_cache genblk5[6] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+15905,"VX_cache genblk5[6] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+15913,"VX_cache genblk5[6] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+15921,"VX_cache genblk5[6] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+15929,"VX_cache genblk5[6] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+15881,"VX_cache genblk5[6] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+48761,"VX_cache genblk5[6] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+16681,"VX_cache genblk5[6] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+16689,"VX_cache genblk5[6] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+16697,"VX_cache genblk5[6] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+16705,"VX_cache genblk5[6] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+16737,"VX_cache genblk5[6] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+16769,"VX_cache genblk5[6] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+50241,"VX_cache genblk5[6] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+50249,"VX_cache genblk5[6] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+50257,"VX_cache genblk5[6] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+50289,"VX_cache genblk5[6] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+50241,"VX_cache genblk5[6] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+50249,"VX_cache genblk5[6] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+50257,"VX_cache genblk5[6] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+50289,"VX_cache genblk5[6] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+50321,"VX_cache genblk5[6] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+50329,"VX_cache genblk5[6] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+16785,"VX_cache genblk5[6] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+2073,"VX_cache genblk5[6] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+16793,"VX_cache genblk5[6] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+16801,"VX_cache genblk5[6] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[6] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+2073,"VX_cache genblk5[6] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+16793,"VX_cache genblk5[6] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+1553,"VX_cache genblk5[6] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+16809,"VX_cache genblk5[6] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+50321,"VX_cache genblk5[6] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+48761,"VX_cache genblk5[6] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+50337,"VX_cache genblk5[6] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+50337,"VX_cache genblk5[6] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+16889,"VX_cache genblk5[6] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+1633,"VX_cache genblk5[6] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+50345+i*10,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+50985,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+51065,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+51145,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+51153,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+51161,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+50321,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+48761,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+51169,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+16897,"VX_cache genblk5[6] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+16897,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+16905,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[6] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[6] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+16025,"VX_cache genblk5[6] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[6] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+16913,"VX_cache genblk5[6] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+51177,"VX_cache genblk5[6] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+51177,"VX_cache genblk5[6] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[6] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank tag_data_access reset", false,-1); + vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access stall", false,-1); + vcdp->declBit(c+16409,"VX_cache genblk5[6] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+16417,"VX_cache genblk5[6] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+15977,"VX_cache genblk5[6] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+16473,"VX_cache genblk5[6] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+16449,"VX_cache genblk5[6] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+16985,"VX_cache genblk5[6] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+16993,"VX_cache genblk5[6] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+17001,"VX_cache genblk5[6] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+16385,"VX_cache genblk5[6] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+16393,"VX_cache genblk5[6] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+17033,"VX_cache genblk5[6] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+16289,"VX_cache genblk5[6] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+16297,"VX_cache genblk5[6] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+16329,"VX_cache genblk5[6] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+16337,"VX_cache genblk5[6] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+16345,"VX_cache genblk5[6] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+16353,"VX_cache genblk5[6] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+16401,"VX_cache genblk5[6] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+16425,"VX_cache genblk5[6] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+16433,"VX_cache genblk5[6] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+17041+i*1,"VX_cache genblk5[6] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+17049+i*1,"VX_cache genblk5[6] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+17057+i*1,"VX_cache genblk5[6] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+17065+i*1,"VX_cache genblk5[6] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+17073+i*4,"VX_cache genblk5[6] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+17105,"VX_cache genblk5[6] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+17113,"VX_cache genblk5[6] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+17121,"VX_cache genblk5[6] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+17129,"VX_cache genblk5[6] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+17137,"VX_cache genblk5[6] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+17169,"VX_cache genblk5[6] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+17177,"VX_cache genblk5[6] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+16353,"VX_cache genblk5[6] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+16329,"VX_cache genblk5[6] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+16297,"VX_cache genblk5[6] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+17185,"VX_cache genblk5[6] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+17193,"VX_cache genblk5[6] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+16337,"VX_cache genblk5[6] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+17225,"VX_cache genblk5[6] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+17233,"VX_cache genblk5[6] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+17241,"VX_cache genblk5[6] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+17249,"VX_cache genblk5[6] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+17257,"VX_cache genblk5[6] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+17193,"VX_cache genblk5[6] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+17265,"VX_cache genblk5[6] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+17225,"VX_cache genblk5[6] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+17273,"VX_cache genblk5[6] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+17281,"VX_cache genblk5[6] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+17289,"VX_cache genblk5[6] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+17297,"VX_cache genblk5[6] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+17305,"VX_cache genblk5[6] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+17313,"VX_cache genblk5[6] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+17321,"VX_cache genblk5[6] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+17329,"VX_cache genblk5[6] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[6] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+17105,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+17113,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+17121,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+17129,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+17137,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+17225,"VX_cache genblk5[6] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+17185,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+17241,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+17249,"VX_cache genblk5[6] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+17193,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+16337,"VX_cache genblk5[6] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+51241,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+51273,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+51305,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+51337,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+51369,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+51401,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+51433,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+51465,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+51497,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+51529,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+51561,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+51593,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+51625,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+51657,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+51689,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+51721,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+51753+i*1,"VX_cache genblk5[6] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+51881,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+51889,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+51897,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+51905,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+51913,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+51921,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+51929,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+51937,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+51945,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+51953,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+51961,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+51969,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+51977,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+51985,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+51993,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+52001,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+52009,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+52017,"VX_cache genblk5[6] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+17337,"VX_cache genblk5[6] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+52025,"VX_cache genblk5[6] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+52033,"VX_cache genblk5[6] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+17345,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+17345,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+52041,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[6] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[6] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+16025,"VX_cache genblk5[6] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[6] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+17393,"VX_cache genblk5[6] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+52089,"VX_cache genblk5[6] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+52089,"VX_cache genblk5[6] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[6] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58849,"VX_cache genblk5[6] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[6] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[6] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[6] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+16521,"VX_cache genblk5[6] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+16529,"VX_cache genblk5[6] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19913,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+48929,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+48937,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+48873,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+48881,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+48897,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+48905,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+16489,"VX_cache genblk5[6] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+49041,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+49049,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+48785,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+48793,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+16985,"VX_cache genblk5[6] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+16473,"VX_cache genblk5[6] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+15961,"VX_cache genblk5[6] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+15937,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+15945,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+48809,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+48817,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+48825,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+48801,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+48833,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+15953,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+48849,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+48857,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+48865,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+52169+i*3,"VX_cache genblk5[6] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+52553,"VX_cache genblk5[6] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+52657,"VX_cache genblk5[6] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+52665,"VX_cache genblk5[6] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+52673,"VX_cache genblk5[6] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+52681,"VX_cache genblk5[6] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+52689,"VX_cache genblk5[6] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+52697,"VX_cache genblk5[6] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+52705,"VX_cache genblk5[6] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+52689,"VX_cache genblk5[6] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+17473,"VX_cache genblk5[6] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+17481,"VX_cache genblk5[6] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+17489,"VX_cache genblk5[6] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+15945,"VX_cache genblk5[6] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+52673,"VX_cache genblk5[6] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+17497,"VX_cache genblk5[6] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+17505,"VX_cache genblk5[6] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+17513,"VX_cache genblk5[6] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+17521,"VX_cache genblk5[6] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+17529,"VX_cache genblk5[6] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+17537,"VX_cache genblk5[6] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[6] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[6] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank cwb_queue reset", false,-1); + vcdp->declBit(c+16537,"VX_cache genblk5[6] bank cwb_queue push", false,-1); + vcdp->declBit(c+2057,"VX_cache genblk5[6] bank cwb_queue pop", false,-1); + vcdp->declArray(c+17545,"VX_cache genblk5[6] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+17569,"VX_cache genblk5[6] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+49089,"VX_cache genblk5[6] bank cwb_queue empty", false,-1); + vcdp->declBit(c+49097,"VX_cache genblk5[6] bank cwb_queue full", false,-1); + vcdp->declBus(c+52713,"VX_cache genblk5[6] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+52713,"VX_cache genblk5[6] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+1641,"VX_cache genblk5[6] bank cwb_queue reading", false,-1); + vcdp->declBit(c+17593,"VX_cache genblk5[6] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+52721+i*3,"VX_cache genblk5[6] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+52913,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+52937,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+52961,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+52969,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+52977,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+49089,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+49097,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+52985,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[6] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[6] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[6] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[6] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[6] bank dwb_queue reset", false,-1); + vcdp->declBit(c+16561,"VX_cache genblk5[6] bank dwb_queue push", false,-1); + vcdp->declBit(c+2065,"VX_cache genblk5[6] bank dwb_queue pop", false,-1); + vcdp->declArray(c+17601,"VX_cache genblk5[6] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+17657,"VX_cache genblk5[6] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+49105,"VX_cache genblk5[6] bank dwb_queue empty", false,-1); + vcdp->declBit(c+49113,"VX_cache genblk5[6] bank dwb_queue full", false,-1); + vcdp->declBus(c+52993,"VX_cache genblk5[6] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+52993,"VX_cache genblk5[6] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+1649,"VX_cache genblk5[6] bank dwb_queue reading", false,-1); + vcdp->declBit(c+17713,"VX_cache genblk5[6] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+53001+i*7,"VX_cache genblk5[6] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+53225,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+53281,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+53337,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+53345,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+53353,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+49105,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+49113,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+53361,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58641,"VX_cache genblk5[7] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58857,"VX_cache genblk5[7] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58649,"VX_cache genblk5[7] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[7] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[7] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[7] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank reset", false,-1); + vcdp->declBus(c+257,"VX_cache genblk5[7] bank core_req_valid", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[7] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[7] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+58049,"VX_cache genblk5[7] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+58081,"VX_cache genblk5[7] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[7] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+19969,"VX_cache genblk5[7] bank core_req_ready", false,-1); + vcdp->declBit(c+19937,"VX_cache genblk5[7] bank core_rsp_valid", false,-1); + vcdp->declBus(c+3569,"VX_cache genblk5[7] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+3577,"VX_cache genblk5[7] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+3585,"VX_cache genblk5[7] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+265,"VX_cache genblk5[7] bank core_rsp_ready", false,-1); + vcdp->declBit(c+3601,"VX_cache genblk5[7] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+19953,"VX_cache genblk5[7] bank dram_fill_req_addr", false,-1, 24,0); + vcdp->declBit(c+19649,"VX_cache genblk5[7] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+58609,"VX_cache genblk5[7] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+58289,"VX_cache genblk5[7] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+58489,"VX_cache genblk5[7] bank dram_fill_rsp_addr", false,-1, 24,0); + vcdp->declBit(c+19945,"VX_cache genblk5[7] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+3609,"VX_cache genblk5[7] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+3617,"VX_cache genblk5[7] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+3625,"VX_cache genblk5[7] bank dram_wb_req_addr", false,-1, 24,0); + vcdp->declArray(c+3633,"VX_cache genblk5[7] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+273,"VX_cache genblk5[7] bank dram_wb_req_ready", false,-1); + vcdp->declBit(c+58617,"VX_cache genblk5[7] bank snp_req_valid", false,-1); + vcdp->declBus(c+58505,"VX_cache genblk5[7] bank snp_req_addr", false,-1, 24,0); + vcdp->declBit(c+58353,"VX_cache genblk5[7] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+58361,"VX_cache genblk5[7] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+19961,"VX_cache genblk5[7] bank snp_req_ready", false,-1); + vcdp->declBit(c+3665,"VX_cache genblk5[7] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+3673,"VX_cache genblk5[7] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+281,"VX_cache genblk5[7] bank snp_rsp_ready", false,-1); + vcdp->declBit(c+17721,"VX_cache genblk5[7] bank snrq_pop", false,-1); + vcdp->declBit(c+53369,"VX_cache genblk5[7] bank snrq_empty", false,-1); + vcdp->declBit(c+53377,"VX_cache genblk5[7] bank snrq_full", false,-1); + vcdp->declBus(c+17729,"VX_cache genblk5[7] bank snrq_addr_st0", false,-1, 24,0); + vcdp->declBit(c+17737,"VX_cache genblk5[7] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+17745,"VX_cache genblk5[7] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+17753,"VX_cache genblk5[7] bank dfpq_pop", false,-1); + vcdp->declBit(c+53385,"VX_cache genblk5[7] bank dfpq_empty", false,-1); + vcdp->declBit(c+53393,"VX_cache genblk5[7] bank dfpq_full", false,-1); + vcdp->declBus(c+17761,"VX_cache genblk5[7] bank dfpq_addr_st0", false,-1, 24,0); + vcdp->declArray(c+17769,"VX_cache genblk5[7] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+17801,"VX_cache genblk5[7] bank reqq_pop", false,-1); + vcdp->declBit(c+2081,"VX_cache genblk5[7] bank reqq_push", false,-1); + vcdp->declBit(c+17809,"VX_cache genblk5[7] bank reqq_empty", false,-1); + vcdp->declBit(c+53401,"VX_cache genblk5[7] bank reqq_full", false,-1); + vcdp->declBit(c+17817,"VX_cache genblk5[7] bank reqq_req_st0", false,-1); + vcdp->declBus(c+17825,"VX_cache genblk5[7] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+17833,"VX_cache genblk5[7] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+17841,"VX_cache genblk5[7] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+17849,"VX_cache genblk5[7] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+17857,"VX_cache genblk5[7] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+17865,"VX_cache genblk5[7] bank mrvq_pop", false,-1); + vcdp->declBit(c+53425,"VX_cache genblk5[7] bank mrvq_full", false,-1); + vcdp->declBit(c+53433,"VX_cache genblk5[7] bank mrvq_stop", false,-1); + vcdp->declBit(c+17873,"VX_cache genblk5[7] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+53441,"VX_cache genblk5[7] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+53449,"VX_cache genblk5[7] bank mrvq_addr_st0", false,-1, 24,0); + vcdp->declBus(c+53457,"VX_cache genblk5[7] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+53465,"VX_cache genblk5[7] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+53473,"VX_cache genblk5[7] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+17881,"VX_cache genblk5[7] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+53489,"VX_cache genblk5[7] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+53497,"VX_cache genblk5[7] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+53505,"VX_cache genblk5[7] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+17889,"VX_cache genblk5[7] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+17897,"VX_cache genblk5[7] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+17905,"VX_cache genblk5[7] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+53513,"VX_cache genblk5[7] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+53521,"VX_cache genblk5[7] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+53537,"VX_cache genblk5[7] bank miss_add_rw", false,-1); + vcdp->declBus(c+53545,"VX_cache genblk5[7] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+19953,"VX_cache genblk5[7] bank addr_st2", false,-1, 24,0); + vcdp->declBit(c+53553,"VX_cache genblk5[7] bank is_fill_st2", false,-1); + vcdp->declBit(c+17913,"VX_cache genblk5[7] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+17921,"VX_cache genblk5[7] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+17929,"VX_cache genblk5[7] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+17937,"VX_cache genblk5[7] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+17945,"VX_cache genblk5[7] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[7] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+17961,"VX_cache genblk5[7] bank is_fill_in_pipe", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+17969+i*1,"VX_cache genblk5[7] bank is_fill_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+17977+i*1,"VX_cache genblk5[7] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+58753,"VX_cache genblk5[7] bank j", false,-1, 31,0); + vcdp->declBit(c+17873,"VX_cache genblk5[7] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+17985,"VX_cache genblk5[7] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+17993,"VX_cache genblk5[7] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+18001,"VX_cache genblk5[7] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+17985,"VX_cache genblk5[7] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+18009,"VX_cache genblk5[7] bank qual_valid_st0", false,-1); + vcdp->declBus(c+18017,"VX_cache genblk5[7] bank qual_addr_st0", false,-1, 24,0); + vcdp->declBus(c+18025,"VX_cache genblk5[7] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+17873,"VX_cache genblk5[7] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+18033,"VX_cache genblk5[7] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+18041,"VX_cache genblk5[7] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+18073,"VX_cache genblk5[7] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+18089,"VX_cache genblk5[7] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+18097,"VX_cache genblk5[7] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+18105,"VX_cache genblk5[7] bank qual_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+18113+i*1,"VX_cache genblk5[7] bank valid_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+18121+i*1,"VX_cache genblk5[7] bank addr_st1", true,(i+0), 24,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+18129+i*1,"VX_cache genblk5[7] bank wsel_st1", true,(i+0), 1,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+18137+i*1,"VX_cache genblk5[7] bank writeword_st1", true,(i+0), 31,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declQuad(c+18145+i*2,"VX_cache genblk5[7] bank inst_meta_st1", true,(i+0), 48,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+18161+i*4,"VX_cache genblk5[7] bank writedata_st1", true,(i+0), 127,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+18193+i*1,"VX_cache genblk5[7] bank is_snp_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+18201+i*1,"VX_cache genblk5[7] bank snp_invalidate_st1", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+18209+i*1,"VX_cache genblk5[7] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+18217,"VX_cache genblk5[7] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+18225,"VX_cache genblk5[7] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+18257,"VX_cache genblk5[7] bank readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+18265,"VX_cache genblk5[7] bank miss_st1e", false,-1); + vcdp->declBit(c+18273,"VX_cache genblk5[7] bank dirty_st1e", false,-1); + vcdp->declBus(c+18281,"VX_cache genblk5[7] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+18289,"VX_cache genblk5[7] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+18305,"VX_cache genblk5[7] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+18313,"VX_cache genblk5[7] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+18321,"VX_cache genblk5[7] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+18329,"VX_cache genblk5[7] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+18337,"VX_cache genblk5[7] bank is_snp_st1e", false,-1); + vcdp->declBit(c+18345,"VX_cache genblk5[7] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+18353,"VX_cache genblk5[7] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+18361,"VX_cache genblk5[7] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+18369,"VX_cache genblk5[7] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+18377,"VX_cache genblk5[7] bank valid_st1e", false,-1); + vcdp->declBit(c+18385,"VX_cache genblk5[7] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+18393,"VX_cache genblk5[7] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+18401,"VX_cache genblk5[7] bank addr_st1e", false,-1, 24,0); + vcdp->declBit(c+18409,"VX_cache genblk5[7] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+18385,"VX_cache genblk5[7] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+53561,"VX_cache genblk5[7] bank valid_st2", false,-1); + vcdp->declBus(c+53569,"VX_cache genblk5[7] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+53577,"VX_cache genblk5[7] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+53585,"VX_cache genblk5[7] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+53593,"VX_cache genblk5[7] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+53625,"VX_cache genblk5[7] bank miss_st2", false,-1); + vcdp->declBit(c+53633,"VX_cache genblk5[7] bank dirty_st2", false,-1); + vcdp->declBus(c+53641,"VX_cache genblk5[7] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+53649,"VX_cache genblk5[7] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+53665,"VX_cache genblk5[7] bank readtag_st2", false,-1, 20,0); + vcdp->declBit(c+53673,"VX_cache genblk5[7] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+53681,"VX_cache genblk5[7] bank is_snp_st2", false,-1); + vcdp->declBit(c+53689,"VX_cache genblk5[7] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+53697,"VX_cache genblk5[7] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+53705,"VX_cache genblk5[7] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+18417,"VX_cache genblk5[7] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+53713,"VX_cache genblk5[7] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+53721,"VX_cache genblk5[7] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+18425,"VX_cache genblk5[7] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+18433,"VX_cache genblk5[7] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+53697,"VX_cache genblk5[7] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+18441,"VX_cache genblk5[7] bank miss_add_unqual", false,-1); + vcdp->declBit(c+18449,"VX_cache genblk5[7] bank miss_add", false,-1); + vcdp->declBus(c+19953,"VX_cache genblk5[7] bank miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+53569,"VX_cache genblk5[7] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+53577,"VX_cache genblk5[7] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+53681,"VX_cache genblk5[7] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+53689,"VX_cache genblk5[7] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+18457,"VX_cache genblk5[7] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+18465,"VX_cache genblk5[7] bank cwbq_push", false,-1); + vcdp->declBit(c+2089,"VX_cache genblk5[7] bank cwbq_pop", false,-1); + vcdp->declBit(c+53729,"VX_cache genblk5[7] bank cwbq_empty", false,-1); + vcdp->declBit(c+53737,"VX_cache genblk5[7] bank cwbq_full", false,-1); + vcdp->declBit(c+18473,"VX_cache genblk5[7] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+53585,"VX_cache genblk5[7] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+53513,"VX_cache genblk5[7] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+53521,"VX_cache genblk5[7] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+18441,"VX_cache genblk5[7] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+18481,"VX_cache genblk5[7] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+18489,"VX_cache genblk5[7] bank dwbq_push", false,-1); + vcdp->declBit(c+2097,"VX_cache genblk5[7] bank dwbq_pop", false,-1); + vcdp->declBit(c+53745,"VX_cache genblk5[7] bank dwbq_empty", false,-1); + vcdp->declBit(c+53753,"VX_cache genblk5[7] bank dwbq_full", false,-1); + vcdp->declBit(c+18497,"VX_cache genblk5[7] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+18505,"VX_cache genblk5[7] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+18513,"VX_cache genblk5[7] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+18521,"VX_cache genblk5[7] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+18529,"VX_cache genblk5[7] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+53761,"VX_cache genblk5[7] bank dwbq_req_addr", false,-1, 24,0); + vcdp->declBus(c+53769,"VX_cache genblk5[7] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+1657,"VX_cache genblk5[7] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+1665,"VX_cache genblk5[7] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+53777,"VX_cache genblk5[7] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+58761,"VX_cache genblk5[7] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+58617,"VX_cache genblk5[7] bank snp_req_queue push", false,-1); + vcdp->declBit(c+17721,"VX_cache genblk5[7] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+1673,"VX_cache genblk5[7] bank snp_req_queue data_in", false,-1, 53,0); + vcdp->declQuad(c+18537,"VX_cache genblk5[7] bank snp_req_queue data_out", false,-1, 53,0); + vcdp->declBit(c+53369,"VX_cache genblk5[7] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+53377,"VX_cache genblk5[7] bank snp_req_queue full", false,-1); + vcdp->declBus(c+53785,"VX_cache genblk5[7] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+53785,"VX_cache genblk5[7] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+18553,"VX_cache genblk5[7] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+1689,"VX_cache genblk5[7] bank snp_req_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declQuad(c+53793+i*2,"VX_cache genblk5[7] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} + vcdp->declQuad(c+54049,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); + vcdp->declQuad(c+54065,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); + vcdp->declBus(c+54081,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+54089,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+54097,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+53369,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+53377,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+54105,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58769,"VX_cache genblk5[7] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank dfp_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank dfp_queue reset", false,-1); + vcdp->declBit(c+58609,"VX_cache genblk5[7] bank dfp_queue push", false,-1); + vcdp->declBit(c+17753,"VX_cache genblk5[7] bank dfp_queue pop", false,-1); + vcdp->declArray(c+1697,"VX_cache genblk5[7] bank dfp_queue data_in", false,-1, 152,0); + vcdp->declArray(c+18561,"VX_cache genblk5[7] bank dfp_queue data_out", false,-1, 152,0); + vcdp->declBit(c+53385,"VX_cache genblk5[7] bank dfp_queue empty", false,-1); + vcdp->declBit(c+53393,"VX_cache genblk5[7] bank dfp_queue full", false,-1); + vcdp->declBus(c+54113,"VX_cache genblk5[7] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+54113,"VX_cache genblk5[7] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+18601,"VX_cache genblk5[7] bank dfp_queue reading", false,-1); + vcdp->declBit(c+1737,"VX_cache genblk5[7] bank dfp_queue writing", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+54121+i*5,"VX_cache genblk5[7] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} + vcdp->declArray(c+54761,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); + vcdp->declArray(c+54801,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); + vcdp->declBus(c+54841,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+54849,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+54857,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+53385,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+53393,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+54865,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[7] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank core_req_arb clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank core_req_arb reset", false,-1); + vcdp->declBit(c+2081,"VX_cache genblk5[7] bank core_req_arb reqq_push", false,-1); + vcdp->declBus(c+257,"VX_cache genblk5[7] bank core_req_arb bank_valids", false,-1, 3,0); + vcdp->declBus(c+58033,"VX_cache genblk5[7] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+58041,"VX_cache genblk5[7] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+58081,"VX_cache genblk5[7] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+58049,"VX_cache genblk5[7] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+58113,"VX_cache genblk5[7] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+17801,"VX_cache genblk5[7] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+17833,"VX_cache genblk5[7] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+17841,"VX_cache genblk5[7] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+17849,"VX_cache genblk5[7] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+17857,"VX_cache genblk5[7] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+17809,"VX_cache genblk5[7] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+53401,"VX_cache genblk5[7] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+18609,"VX_cache genblk5[7] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+18617,"VX_cache genblk5[7] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+18625,"VX_cache genblk5[7] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+18633,"VX_cache genblk5[7] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+18665,"VX_cache genblk5[7] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+18697,"VX_cache genblk5[7] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+54881,"VX_cache genblk5[7] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+54889,"VX_cache genblk5[7] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+54897,"VX_cache genblk5[7] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+54929,"VX_cache genblk5[7] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+54881,"VX_cache genblk5[7] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+54889,"VX_cache genblk5[7] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+54897,"VX_cache genblk5[7] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+54929,"VX_cache genblk5[7] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+54961,"VX_cache genblk5[7] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+54969,"VX_cache genblk5[7] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+18713,"VX_cache genblk5[7] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+2105,"VX_cache genblk5[7] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+18721,"VX_cache genblk5[7] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+18729,"VX_cache genblk5[7] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+58777,"VX_cache genblk5[7] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+2105,"VX_cache genblk5[7] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+18721,"VX_cache genblk5[7] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+1745,"VX_cache genblk5[7] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+18737,"VX_cache genblk5[7] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+54961,"VX_cache genblk5[7] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+53401,"VX_cache genblk5[7] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+54977,"VX_cache genblk5[7] bank core_req_arb reqq_queue size", false,-1, 3,0); + vcdp->declBus(c+54977,"VX_cache genblk5[7] bank core_req_arb reqq_queue size_r", false,-1, 3,0); + vcdp->declBit(c+18817,"VX_cache genblk5[7] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+1825,"VX_cache genblk5[7] bank core_req_arb reqq_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+54985+i*10,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+55625,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+55705,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+55785,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+55793,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+55801,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+54961,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+53401,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+55809,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+18825,"VX_cache genblk5[7] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+18825,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+18833,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+58785,"VX_cache genblk5[7] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[7] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[7] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[7] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+18841,"VX_cache genblk5[7] bank s0_1_c0 in", false,-1, 241,0); + vcdp->declArray(c+55817,"VX_cache genblk5[7] bank s0_1_c0 out", false,-1, 241,0); + vcdp->declArray(c+55817,"VX_cache genblk5[7] bank s0_1_c0 value", false,-1, 241,0); + vcdp->declBus(c+58649,"VX_cache genblk5[7] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank tag_data_access clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank tag_data_access reset", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access stall", false,-1); + vcdp->declBit(c+18337,"VX_cache genblk5[7] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+18345,"VX_cache genblk5[7] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+17905,"VX_cache genblk5[7] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access readaddr_st10", false,-1, 3,0); + vcdp->declBus(c+18401,"VX_cache genblk5[7] bank tag_data_access writeaddr_st1e", false,-1, 24,0); + vcdp->declBit(c+18377,"VX_cache genblk5[7] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+18913,"VX_cache genblk5[7] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+18921,"VX_cache genblk5[7] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+18929,"VX_cache genblk5[7] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+18313,"VX_cache genblk5[7] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+18321,"VX_cache genblk5[7] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+18961,"VX_cache genblk5[7] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+18217,"VX_cache genblk5[7] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+18225,"VX_cache genblk5[7] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+18257,"VX_cache genblk5[7] bank tag_data_access readtag_st1e", false,-1, 20,0); + vcdp->declBit(c+18265,"VX_cache genblk5[7] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+18273,"VX_cache genblk5[7] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+18281,"VX_cache genblk5[7] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+18329,"VX_cache genblk5[7] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+18353,"VX_cache genblk5[7] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+18361,"VX_cache genblk5[7] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+18969+i*1,"VX_cache genblk5[7] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+18977+i*1,"VX_cache genblk5[7] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+18985+i*1,"VX_cache genblk5[7] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+18993+i*1,"VX_cache genblk5[7] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+19001+i*4,"VX_cache genblk5[7] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+19033,"VX_cache genblk5[7] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+19041,"VX_cache genblk5[7] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+19049,"VX_cache genblk5[7] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+19057,"VX_cache genblk5[7] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); + vcdp->declArray(c+19065,"VX_cache genblk5[7] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+19097,"VX_cache genblk5[7] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+19105,"VX_cache genblk5[7] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+18281,"VX_cache genblk5[7] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+18257,"VX_cache genblk5[7] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); + vcdp->declArray(c+18225,"VX_cache genblk5[7] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+19113,"VX_cache genblk5[7] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+19121,"VX_cache genblk5[7] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+18265,"VX_cache genblk5[7] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+19153,"VX_cache genblk5[7] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+19161,"VX_cache genblk5[7] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+19169,"VX_cache genblk5[7] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+19177,"VX_cache genblk5[7] bank tag_data_access writetag_st1e", false,-1, 20,0); + vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access writeladdr_st1e", false,-1, 3,0); + vcdp->declBus(c+19185,"VX_cache genblk5[7] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+19121,"VX_cache genblk5[7] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+19193,"VX_cache genblk5[7] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+19153,"VX_cache genblk5[7] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+19201,"VX_cache genblk5[7] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+19209,"VX_cache genblk5[7] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+19217,"VX_cache genblk5[7] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+19225,"VX_cache genblk5[7] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+19233,"VX_cache genblk5[7] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+19241,"VX_cache genblk5[7] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+19249,"VX_cache genblk5[7] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+19257,"VX_cache genblk5[7] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+58649,"VX_cache genblk5[7] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); + vcdp->declBit(c+19033,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+19041,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+19049,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+19057,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); + vcdp->declArray(c+19065,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+19153,"VX_cache genblk5[7] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+19113,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+19169,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); + vcdp->declBus(c+19177,"VX_cache genblk5[7] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); + vcdp->declArray(c+19121,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+18265,"VX_cache genblk5[7] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declArray(c+55881,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); + vcdp->declArray(c+55913,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); + vcdp->declArray(c+55945,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); + vcdp->declArray(c+55977,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); + vcdp->declArray(c+56009,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); + vcdp->declArray(c+56041,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); + vcdp->declArray(c+56073,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); + vcdp->declArray(c+56105,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); + vcdp->declArray(c+56137,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); + vcdp->declArray(c+56169,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); + vcdp->declArray(c+56201,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); + vcdp->declArray(c+56233,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); + vcdp->declArray(c+56265,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); + vcdp->declArray(c+56297,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); + vcdp->declArray(c+56329,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); + vcdp->declArray(c+56361,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); + {int i; for (i=0; i<16; i++) { + vcdp->declBus(c+56393+i*1,"VX_cache genblk5[7] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} + vcdp->declBus(c+56521,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); + vcdp->declBus(c+56529,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); + vcdp->declBus(c+56537,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); + vcdp->declBus(c+56545,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); + vcdp->declBus(c+56553,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); + vcdp->declBus(c+56561,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); + vcdp->declBus(c+56569,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); + vcdp->declBus(c+56577,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); + vcdp->declBus(c+56585,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); + vcdp->declBus(c+56593,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); + vcdp->declBus(c+56601,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); + vcdp->declBus(c+56609,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); + vcdp->declBus(c+56617,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); + vcdp->declBus(c+56625,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); + vcdp->declBus(c+56633,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); + vcdp->declBus(c+56641,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); + vcdp->declBus(c+56649,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); + vcdp->declBus(c+56657,"VX_cache genblk5[7] bank tag_data_access tag_data_structure valid", false,-1, 15,0); + vcdp->declBit(c+19265,"VX_cache genblk5[7] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+56665,"VX_cache genblk5[7] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+56673,"VX_cache genblk5[7] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+58793,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+19273,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 in", false,-1, 166,0); + vcdp->declArray(c+19273,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 out", false,-1, 166,0); + vcdp->declArray(c+56681,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 value", false,-1, 166,0); + vcdp->declBus(c+58801,"VX_cache genblk5[7] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+58641,"VX_cache genblk5[7] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[7] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+58721,"VX_cache genblk5[7] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+19321,"VX_cache genblk5[7] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+56729,"VX_cache genblk5[7] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+56729,"VX_cache genblk5[7] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+58641,"VX_cache genblk5[7] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+58857,"VX_cache genblk5[7] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+58657,"VX_cache genblk5[7] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+58689,"VX_cache genblk5[7] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+58697,"VX_cache genblk5[7] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+18449,"VX_cache genblk5[7] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+18457,"VX_cache genblk5[7] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+19953,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); + vcdp->declBus(c+53569,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+53577,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+53513,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+53521,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+53537,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+53545,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+18417,"VX_cache genblk5[7] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+53681,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+53689,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+53425,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+53433,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+18913,"VX_cache genblk5[7] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+18401,"VX_cache genblk5[7] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); + vcdp->declBit(c+17889,"VX_cache genblk5[7] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+17865,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+17873,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+53449,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); + vcdp->declBus(c+53457,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+53465,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+53441,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+53473,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+17881,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+53489,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+53497,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+53505,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+56809+i*3,"VX_cache genblk5[7] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+57193,"VX_cache genblk5[7] bank cache_miss_resrv addr_table", false,-1, 399,0); + vcdp->declBus(c+57297,"VX_cache genblk5[7] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+57305,"VX_cache genblk5[7] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+57313,"VX_cache genblk5[7] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+57321,"VX_cache genblk5[7] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+57329,"VX_cache genblk5[7] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+57337,"VX_cache genblk5[7] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+57345,"VX_cache genblk5[7] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+57329,"VX_cache genblk5[7] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+19401,"VX_cache genblk5[7] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+19409,"VX_cache genblk5[7] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+19417,"VX_cache genblk5[7] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+17873,"VX_cache genblk5[7] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+57313,"VX_cache genblk5[7] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+19425,"VX_cache genblk5[7] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+19433,"VX_cache genblk5[7] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+19441,"VX_cache genblk5[7] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+19449,"VX_cache genblk5[7] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+19457,"VX_cache genblk5[7] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+19465,"VX_cache genblk5[7] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+58809,"VX_cache genblk5[7] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58665,"VX_cache genblk5[7] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank cwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank cwb_queue reset", false,-1); + vcdp->declBit(c+18465,"VX_cache genblk5[7] bank cwb_queue push", false,-1); + vcdp->declBit(c+2089,"VX_cache genblk5[7] bank cwb_queue pop", false,-1); + vcdp->declArray(c+19473,"VX_cache genblk5[7] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+19497,"VX_cache genblk5[7] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+53729,"VX_cache genblk5[7] bank cwb_queue empty", false,-1); + vcdp->declBit(c+53737,"VX_cache genblk5[7] bank cwb_queue full", false,-1); + vcdp->declBus(c+57353,"VX_cache genblk5[7] bank cwb_queue size", false,-1, 3,0); + vcdp->declBus(c+57353,"VX_cache genblk5[7] bank cwb_queue size_r", false,-1, 3,0); + vcdp->declBit(c+1833,"VX_cache genblk5[7] bank cwb_queue reading", false,-1); + vcdp->declBit(c+19521,"VX_cache genblk5[7] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<8; i++) { + vcdp->declArray(c+57361+i*3,"VX_cache genblk5[7] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+57553,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+57577,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+57601,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); + vcdp->declBus(c+57609,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); + vcdp->declBus(c+57617,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); + vcdp->declBit(c+53729,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+53737,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+57625,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+58817,"VX_cache genblk5[7] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+58673,"VX_cache genblk5[7] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+58681,"VX_cache genblk5[7] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+58009,"VX_cache genblk5[7] bank dwb_queue clk", false,-1); + vcdp->declBit(c+58017,"VX_cache genblk5[7] bank dwb_queue reset", false,-1); + vcdp->declBit(c+18489,"VX_cache genblk5[7] bank dwb_queue push", false,-1); + vcdp->declBit(c+2097,"VX_cache genblk5[7] bank dwb_queue pop", false,-1); + vcdp->declArray(c+19529,"VX_cache genblk5[7] bank dwb_queue data_in", false,-1, 198,0); + vcdp->declArray(c+19585,"VX_cache genblk5[7] bank dwb_queue data_out", false,-1, 198,0); + vcdp->declBit(c+53745,"VX_cache genblk5[7] bank dwb_queue empty", false,-1); + vcdp->declBit(c+53753,"VX_cache genblk5[7] bank dwb_queue full", false,-1); + vcdp->declBus(c+57633,"VX_cache genblk5[7] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+57633,"VX_cache genblk5[7] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+1841,"VX_cache genblk5[7] bank dwb_queue reading", false,-1); + vcdp->declBit(c+19641,"VX_cache genblk5[7] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+57641+i*7,"VX_cache genblk5[7] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} + vcdp->declArray(c+57865,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); + vcdp->declArray(c+57921,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); + vcdp->declBus(c+57977,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+57985,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+57993,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+53745,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+53753,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+58001,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + } +} + +void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedVcd* vcdp, uint32_t code) { + VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; + int c = code; + if (0 && vcdp && c) {} // Prevent unused + // Variables + WData/*127:0*/ __Vtemp1013[4]; + WData/*127:0*/ __Vtemp1032[4]; + WData/*127:0*/ __Vtemp1051[4]; + WData/*127:0*/ __Vtemp1070[4]; + WData/*127:0*/ __Vtemp1089[4]; + WData/*127:0*/ __Vtemp1108[4]; + WData/*127:0*/ __Vtemp1127[4]; + WData/*127:0*/ __Vtemp1146[4]; + WData/*127:0*/ __Vtemp1155[4]; + WData/*127:0*/ __Vtemp1156[4]; + WData/*127:0*/ __Vtemp1157[4]; + WData/*127:0*/ __Vtemp1158[4]; + WData/*127:0*/ __Vtemp1159[4]; + WData/*127:0*/ __Vtemp1160[4]; + WData/*127:0*/ __Vtemp1161[4]; + WData/*127:0*/ __Vtemp1162[4]; + WData/*127:0*/ __Vtemp1163[4]; + WData/*127:0*/ __Vtemp1164[4]; + WData/*127:0*/ __Vtemp1165[4]; + WData/*127:0*/ __Vtemp1166[4]; + WData/*127:0*/ __Vtemp1167[4]; + WData/*127:0*/ __Vtemp1168[4]; + WData/*127:0*/ __Vtemp1169[4]; + WData/*127:0*/ __Vtemp1170[4]; + WData/*127:0*/ __Vtemp1179[4]; + WData/*127:0*/ __Vtemp1180[4]; + WData/*127:0*/ __Vtemp1181[4]; + WData/*127:0*/ __Vtemp1182[4]; + WData/*127:0*/ __Vtemp1183[4]; + WData/*127:0*/ __Vtemp1184[4]; + WData/*127:0*/ __Vtemp1185[4]; + WData/*127:0*/ __Vtemp1186[4]; + WData/*127:0*/ __Vtemp1187[4]; + WData/*127:0*/ __Vtemp1188[4]; + WData/*127:0*/ __Vtemp1189[4]; + WData/*127:0*/ __Vtemp1190[4]; + WData/*127:0*/ __Vtemp1191[4]; + WData/*127:0*/ __Vtemp1192[4]; + WData/*127:0*/ __Vtemp1193[4]; + WData/*127:0*/ __Vtemp1194[4]; + WData/*127:0*/ __Vtemp1203[4]; + WData/*127:0*/ __Vtemp1204[4]; + WData/*127:0*/ __Vtemp1205[4]; + WData/*127:0*/ __Vtemp1206[4]; + WData/*127:0*/ __Vtemp1207[4]; + WData/*127:0*/ __Vtemp1208[4]; + WData/*127:0*/ __Vtemp1209[4]; + WData/*127:0*/ __Vtemp1210[4]; + WData/*127:0*/ __Vtemp1211[4]; + WData/*127:0*/ __Vtemp1212[4]; + WData/*127:0*/ __Vtemp1213[4]; + WData/*127:0*/ __Vtemp1214[4]; + WData/*127:0*/ __Vtemp1215[4]; + WData/*127:0*/ __Vtemp1216[4]; + WData/*127:0*/ __Vtemp1217[4]; + WData/*127:0*/ __Vtemp1218[4]; + WData/*127:0*/ __Vtemp1227[4]; + WData/*127:0*/ __Vtemp1228[4]; + WData/*127:0*/ __Vtemp1229[4]; + WData/*127:0*/ __Vtemp1230[4]; + WData/*127:0*/ __Vtemp1231[4]; + WData/*127:0*/ __Vtemp1232[4]; + WData/*127:0*/ __Vtemp1233[4]; + WData/*127:0*/ __Vtemp1234[4]; + WData/*127:0*/ __Vtemp1235[4]; + WData/*127:0*/ __Vtemp1236[4]; + WData/*127:0*/ __Vtemp1237[4]; + WData/*127:0*/ __Vtemp1238[4]; + WData/*127:0*/ __Vtemp1239[4]; + WData/*127:0*/ __Vtemp1240[4]; + WData/*127:0*/ __Vtemp1241[4]; + WData/*127:0*/ __Vtemp1242[4]; + WData/*127:0*/ __Vtemp1251[4]; + WData/*127:0*/ __Vtemp1252[4]; + WData/*127:0*/ __Vtemp1253[4]; + WData/*127:0*/ __Vtemp1254[4]; + WData/*127:0*/ __Vtemp1255[4]; + WData/*127:0*/ __Vtemp1256[4]; + WData/*127:0*/ __Vtemp1257[4]; + WData/*127:0*/ __Vtemp1258[4]; + WData/*127:0*/ __Vtemp1259[4]; + WData/*127:0*/ __Vtemp1260[4]; + WData/*127:0*/ __Vtemp1261[4]; + WData/*127:0*/ __Vtemp1262[4]; + WData/*127:0*/ __Vtemp1263[4]; + WData/*127:0*/ __Vtemp1264[4]; + WData/*127:0*/ __Vtemp1265[4]; + WData/*127:0*/ __Vtemp1266[4]; + WData/*127:0*/ __Vtemp1275[4]; + WData/*127:0*/ __Vtemp1276[4]; + WData/*127:0*/ __Vtemp1277[4]; + WData/*127:0*/ __Vtemp1278[4]; + WData/*127:0*/ __Vtemp1279[4]; + WData/*127:0*/ __Vtemp1280[4]; + WData/*127:0*/ __Vtemp1281[4]; + WData/*127:0*/ __Vtemp1282[4]; + WData/*127:0*/ __Vtemp1283[4]; + WData/*127:0*/ __Vtemp1284[4]; + WData/*127:0*/ __Vtemp1285[4]; + WData/*127:0*/ __Vtemp1286[4]; + WData/*127:0*/ __Vtemp1287[4]; + WData/*127:0*/ __Vtemp1288[4]; + WData/*127:0*/ __Vtemp1289[4]; + WData/*127:0*/ __Vtemp1290[4]; + WData/*127:0*/ __Vtemp1299[4]; + WData/*127:0*/ __Vtemp1300[4]; + WData/*127:0*/ __Vtemp1301[4]; + WData/*127:0*/ __Vtemp1302[4]; + WData/*127:0*/ __Vtemp1303[4]; + WData/*127:0*/ __Vtemp1304[4]; + WData/*127:0*/ __Vtemp1305[4]; + WData/*127:0*/ __Vtemp1306[4]; + WData/*127:0*/ __Vtemp1307[4]; + WData/*127:0*/ __Vtemp1308[4]; + WData/*127:0*/ __Vtemp1309[4]; + WData/*127:0*/ __Vtemp1310[4]; + WData/*127:0*/ __Vtemp1311[4]; + WData/*127:0*/ __Vtemp1312[4]; + WData/*127:0*/ __Vtemp1313[4]; + WData/*127:0*/ __Vtemp1314[4]; + WData/*127:0*/ __Vtemp1323[4]; + WData/*127:0*/ __Vtemp1324[4]; + WData/*127:0*/ __Vtemp1325[4]; + WData/*127:0*/ __Vtemp1326[4]; + WData/*127:0*/ __Vtemp1327[4]; + WData/*127:0*/ __Vtemp1328[4]; + WData/*127:0*/ __Vtemp1329[4]; + WData/*127:0*/ __Vtemp1330[4]; + WData/*127:0*/ __Vtemp1331[4]; + WData/*127:0*/ __Vtemp1332[4]; + WData/*127:0*/ __Vtemp1333[4]; + WData/*127:0*/ __Vtemp1334[4]; + WData/*127:0*/ __Vtemp1335[4]; + WData/*127:0*/ __Vtemp1336[4]; + WData/*127:0*/ __Vtemp1337[4]; + WData/*127:0*/ __Vtemp1338[4]; + WData/*127:0*/ __Vtemp986[4]; + WData/*127:0*/ __Vtemp987[4]; + WData/*127:0*/ __Vtemp988[4]; + WData/*127:0*/ __Vtemp989[4]; + WData/*127:0*/ __Vtemp990[4]; + WData/*127:0*/ __Vtemp991[4]; + WData/*127:0*/ __Vtemp992[4]; + WData/*127:0*/ __Vtemp993[4]; + WData/*223:0*/ __Vtemp994[7]; + WData/*127:0*/ __Vtemp995[4]; + WData/*127:0*/ __Vtemp1000[4]; + WData/*127:0*/ __Vtemp1006[4]; + WData/*127:0*/ __Vtemp1007[4]; + WData/*127:0*/ __Vtemp1010[4]; + WData/*127:0*/ __Vtemp1011[4]; + WData/*127:0*/ __Vtemp1012[4]; + WData/*127:0*/ __Vtemp1014[4]; + WData/*127:0*/ __Vtemp1019[4]; + WData/*127:0*/ __Vtemp1025[4]; + WData/*127:0*/ __Vtemp1026[4]; + WData/*127:0*/ __Vtemp1029[4]; + WData/*127:0*/ __Vtemp1030[4]; + WData/*127:0*/ __Vtemp1031[4]; + WData/*127:0*/ __Vtemp1033[4]; + WData/*127:0*/ __Vtemp1038[4]; + WData/*127:0*/ __Vtemp1044[4]; + WData/*127:0*/ __Vtemp1045[4]; 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+ vcdp->fullBit(c+49,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)))); + vcdp->fullBit(c+57,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)))); + vcdp->fullBus(c+65,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+73,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U)))); + vcdp->fullBit(c+81,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 1U)))); + vcdp->fullBit(c+89,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 1U)))); + vcdp->fullBus(c+97,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+105,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U)))); + vcdp->fullBit(c+113,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 2U)))); + vcdp->fullBit(c+121,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 2U)))); + vcdp->fullBus(c+129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+137,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U)))); + vcdp->fullBit(c+145,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 3U)))); + vcdp->fullBit(c+153,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 3U)))); + vcdp->fullBus(c+161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+169,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 4U)))); + vcdp->fullBit(c+177,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 4U)))); + vcdp->fullBit(c+185,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 4U)))); + vcdp->fullBus(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+201,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 5U)))); + vcdp->fullBit(c+209,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 5U)))); + vcdp->fullBit(c+217,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 5U)))); + vcdp->fullBus(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+233,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 6U)))); + vcdp->fullBit(c+241,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 6U)))); + vcdp->fullBit(c+249,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 6U)))); + vcdp->fullBus(c+257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid),4); + vcdp->fullBit(c+265,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 7U)))); + vcdp->fullBit(c+273,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) + >> 7U)))); + vcdp->fullBit(c+281,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) + >> 7U)))); + vcdp->fullBus(c+289,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),8); + vcdp->fullBit(c+297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); + vcdp->fullBit(c+305,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); + vcdp->fullBit(c+313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+401,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+1057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+1065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+1073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+1081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+1089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+1097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+1113,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+1121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+1161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+1169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+1249,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+1257,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+1265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+1273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+1281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+1289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+1305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+1313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+1353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+1361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+1441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+1449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+1457,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+1465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+1473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+1497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+1505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+1545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+1553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+1633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+1641,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+1649,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+1657,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+1665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+1673,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); + vcdp->fullBit(c+1689,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+1697,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); + vcdp->fullBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+1745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+1825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+1833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+1841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+1849,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U + != + (0xffU + & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); + vcdp->fullBit(c+1857,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1865,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); + vcdp->fullBit(c+1873,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+1881,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1889,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1897,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 1U))))); + vcdp->fullBit(c+1905,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+1913,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1921,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1929,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 2U))))); + vcdp->fullBit(c+1937,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+1945,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1953,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1961,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 3U))))); + vcdp->fullBit(c+1969,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+1977,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1985,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1993,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 4U))))); + vcdp->fullBit(c+2001,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+2009,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+2017,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+2025,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 5U))))); + vcdp->fullBit(c+2033,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+2041,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+2049,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+2057,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 6U))))); + vcdp->fullBit(c+2065,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+2073,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+2081,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+2089,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) + >> 7U))))); + vcdp->fullBit(c+2097,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+2105,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+2113,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),8); + vcdp->fullBus(c+2121,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),8); + vcdp->fullBus(c+2129,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),16); + vcdp->fullArray(c+2137,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),256); + vcdp->fullArray(c+2201,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),336); + vcdp->fullBus(c+2289,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),8); + vcdp->fullArray(c+2297,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),224); + vcdp->fullBus(c+2353,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),8); + vcdp->fullBus(c+2361,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),8); + vcdp->fullArray(c+2369,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),128); + vcdp->fullArray(c+2401,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),224); + vcdp->fullArray(c+2457,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),1024); + vcdp->fullBus(c+2713,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),8); + vcdp->fullBus(c+2721,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),8); + vcdp->fullArray(c+2729,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),224); + vcdp->fullBus(c+2785,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+2801,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+2817,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+2833,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+2841,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp986[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp986[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp986[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp986[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+2849,(__Vtemp986),128); + vcdp->fullBit(c+2881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+2889,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+2897,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+2913,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+2929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+2937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+2945,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+2953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp987[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp987[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp987[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp987[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+2961,(__Vtemp987),128); + vcdp->fullBit(c+2993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+3001,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+3009,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+3025,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+3041,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+3057,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+3065,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp988[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp988[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp988[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp988[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+3073,(__Vtemp988),128); + vcdp->fullBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+3113,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+3121,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+3137,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+3153,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+3169,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+3177,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp989[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp989[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp989[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp989[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+3185,(__Vtemp989),128); + vcdp->fullBit(c+3217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+3225,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+3233,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+3241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+3249,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+3265,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+3273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+3281,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+3289,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp990[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp990[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp990[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp990[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+3297,(__Vtemp990),128); + vcdp->fullBit(c+3329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+3337,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+3345,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+3361,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+3377,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+3385,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+3393,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+3401,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp991[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp991[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp991[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp991[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+3409,(__Vtemp991),128); + vcdp->fullBit(c+3441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+3449,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+3457,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+3473,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+3489,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+3497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+3505,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+3513,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp992[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp992[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp992[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp992[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+3521,(__Vtemp992),128); + vcdp->fullBit(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+3561,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+3569,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))),2); + vcdp->fullBus(c+3577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+3585,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); + vcdp->fullBit(c+3601,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)))))); + vcdp->fullBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+3617,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xbU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x15U)))),16); + vcdp->fullBus(c+3625,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 4U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1cU)))),25); + __Vtemp993[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp993[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp993[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp993[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->fullArray(c+3633,(__Vtemp993),128); + vcdp->fullBit(c+3665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+3673,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBit(c+3681,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); + vcdp->fullBit(c+3689,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vcdp->fullBus(c+3697,(((0xdfU >= (0xffU & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? (0xfffffffU & (((0U + == + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + ((IData)(1U) + + + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ + (7U + & (((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1cU) + * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) + : 0U)),28); + vcdp->fullBit(c+3705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+3713,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); + vcdp->fullBus(c+3721,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),3); + vcdp->fullBit(c+3729,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); + vcdp->fullBit(c+3737,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); + vcdp->fullBit(c+3745,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); + vcdp->fullBus(c+3753,((0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])),8); + __Vtemp994[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; + __Vtemp994[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; + __Vtemp994[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; + __Vtemp994[3U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]; + __Vtemp994[4U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]; + __Vtemp994[5U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]; + __Vtemp994[6U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]; + vcdp->fullArray(c+3761,(__Vtemp994),224); + vcdp->fullBus(c+3817,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),8); + vcdp->fullArray(c+3825,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),224); + vcdp->fullBus(c+3881,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),8); + vcdp->fullBit(c+3889,((1U & ((~ (IData)((0U + != + (0xffU + & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+3897,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+3905,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),3); + vcdp->fullBit(c+3913,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); + vcdp->fullArray(c+3921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),232); + vcdp->fullArray(c+3985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),232); + vcdp->fullBit(c+4049,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); + vcdp->fullBus(c+4057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->fullBus(c+4065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBus(c+4073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->fullBus(c+4081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+4089,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); + vcdp->fullQuad(c+4121,(((0x14fU >= (0x1ffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (VL_ULL(0x3ffffffffff) + & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? VL_ULL(0) + : ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(2U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((IData)(0x40U) + - (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))])) + << ((0U + == + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0x20U + : ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (0xfU + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))])) + >> (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) + : VL_ULL(0))),42); + vcdp->fullBus(c+4137,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),8); + vcdp->fullBus(c+4145,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),3); + vcdp->fullBit(c+4153,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); + vcdp->fullBus(c+4161,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->fullBus(c+4169,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) + | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),8); + vcdp->fullBus(c+4177,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),8); + vcdp->fullBus(c+4185,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBus(c+4193,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),3); + vcdp->fullBit(c+4201,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); + vcdp->fullBus(c+4209,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),8); + vcdp->fullBus(c+4217,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBit(c+4225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+4233,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+4241,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+4249,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+4257,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+4265,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp995[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp995[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp995[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp995[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+4273,(__Vtemp995),128); + vcdp->fullBit(c+4305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+4313,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+4321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+4329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+4337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+4345,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+4353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+4361,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+4369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+4393,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+4401,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+4417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+4449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+4457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+4513,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+4521,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+4529,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+4537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1000[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1000[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1000[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1000[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+4545,(__Vtemp1000),128); + vcdp->fullQuad(c+4577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+4601,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+4609,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+4617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+4625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+4633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+4641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+4649,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+4665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+4713,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1006[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1006[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1006[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1006[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+4721,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1006[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1006[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1007[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1007[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1007[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1007[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+4729,(__Vtemp1007),128); + vcdp->fullBus(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+4777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+4785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+4793,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+4809,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+4817,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+4825,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+4833,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+4849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+4857,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+4865,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+4873,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+4881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+4889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+4897,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+4913,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+4921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+4929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+4937,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+4953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+4969,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+4985,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+5017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+5025,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+5041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+5105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+5113,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+5121,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+5129,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1010[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1010[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1010[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1010[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+5137,(__Vtemp1010),120); + __Vtemp1011[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1011[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1011[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1011[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+5169,(__Vtemp1011),128); + vcdp->fullQuad(c+5201,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+5217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+5225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+5233,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+5241,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+5321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+5329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+5337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+5345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+5409,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+5417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+5425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1012[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1012[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1012[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1012[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+5433,(__Vtemp1012),128); + vcdp->fullBus(c+5465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+5489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+5497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+5505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+5537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+5545,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1013[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1013[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1013[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1013[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+5569,(__Vtemp1013),128); + vcdp->fullBit(c+5601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+5625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+5681,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+5689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+5697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+5705,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+5713,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+5729,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+5737,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5745,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5753,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5761,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+5769,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+5777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+5825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+5905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+5913,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+5921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+5929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+5937,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+5945,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+5953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+5961,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+5969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+6001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+6025,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+6153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+6161,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+6169,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+6177,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+6185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+6193,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1014[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1014[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1014[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1014[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+6201,(__Vtemp1014),128); + vcdp->fullBit(c+6233,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+6241,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+6249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+6257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+6265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+6273,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+6281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+6289,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+6297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+6321,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+6329,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+6345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+6377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+6385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+6441,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+6449,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+6457,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+6465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1019[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1019[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1019[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1019[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+6473,(__Vtemp1019),128); + vcdp->fullQuad(c+6505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+6529,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+6537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+6545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+6553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+6561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+6569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+6577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+6593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+6641,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1025[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1025[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1025[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1025[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+6649,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1025[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1025[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1026[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1026[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1026[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1026[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+6657,(__Vtemp1026),128); + vcdp->fullBus(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+6705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+6713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+6721,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+6737,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+6745,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+6753,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+6761,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+6777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+6785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+6793,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+6801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+6809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+6817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+6825,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+6841,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+6849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+6857,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+6865,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+6881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+6897,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+6913,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+6945,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+6953,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+6969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+7033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+7041,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+7049,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+7057,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1029[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1029[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1029[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1029[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+7065,(__Vtemp1029),120); + __Vtemp1030[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1030[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1030[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1030[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+7097,(__Vtemp1030),128); + vcdp->fullQuad(c+7129,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+7145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+7153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+7161,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+7169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+7249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+7257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+7265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+7273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+7337,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+7345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+7353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1031[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1031[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1031[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1031[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+7361,(__Vtemp1031),128); + vcdp->fullBus(c+7393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+7417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+7425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+7433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+7465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+7473,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1032[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1032[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1032[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1032[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+7497,(__Vtemp1032),128); + vcdp->fullBit(c+7529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+7553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+7609,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+7617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+7625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+7633,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+7641,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+7657,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+7665,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7673,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7681,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7689,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+7697,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+7753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+7833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+7841,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+7849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+7857,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+7865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+7873,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+7881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+7889,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+7897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+7929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+7953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+7961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+8017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+8073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+8081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+8089,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+8097,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+8105,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+8113,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+8121,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1033[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1033[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1033[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1033[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+8129,(__Vtemp1033),128); + vcdp->fullBit(c+8161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+8169,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+8177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+8185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+8193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+8201,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+8209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+8217,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+8225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+8233,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+8241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+8249,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+8257,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+8265,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+8273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+8305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+8313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+8369,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+8377,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+8385,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+8393,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1038[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1038[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1038[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1038[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+8401,(__Vtemp1038),128); + vcdp->fullQuad(c+8433,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+8457,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+8465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+8473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+8481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+8489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+8497,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+8505,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+8521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+8569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1044[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1044[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1044[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1044[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+8577,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1044[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1044[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1045[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1045[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1045[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1045[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+8585,(__Vtemp1045),128); + vcdp->fullBus(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+8633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+8641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+8649,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+8665,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+8673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+8681,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+8689,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+8705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+8713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+8721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+8729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+8737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+8745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+8753,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+8769,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+8777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+8785,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+8793,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+8809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+8825,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+8841,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+8873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+8881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+8897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+8961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+8969,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+8977,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+8985,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1048[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1048[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1048[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1048[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+8993,(__Vtemp1048),120); + __Vtemp1049[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1049[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1049[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1049[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+9025,(__Vtemp1049),128); + vcdp->fullQuad(c+9057,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+9073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+9081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+9089,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+9097,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+9177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+9185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+9193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+9201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+9265,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+9273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+9281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1050[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1050[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1050[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1050[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+9289,(__Vtemp1050),128); + vcdp->fullBus(c+9321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+9345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+9353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+9361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+9393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+9401,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1051[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1051[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1051[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1051[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+9425,(__Vtemp1051),128); + vcdp->fullBit(c+9457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+9481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+9537,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+9545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+9553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+9561,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+9569,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+9585,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+9593,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9601,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9609,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9617,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9625,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+9681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+9761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+9769,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+9777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+9785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+9793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+9801,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+9809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+9817,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+9825,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+9833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+9857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+9881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+9889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+9945,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+10001,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+10009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+10017,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+10025,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+10033,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+10041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+10049,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1052[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1052[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1052[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1052[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+10057,(__Vtemp1052),128); + vcdp->fullBit(c+10089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+10097,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+10105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+10113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+10121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+10129,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+10137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+10145,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+10153,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+10161,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+10169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+10177,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+10185,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+10193,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+10201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+10209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+10217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+10225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+10233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+10241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+10249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+10257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+10265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+10273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+10281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+10289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+10297,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+10305,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+10313,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+10321,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1057[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1057[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1057[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1057[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+10329,(__Vtemp1057),128); + vcdp->fullQuad(c+10361,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))),49); + vcdp->fullBit(c+10377,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+10385,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+10393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+10401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+10409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+10417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+10425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+10433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+10449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+10481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+10489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+10497,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1063[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1063[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1063[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1063[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+10505,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1063[ + ((IData)(1U) + + (3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1063[(3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1064[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1064[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1064[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1064[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+10513,(__Vtemp1064),128); + vcdp->fullBus(c+10545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+10553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+10561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+10569,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+10577,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+10593,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+10601,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 6U))))); + vcdp->fullBus(c+10609,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+10617,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+10625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+10633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+10641,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+10649,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+10657,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+10665,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+10673,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+10681,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+10689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+10697,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+10705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+10713,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+10721,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+10729,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+10737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+10745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+10753,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+10761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+10769,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+10777,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+10785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+10793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+10801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+10809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+10817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+10825,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+10841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+10849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+10889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+10897,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+10905,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+10913,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1067[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1067[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1067[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1067[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+10921,(__Vtemp1067),120); + __Vtemp1068[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1068[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1068[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1068[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+10953,(__Vtemp1068),128); + vcdp->fullQuad(c+10985,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+11001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+11009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+11017,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) + & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+11025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+11105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+11113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+11121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+11129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+11193,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+11201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+11209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1069[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1069[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1069[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1069[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+11217,(__Vtemp1069),128); + vcdp->fullBus(c+11249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+11257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+11265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+11273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+11281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+11289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+11321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+11329,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+11337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+11345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1070[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1070[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1070[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1070[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+11353,(__Vtemp1070),128); + vcdp->fullBit(c+11385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+11393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+11401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+11409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+11441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+11449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+11457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+11465,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+11473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+11481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+11489,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+11497,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+11505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+11513,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+11521,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+11529,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+11537,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+11545,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+11553,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+11561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+11609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+11689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+11697,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+11705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+11713,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+11721,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+11729,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+11737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+11745,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+11753,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+11761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+11785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+11809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+11817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+11873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+11929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+11937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+11945,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+11953,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+11961,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+11969,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+11977,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1071[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1071[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1071[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1071[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+11985,(__Vtemp1071),128); + vcdp->fullBit(c+12017,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+12025,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+12033,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+12041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+12049,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+12057,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+12065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+12073,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+12081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+12089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+12097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+12105,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+12113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+12121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+12129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+12137,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+12145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+12153,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+12161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+12169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+12177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+12185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+12193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+12201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+12209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+12217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+12225,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+12233,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+12241,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+12249,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1076[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1076[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1076[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1076[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+12257,(__Vtemp1076),128); + vcdp->fullQuad(c+12289,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))),49); + vcdp->fullBit(c+12305,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+12313,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+12321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+12329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+12337,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+12345,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+12353,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+12361,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+12377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+12409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+12417,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+12425,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1082[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1082[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1082[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1082[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+12433,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1082[ + ((IData)(1U) + + (3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1082[(3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1083[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1083[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1083[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1083[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+12441,(__Vtemp1083),128); + vcdp->fullBus(c+12473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+12481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+12489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+12497,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+12505,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+12521,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+12529,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 6U))))); + vcdp->fullBus(c+12537,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+12545,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+12553,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+12561,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+12569,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+12577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+12585,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+12593,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+12601,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+12609,((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+12617,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+12625,((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+12633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+12641,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+12649,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+12657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+12665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+12673,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+12681,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+12689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+12697,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+12705,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+12713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+12721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+12729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+12737,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+12745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+12753,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+12769,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+12777,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+12817,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+12825,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+12833,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+12841,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1086[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1086[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1086[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1086[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+12849,(__Vtemp1086),120); + __Vtemp1087[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1087[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1087[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1087[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+12881,(__Vtemp1087),128); + vcdp->fullQuad(c+12913,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+12929,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+12937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+12945,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) + & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+12953,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+13033,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+13041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+13049,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+13057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+13121,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+13129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+13137,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1088[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1088[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1088[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1088[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+13145,(__Vtemp1088),128); + vcdp->fullBus(c+13177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+13185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+13193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+13201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+13209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+13217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+13249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+13257,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+13265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+13273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1089[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1089[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1089[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1089[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+13281,(__Vtemp1089),128); + vcdp->fullBit(c+13313,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+13321,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+13329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+13337,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+13369,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+13377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+13385,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+13393,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+13401,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+13409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+13417,((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+13425,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+13433,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+13441,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+13449,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+13457,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+13465,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+13473,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+13481,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+13489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+13537,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+13617,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+13625,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+13633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+13649,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+13657,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+13673,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+13681,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+13713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+13737,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+13745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+13801,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+13857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+13865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+13873,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+13881,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+13889,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+13897,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+13905,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1090[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1090[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1090[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1090[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+13913,(__Vtemp1090),128); + vcdp->fullBit(c+13945,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+13953,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+13961,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+13969,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+13977,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+13985,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+13993,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+14001,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+14009,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+14017,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+14025,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+14033,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+14041,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+14049,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+14121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+14129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+14137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+14145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+14153,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+14161,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+14169,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+14177,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1095[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1095[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1095[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1095[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+14185,(__Vtemp1095),128); + vcdp->fullQuad(c+14217,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))),49); + vcdp->fullBit(c+14233,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+14241,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+14249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+14257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+14265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+14273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+14281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+14289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+14305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+14337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+14345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+14353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1101[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1101[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1101[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1101[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+14361,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1101[ + ((IData)(1U) + + (3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1101[(3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1102[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1102[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1102[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1102[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+14369,(__Vtemp1102),128); + vcdp->fullBus(c+14401,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+14409,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+14417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+14425,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+14433,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+14449,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+14457,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 6U))))); + vcdp->fullBus(c+14465,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+14473,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+14481,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+14489,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+14497,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+14505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+14513,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+14521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+14529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+14537,((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+14545,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+14553,((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+14561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+14569,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+14577,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+14585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+14593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+14601,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+14609,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+14617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+14625,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+14633,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+14641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+14649,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+14657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+14665,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+14673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+14681,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+14697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+14705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+14745,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+14753,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+14761,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+14769,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1105[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1105[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1105[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1105[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+14777,(__Vtemp1105),120); + __Vtemp1106[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1106[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1106[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1106[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+14809,(__Vtemp1106),128); + vcdp->fullQuad(c+14841,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+14857,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+14873,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) + & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+14881,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+14961,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+14969,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+14977,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+14985,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+15049,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+15057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+15065,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1107[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1107[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1107[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1107[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+15073,(__Vtemp1107),128); + vcdp->fullBus(c+15105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+15113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+15121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+15129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+15137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+15145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+15177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+15185,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+15193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+15201,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1108[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1108[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1108[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1108[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+15209,(__Vtemp1108),128); + vcdp->fullBit(c+15241,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+15249,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+15257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+15265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+15297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+15305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+15313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+15321,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+15329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+15337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+15345,((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+15353,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+15361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+15369,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+15377,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+15385,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+15393,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+15401,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+15409,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+15417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+15465,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+15545,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+15553,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+15585,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+15601,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+15609,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+15617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+15641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+15673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+15729,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+15785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+15793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+15801,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+15809,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+15817,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+15825,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+15833,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1109[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1109[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1109[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1109[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+15841,(__Vtemp1109),128); + vcdp->fullBit(c+15873,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+15881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+15889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+15897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+15905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+15913,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+15921,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+15929,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+15937,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+15945,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+15953,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+15961,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+15969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+15977,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+15985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+15993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+16001,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+16009,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+16017,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+16025,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+16033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+16041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+16049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+16057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+16065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+16073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+16081,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+16089,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+16097,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+16105,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1114[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1114[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1114[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1114[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+16113,(__Vtemp1114),128); + vcdp->fullQuad(c+16145,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))),49); + vcdp->fullBit(c+16161,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+16169,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+16177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+16185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+16193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+16201,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+16209,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+16217,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+16233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+16265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+16273,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+16281,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1120[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1120[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1120[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1120[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+16289,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1120[ + ((IData)(1U) + + (3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1120[(3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1121[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1121[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1121[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1121[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+16297,(__Vtemp1121),128); + vcdp->fullBus(c+16329,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+16337,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+16345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+16353,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+16361,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+16377,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+16385,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 6U))))); + vcdp->fullBus(c+16393,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+16401,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+16409,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+16417,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+16425,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+16433,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+16441,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+16449,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+16457,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+16465,((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+16473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+16481,((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+16489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+16497,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+16505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+16513,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+16521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+16529,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+16537,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+16545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+16553,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+16561,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+16569,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+16577,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+16585,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+16593,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+16601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+16609,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+16625,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+16633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+16673,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+16681,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+16689,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+16697,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1124[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1124[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1124[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1124[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+16705,(__Vtemp1124),120); + __Vtemp1125[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1125[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1125[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1125[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+16737,(__Vtemp1125),128); + vcdp->fullQuad(c+16769,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+16785,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+16793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+16801,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) + & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+16809,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+16889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+16897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+16905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+16913,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+16977,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+16985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+16993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1126[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1126[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1126[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1126[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+17001,(__Vtemp1126),128); + vcdp->fullBus(c+17033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+17041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+17049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+17057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+17065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+17073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+17105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+17113,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+17121,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+17129,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1127[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1127[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1127[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1127[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+17137,(__Vtemp1127),128); + vcdp->fullBit(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+17185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+17193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+17225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+17233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+17241,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+17249,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+17257,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+17265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+17273,((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+17281,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+17289,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+17297,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+17305,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+17313,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+17321,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+17329,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+17337,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+17345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+17393,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+17473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+17481,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+17489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+17497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+17505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+17513,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+17529,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+17537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+17593,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+17601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+17657,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+17713,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+17721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+17729,((0x1ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),25); + vcdp->fullBit(c+17737,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->fullBus(c+17745,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+17753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+17761,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); + __Vtemp1128[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp1128[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp1128[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp1128[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+17769,(__Vtemp1128),128); + vcdp->fullBit(c+17801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+17809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+17817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+17825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+17833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+17841,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->fullBus(c+17849,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+17857,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->fullBit(c+17865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+17873,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+17881,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+17889,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+17897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x1ffffffU & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+17905,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+17937,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+17945,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+17953,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+17961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+17969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+17977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+17985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+17993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+18001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+18009,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+18017,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x1ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x18fU + >= + (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x1ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x1ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 5U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x1ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),25); + vcdp->fullBus(c+18025,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & + ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+18033,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp1133[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp1133[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp1133[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp1133[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+18041,(__Vtemp1133),128); + vcdp->fullQuad(c+18073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) + : VL_ULL(0))))),49); + vcdp->fullBit(c+18089,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+18097,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+18105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+18113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+18121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0]),25); + vcdp->fullBus(c+18129,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+18137,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+18145,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+18161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+18193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+18201,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+18209,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp1139[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1139[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1139[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1139[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullBus(c+18217,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp1139[ + ((IData)(1U) + + (3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp1139[(3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp1140[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp1140[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp1140[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp1140[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+18225,(__Vtemp1140),128); + vcdp->fullBus(c+18257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),21); + vcdp->fullBit(c+18265,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+18273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+18281,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+18289,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+18305,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+18313,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 6U))))); + vcdp->fullBus(c+18321,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+18329,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+18337,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+18345,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+18353,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+18361,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+18369,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+18377,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+18385,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+18393,((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+18401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]),25); + vcdp->fullBit(c+18409,((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+18417,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+18425,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x1ffffffU & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == (0x1ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+18433,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x1ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+18441,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+18449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+18457,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+18465,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+18473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+18481,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & + (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+18489,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+18497,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+18505,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+18513,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+18521,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 5U)))); + vcdp->fullBit(c+18529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+18537,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); + vcdp->fullBit(c+18553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+18561,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); + vcdp->fullBit(c+18601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+18609,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+18617,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+18625,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp1143[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp1143[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp1143[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp1143[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+18633,(__Vtemp1143),120); + __Vtemp1144[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp1144[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp1144[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp1144[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+18665,(__Vtemp1144),128); + vcdp->fullQuad(c+18697,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+18713,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+18721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+18729,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) + & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+18737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+18817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+18825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+18833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+18841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); + vcdp->fullBus(c+18905,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])),4); + vcdp->fullBit(c+18913,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+18921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp1145[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp1145[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp1145[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp1145[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+18929,(__Vtemp1145),128); + vcdp->fullBus(c+18961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+18969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+18977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+18985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+18993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); + vcdp->fullArray(c+19001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+19033,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBit(c+19041,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) + >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U]))))); + vcdp->fullBus(c+19049,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+19057,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])]),21); + __Vtemp1146[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][0U]; + __Vtemp1146[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][1U]; + __Vtemp1146[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][2U]; + __Vtemp1146[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U])][3U]; + vcdp->fullArray(c+19065,(__Vtemp1146),128); + vcdp->fullBit(c+19097,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+19105,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+19113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+19121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+19153,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+19161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+19169,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+19177,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 + [0U] >> 4U))),21); + vcdp->fullBus(c+19185,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+19193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+19201,((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+19209,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+19217,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+19225,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+19233,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+19241,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+19249,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+19257,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+19265,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+19273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); + vcdp->fullArray(c+19321,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+19401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+19409,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+19417,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+19425,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+19433,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+19441,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+19449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+19457,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+19465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+19473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+19497,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+19521,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+19529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); + vcdp->fullArray(c+19585,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); + vcdp->fullBit(c+19641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+19649,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19657,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19665,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19673,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19681,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19689,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19697,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19713,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19721,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19729,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19737,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19745,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19753,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19761,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19769,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19777,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19785,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19793,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19801,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19817,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19825,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19833,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19841,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19849,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19857,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19865,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19873,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19889,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19897,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19905,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19913,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19921,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19929,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19937,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+19945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU)))),25); + vcdp->fullBit(c+19961,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+19969,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+19977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); + vcdp->fullBit(c+19985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+19993,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); + vcdp->fullBit(c+20001,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBus(c+20009,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r)),28); + vcdp->fullBit(c+20017,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+20025,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+20033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->fullBus(c+20041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[0]),28); + vcdp->fullBus(c+20042,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[1]),28); + vcdp->fullBus(c+20057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),28); + vcdp->fullBus(c+20065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),28); + vcdp->fullBit(c+20073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)); + vcdp->fullBit(c+20081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)); + vcdp->fullBit(c+20089,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)); + vcdp->fullBit(c+20097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+20105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),8); + vcdp->fullArray(c+20113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),224); + vcdp->fullBit(c+20169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+20177,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))))); + vcdp->fullBus(c+20185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),4); + vcdp->fullArray(c+20193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),232); + vcdp->fullArray(c+20201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),232); + vcdp->fullArray(c+20209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),232); + vcdp->fullArray(c+20217,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),232); + vcdp->fullArray(c+20225,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[4]),232); + vcdp->fullArray(c+20233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[5]),232); + vcdp->fullArray(c+20241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[6]),232); + vcdp->fullArray(c+20249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[7]),232); + vcdp->fullArray(c+20705,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),232); + vcdp->fullArray(c+20769,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),232); + vcdp->fullBus(c+20833,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+20841,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+20849,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+20857,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+20865,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),8); + vcdp->fullBit(c+20873,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); + vcdp->fullBus(c+20881,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),8); + vcdp->fullBit(c+20889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+20897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+20905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+20913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+20921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+20945,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+20953,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+20961,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+20969,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+20977,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+20985,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+20993,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+21009,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+21017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+21025,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+21033,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+21041,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+21057,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+21065,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+21073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+21081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+21097,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+21105,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1154[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1154[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1154[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1154[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+21113,(__Vtemp1154),128); + vcdp->fullBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+21153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+21161,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+21169,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+21185,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+21193,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+21201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+21209,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+21217,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+21225,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+21233,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+21241,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+21249,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21257,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+21265,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+21281,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+21289,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+21297,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+21305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+21313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+21315,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+21317,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+21319,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->fullQuad(c+21321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->fullQuad(c+21323,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->fullQuad(c+21325,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->fullQuad(c+21327,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->fullQuad(c+21329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->fullQuad(c+21331,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->fullQuad(c+21333,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->fullQuad(c+21335,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); 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+ vcdp->fullBit(c+22489,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+22497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->fullArray(c+22505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+22515,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+22525,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+22535,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+22545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->fullArray(c+22555,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->fullArray(c+22565,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->fullArray(c+22575,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->fullArray(c+23145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+23225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+23305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+23313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); 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+ vcdp->fullArray(c+23401,(__Vtemp1155),128); + __Vtemp1156[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][0U]; + __Vtemp1156[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][1U]; + __Vtemp1156[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][2U]; + __Vtemp1156[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][3U]; + vcdp->fullArray(c+23433,(__Vtemp1156),128); + __Vtemp1157[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][0U]; + __Vtemp1157[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][1U]; + __Vtemp1157[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][2U]; 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+ __Vtemp1159[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [4U][2U]; + __Vtemp1159[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [4U][3U]; + vcdp->fullArray(c+23529,(__Vtemp1159),128); + __Vtemp1160[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [5U][0U]; + __Vtemp1160[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [5U][1U]; + __Vtemp1160[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [5U][2U]; + __Vtemp1160[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [5U][3U]; + vcdp->fullArray(c+23561,(__Vtemp1160),128); + __Vtemp1161[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [6U][0U]; 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+ vcdp->fullBus(c+24817,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+24825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+24833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+24841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+24849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+24857,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+24865,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+24873,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->fullArray(c+24881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+24884,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+24887,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+24890,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+24893,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->fullArray(c+24896,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->fullArray(c+24899,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->fullArray(c+24902,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->fullArray(c+25073,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+25097,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+25121,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+25129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+25137,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+25145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+25153,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+25161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->fullArray(c+25168,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+25175,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+25182,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+25385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+25441,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+25497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+25505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+25513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+25521,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+25529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+25537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+25545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+25553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+25561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+25569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+25585,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+25593,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+25601,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+25609,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+25617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+25625,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+25633,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+25649,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+25657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+25665,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+25673,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+25681,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+25697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+25705,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+25713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+25721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+25729,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+25737,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+25745,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1178[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1178[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1178[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1178[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+25753,(__Vtemp1178),128); + vcdp->fullBit(c+25785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+25793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+25801,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+25809,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+25825,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+25833,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+25841,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+25849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+25857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+25865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+25873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+25881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+25889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+25897,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+25905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+25913,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+25921,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+25929,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+25937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+25945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+25953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+25955,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+25957,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+25959,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->fullQuad(c+25961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->fullQuad(c+25963,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->fullQuad(c+25965,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->fullQuad(c+25967,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->fullQuad(c+25969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->fullQuad(c+25971,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->fullQuad(c+25973,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->fullQuad(c+25975,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->fullQuad(c+25977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->fullQuad(c+25979,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->fullQuad(c+25981,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->fullQuad(c+25983,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->fullQuad(c+26209,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->fullQuad(c+26225,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->fullBus(c+26241,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+26249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+26257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+26265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+26273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->fullArray(c+26281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->fullArray(c+26286,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->fullArray(c+26291,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->fullArray(c+26296,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->fullArray(c+26301,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->fullArray(c+26306,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->fullArray(c+26311,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->fullArray(c+26316,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->fullArray(c+26321,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->fullArray(c+26326,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->fullArray(c+26331,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->fullArray(c+26336,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->fullArray(c+26341,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->fullArray(c+26346,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->fullArray(c+26351,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->fullArray(c+26356,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->fullArray(c+26921,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->fullArray(c+26961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->fullBus(c+27001,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+27009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+27017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+27025,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+27033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+27041,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+27049,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+27057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+27089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+27121,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+27129,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+27137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->fullArray(c+27145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+27155,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+27165,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+27175,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+27185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->fullArray(c+27195,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->fullArray(c+27205,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->fullArray(c+27215,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->fullArray(c+27785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+27865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+27945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+27953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+27961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+27969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullArray(c+27977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); + __Vtemp1179[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][0U]; + __Vtemp1179[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][1U]; + __Vtemp1179[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][2U]; + __Vtemp1179[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][3U]; 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+ vcdp->fullBus(c+28801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->fullBus(c+28809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->fullBus(c+28817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->fullBus(c+28825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+28833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+28841,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->fullArray(c+28889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+28969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+28972,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+28975,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+28978,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+28981,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+28984,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+28987,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+28990,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+28993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+28996,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+28999,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+29002,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+29005,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+29008,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+29011,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+29014,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+29353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->fullBus(c+29457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+29465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+29473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+29481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+29489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+29497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+29505,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+29513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->fullArray(c+29521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+29524,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+29527,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+29530,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+29533,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->fullArray(c+29536,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->fullArray(c+29539,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->fullArray(c+29542,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->fullArray(c+29713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+29737,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+29761,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+29769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+29777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+29785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+29793,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+29801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->fullArray(c+29808,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+29815,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+29822,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+30025,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+30081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+30137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+30145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+30153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+30161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+30169,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+30177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+30185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+30193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+30201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+30209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+30225,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+30233,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+30241,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+30249,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+30257,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+30265,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+30273,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+30289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+30297,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+30305,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+30313,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+30321,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+30337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+30345,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+30353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+30361,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+30369,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+30377,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+30385,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1202[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1202[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1202[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1202[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+30393,(__Vtemp1202),128); + vcdp->fullBit(c+30425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+30433,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+30441,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+30449,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+30465,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+30473,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+30481,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+30489,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+30497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+30505,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+30513,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+30521,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+30529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+30537,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+30545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+30553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+30561,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+30569,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+30577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+30585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+30593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+30595,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+30597,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+30599,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->fullQuad(c+30601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->fullQuad(c+30603,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->fullQuad(c+30605,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->fullQuad(c+30607,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->fullQuad(c+30609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->fullQuad(c+30611,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->fullQuad(c+30613,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->fullQuad(c+30615,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->fullQuad(c+30617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->fullQuad(c+30619,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->fullQuad(c+30621,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->fullQuad(c+30623,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->fullQuad(c+30849,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->fullQuad(c+30865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->fullBus(c+30881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+30889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+30897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+30905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+30913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->fullArray(c+30921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->fullArray(c+30926,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->fullArray(c+30931,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->fullArray(c+30936,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->fullArray(c+30941,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->fullArray(c+30946,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->fullArray(c+30951,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->fullArray(c+30956,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->fullArray(c+30961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->fullArray(c+30966,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->fullArray(c+30971,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->fullArray(c+30976,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->fullArray(c+30981,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->fullArray(c+30986,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->fullArray(c+30991,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->fullArray(c+30996,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->fullArray(c+31561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->fullArray(c+31601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->fullBus(c+31641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+31649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+31657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+31665,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+31673,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+31681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+31689,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+31697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+31729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+31761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+31769,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+31777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->fullArray(c+31785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+31795,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+31805,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+31815,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+31825,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->fullArray(c+31835,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->fullArray(c+31845,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->fullArray(c+31855,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->fullArray(c+32425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+32505,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+32585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+32593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); 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+ vcdp->fullBus(c+33203,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); + vcdp->fullBus(c+33204,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); + vcdp->fullBus(c+33205,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); + vcdp->fullBus(c+33206,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); + vcdp->fullBus(c+33207,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); + vcdp->fullBus(c+33208,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); + vcdp->fullBus(c+33321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0U]),16); + vcdp->fullBus(c+33329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [1U]),16); + vcdp->fullBus(c+33337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [2U]),16); + vcdp->fullBus(c+33345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [3U]),16); + vcdp->fullBus(c+33353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [4U]),16); + vcdp->fullBus(c+33361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [5U]),16); + vcdp->fullBus(c+33369,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [6U]),16); + vcdp->fullBus(c+33377,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [7U]),16); + vcdp->fullBus(c+33385,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [8U]),16); + vcdp->fullBus(c+33393,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [9U]),16); + vcdp->fullBus(c+33401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xaU]),16); + vcdp->fullBus(c+33409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xbU]),16); + vcdp->fullBus(c+33417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xcU]),16); + vcdp->fullBus(c+33425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xdU]),16); + vcdp->fullBus(c+33433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xeU]),16); + vcdp->fullBus(c+33441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->fullBus(c+33449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->fullBus(c+33457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->fullBus(c+33465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+33473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+33481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->fullArray(c+33529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+33609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+33612,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+33615,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+33618,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+33621,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+33624,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+33627,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+33630,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+33633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+33636,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+33639,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+33642,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+33645,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+33648,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+33651,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+33654,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+33993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->fullBus(c+34097,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+34105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+34113,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+34121,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+34129,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+34137,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+34145,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+34153,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->fullArray(c+34161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+34164,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+34167,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+34170,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+34173,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->fullArray(c+34176,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->fullArray(c+34179,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->fullArray(c+34182,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->fullArray(c+34353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+34377,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+34401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+34409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+34417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+34425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+34433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+34441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->fullArray(c+34448,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+34455,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+34462,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+34665,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+34721,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+34777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+34785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+34793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+34801,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+34809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+34817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+34825,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+34833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+34841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+34849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+34865,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+34873,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+34881,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+34889,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+34897,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+34905,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+34913,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+34929,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+34937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+34945,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+34953,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+34961,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+34977,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+34985,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+34993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+35001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+35009,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+35017,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+35025,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1226[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1226[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1226[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1226[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+35033,(__Vtemp1226),128); + vcdp->fullBit(c+35065,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+35073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+35081,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+35089,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+35105,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+35113,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+35121,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+35129,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+35137,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+35145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+35153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+35161,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+35169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+35177,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+35185,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+35193,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+35201,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+35209,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+35217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+35225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+35233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+35235,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+35237,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+35239,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->fullQuad(c+35241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->fullQuad(c+35243,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->fullQuad(c+35245,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->fullQuad(c+35247,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->fullQuad(c+35249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->fullQuad(c+35251,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->fullQuad(c+35253,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->fullQuad(c+35255,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->fullQuad(c+35257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->fullQuad(c+35259,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->fullQuad(c+35261,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->fullQuad(c+35263,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->fullQuad(c+35489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->fullQuad(c+35505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->fullBus(c+35521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+35529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+35537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+35545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+35553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->fullArray(c+35561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->fullArray(c+35566,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->fullArray(c+35571,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->fullArray(c+35576,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->fullArray(c+35581,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->fullArray(c+35586,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->fullArray(c+35591,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->fullArray(c+35596,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->fullArray(c+35601,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->fullArray(c+35606,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->fullArray(c+35611,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->fullArray(c+35616,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->fullArray(c+35621,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->fullArray(c+35626,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->fullArray(c+35631,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->fullArray(c+35636,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->fullArray(c+36201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->fullArray(c+36241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->fullBus(c+36281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+36289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+36297,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+36305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+36313,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+36321,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+36329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+36337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+36369,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+36401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+36409,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+36417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->fullArray(c+36425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+36435,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+36445,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+36455,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+36465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->fullArray(c+36475,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->fullArray(c+36485,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->fullArray(c+36495,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->fullArray(c+37065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+37145,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+37225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+37233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); 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+ __Vtemp1240[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][1U]; + __Vtemp1240[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][2U]; + __Vtemp1240[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][3U]; + vcdp->fullArray(c+37737,(__Vtemp1240),128); + __Vtemp1241[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][0U]; + __Vtemp1241[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][1U]; + __Vtemp1241[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][2U]; + __Vtemp1241[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][3U]; + vcdp->fullArray(c+37769,(__Vtemp1241),128); + __Vtemp1242[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][0U]; + __Vtemp1242[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][1U]; + __Vtemp1242[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][2U]; + __Vtemp1242[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][3U]; + vcdp->fullArray(c+37801,(__Vtemp1242),128); + vcdp->fullBus(c+37833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); + vcdp->fullBus(c+37834,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); + vcdp->fullBus(c+37835,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); + vcdp->fullBus(c+37836,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); + vcdp->fullBus(c+37837,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); + vcdp->fullBus(c+37838,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); + vcdp->fullBus(c+37839,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); + vcdp->fullBus(c+37840,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); + vcdp->fullBus(c+37841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); + vcdp->fullBus(c+37842,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); + vcdp->fullBus(c+37843,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); + vcdp->fullBus(c+37844,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); + vcdp->fullBus(c+37845,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); + vcdp->fullBus(c+37846,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); + vcdp->fullBus(c+37847,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); + vcdp->fullBus(c+37848,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); + vcdp->fullBus(c+37961,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0U]),16); + vcdp->fullBus(c+37969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [1U]),16); + vcdp->fullBus(c+37977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [2U]),16); + vcdp->fullBus(c+37985,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [3U]),16); + vcdp->fullBus(c+37993,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [4U]),16); + vcdp->fullBus(c+38001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [5U]),16); + vcdp->fullBus(c+38009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [6U]),16); + vcdp->fullBus(c+38017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [7U]),16); + vcdp->fullBus(c+38025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [8U]),16); + vcdp->fullBus(c+38033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [9U]),16); + vcdp->fullBus(c+38041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xaU]),16); + vcdp->fullBus(c+38049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xbU]),16); + vcdp->fullBus(c+38057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xcU]),16); + vcdp->fullBus(c+38065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xdU]),16); + vcdp->fullBus(c+38073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xeU]),16); + vcdp->fullBus(c+38081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->fullBus(c+38089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->fullBus(c+38097,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->fullBus(c+38105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+38113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+38121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->fullArray(c+38169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+38249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+38252,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+38255,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+38258,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+38261,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+38264,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+38267,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+38270,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+38273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+38276,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+38279,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+38282,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+38285,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+38288,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+38291,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+38294,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+38633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->fullBus(c+38737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+38745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+38753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+38761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+38769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+38777,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+38785,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+38793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->fullArray(c+38801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+38804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+38807,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+38810,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+38813,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->fullArray(c+38816,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->fullArray(c+38819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->fullArray(c+38822,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->fullArray(c+38993,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+39017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+39041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+39049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+39057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+39065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+39073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+39081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->fullArray(c+39088,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+39095,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+39102,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+39305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+39361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+39417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+39425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+39433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+39441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+39449,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+39457,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+39465,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+39473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+39481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+39489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+39505,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+39513,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+39521,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+39529,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+39537,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+39545,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+39553,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+39569,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+39577,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+39585,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+39593,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+39601,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+39617,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+39625,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+39633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+39641,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+39649,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+39657,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+39665,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1250[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1250[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1250[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1250[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+39673,(__Vtemp1250),128); + vcdp->fullBit(c+39705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+39713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+39721,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+39729,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+39745,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+39753,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+39761,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+39769,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+39777,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+39785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+39793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+39801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+39809,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+39817,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+39825,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+39833,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+39841,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+39849,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+39857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+39865,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+39873,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+39875,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+39877,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+39879,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->fullQuad(c+39881,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->fullQuad(c+39883,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->fullQuad(c+39885,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->fullQuad(c+39887,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->fullQuad(c+39889,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->fullQuad(c+39891,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->fullQuad(c+39893,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->fullQuad(c+39895,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->fullQuad(c+39897,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->fullQuad(c+39899,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->fullQuad(c+39901,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->fullQuad(c+39903,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->fullQuad(c+40129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->fullQuad(c+40145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->fullBus(c+40161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+40169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+40177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+40185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+40193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->fullArray(c+40201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->fullArray(c+40206,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->fullArray(c+40211,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->fullArray(c+40216,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->fullArray(c+40221,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->fullArray(c+40226,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->fullArray(c+40231,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->fullArray(c+40236,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->fullArray(c+40241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->fullArray(c+40246,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->fullArray(c+40251,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->fullArray(c+40256,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); 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+ vcdp->fullArray(c+43728,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+43735,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+43742,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+43945,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+44001,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+44057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+44065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+44073,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+44081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+44089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+44097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+44105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+44113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+44121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+44129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+44145,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+44153,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+44161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+44169,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+44177,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+44185,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+44193,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+44209,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+44217,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+44225,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+44233,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+44241,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+44257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+44265,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+44273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+44281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+44289,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+44297,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+44305,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1274[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1274[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1274[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1274[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+44313,(__Vtemp1274),128); + vcdp->fullBit(c+44345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+44353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+44361,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+44369,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+44385,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+44393,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+44401,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+44409,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+44417,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+44425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+44433,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+44441,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+44449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+44457,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+44465,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+44473,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+44481,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+44489,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+44497,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+44505,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+44513,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+44515,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+44517,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+44519,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->fullQuad(c+44521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->fullQuad(c+44523,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->fullQuad(c+44525,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->fullQuad(c+44527,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->fullQuad(c+44529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->fullQuad(c+44531,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->fullQuad(c+44533,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->fullQuad(c+44535,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->fullQuad(c+44537,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->fullQuad(c+44539,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->fullQuad(c+44541,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->fullQuad(c+44543,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->fullQuad(c+44769,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->fullQuad(c+44785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->fullBus(c+44801,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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+ vcdp->fullArray(c+48081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+48084,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+48087,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+48090,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+48093,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->fullArray(c+48096,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->fullArray(c+48099,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->fullArray(c+48102,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->fullArray(c+48273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+48297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+48321,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+48329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+48337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+48345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+48353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+48361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->fullArray(c+48368,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+48375,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+48382,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+48585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+48641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+48697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+48705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+48713,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+48721,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+48729,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+48737,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+48745,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+48753,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+48761,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+48769,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+48785,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+48793,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+48801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+48809,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+48817,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+48825,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+48833,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+48849,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+48857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+48865,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+48873,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+48881,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+48897,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+48905,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+48913,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+48921,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+48929,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+48937,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+48945,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1298[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1298[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1298[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1298[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+48953,(__Vtemp1298),128); + vcdp->fullBit(c+48985,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+48993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+49001,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+49009,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+49025,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+49033,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+49041,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+49049,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+49057,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+49065,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+49073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+49081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+49089,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+49097,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+49105,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+49113,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+49121,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+49129,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+49137,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+49145,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+49153,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+49155,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+49157,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+49159,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); 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+ vcdp->fullBit(c+50329,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+50337,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->fullArray(c+50345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+50355,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+50365,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+50375,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+50385,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); 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+ vcdp->fullArray(c+52172,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+52175,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+52178,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+52181,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+52184,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+52187,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+52190,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+52193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+52196,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+52199,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+52202,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+52205,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+52208,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+52211,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+52214,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+52553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->fullBus(c+52657,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+52665,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+52673,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+52681,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+52689,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+52697,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+52705,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+52713,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->fullArray(c+52721,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+52724,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+52727,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+52730,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+52733,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->fullArray(c+52736,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->fullArray(c+52739,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->fullArray(c+52742,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->fullArray(c+52913,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+52937,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+52961,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+52969,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+52977,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+52985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+52993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+53001,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->fullArray(c+53008,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+53015,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+53022,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+53225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+53281,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+53337,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+53345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+53353,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+53361,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+53369,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+53377,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+53385,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+53393,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+53401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+53409,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+53425,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+53433,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+53441,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))),2); + vcdp->fullBus(c+53449,(((0x18fU >= (0x1ffU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? (0x1ffffffU & (( + (0U + == + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x19U) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U)),25); + vcdp->fullBus(c+53457,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))),2); + vcdp->fullBus(c+53465,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U))),32); + vcdp->fullQuad(c+53473,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x37U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x17U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 9U))))),42); + vcdp->fullBus(c+53489,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 4U)))),4); + vcdp->fullBit(c+53497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)))); + vcdp->fullBit(c+53505,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); + vcdp->fullBus(c+53513,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+53521,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) + << 0x39U) | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x19U) + | ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + >> 7U))))),42); + vcdp->fullBit(c+53537,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U)))); + vcdp->fullBus(c+53545,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 2U)))),4); + vcdp->fullBit(c+53553,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))); + vcdp->fullBit(c+53561,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x13U)))); + vcdp->fullBus(c+53569,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x18U)))),2); + vcdp->fullBus(c+53577,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x18U))),32); + vcdp->fullBus(c+53585,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x18U))),32); + __Vtemp1322[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x18U)); + __Vtemp1322[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x18U)); + __Vtemp1322[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x18U)); + __Vtemp1322[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x18U)); + vcdp->fullArray(c+53593,(__Vtemp1322),128); + vcdp->fullBit(c+53625,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 2U)))); + vcdp->fullBit(c+53633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)))); + vcdp->fullBus(c+53641,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 0xfU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + >> 0x11U)))),16); + vcdp->fullQuad(c+53649,((VL_ULL(0x1ffffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); + vcdp->fullBus(c+53665,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),21); + vcdp->fullBit(c+53673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x15U)))); + vcdp->fullBit(c+53681,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x17U)))); + vcdp->fullBit(c+53689,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))); + vcdp->fullBit(c+53697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x18U)))); + vcdp->fullBit(c+53705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU)))); + vcdp->fullBit(c+53713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU)))); + vcdp->fullBit(c+53721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x19U)))); + vcdp->fullBit(c+53729,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+53737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+53745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+53753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+53761,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 1U)) + | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 6U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1aU))))),25); + vcdp->fullBus(c+53769,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 0x19U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 7U)))),28); + vcdp->fullBit(c+53777,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+53785,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+53793,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); + vcdp->fullQuad(c+53795,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); + vcdp->fullQuad(c+53797,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); + vcdp->fullQuad(c+53799,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); + vcdp->fullQuad(c+53801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); + vcdp->fullQuad(c+53803,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); + vcdp->fullQuad(c+53805,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); + vcdp->fullQuad(c+53807,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); + vcdp->fullQuad(c+53809,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); + vcdp->fullQuad(c+53811,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); + vcdp->fullQuad(c+53813,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); + vcdp->fullQuad(c+53815,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); + vcdp->fullQuad(c+53817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); + vcdp->fullQuad(c+53819,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); + vcdp->fullQuad(c+53821,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); + vcdp->fullQuad(c+53823,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); + vcdp->fullQuad(c+54049,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); + vcdp->fullQuad(c+54065,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); + vcdp->fullBus(c+54081,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+54089,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+54097,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+54105,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+54113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->fullArray(c+54121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); + vcdp->fullArray(c+54126,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); + vcdp->fullArray(c+54131,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); + vcdp->fullArray(c+54136,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); + vcdp->fullArray(c+54141,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); + vcdp->fullArray(c+54146,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); + vcdp->fullArray(c+54151,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); + vcdp->fullArray(c+54156,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); + vcdp->fullArray(c+54161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); + vcdp->fullArray(c+54166,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); + vcdp->fullArray(c+54171,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); + vcdp->fullArray(c+54176,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); + vcdp->fullArray(c+54181,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); + vcdp->fullArray(c+54186,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); + vcdp->fullArray(c+54191,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); + vcdp->fullArray(c+54196,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); + vcdp->fullArray(c+54761,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); + vcdp->fullArray(c+54801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); + vcdp->fullBus(c+54841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+54849,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+54857,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+54865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+54873,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+54881,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+54889,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+54897,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+54929,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+54961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+54969,((1U & (~ (IData)((0U + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); + vcdp->fullBus(c+54977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); + vcdp->fullArray(c+54985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+54995,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+55005,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+55015,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+55025,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); + vcdp->fullArray(c+55035,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); + vcdp->fullArray(c+55045,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); + vcdp->fullArray(c+55055,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); + vcdp->fullArray(c+55625,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+55705,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+55785,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+55793,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+55801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+55809,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullArray(c+55817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); + __Vtemp1323[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][0U]; + __Vtemp1323[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][1U]; + __Vtemp1323[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][2U]; + __Vtemp1323[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0U][3U]; + vcdp->fullArray(c+55881,(__Vtemp1323),128); + __Vtemp1324[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][0U]; + __Vtemp1324[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][1U]; + __Vtemp1324[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][2U]; + __Vtemp1324[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [1U][3U]; + vcdp->fullArray(c+55913,(__Vtemp1324),128); + __Vtemp1325[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][0U]; + __Vtemp1325[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][1U]; + __Vtemp1325[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][2U]; + __Vtemp1325[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [2U][3U]; + vcdp->fullArray(c+55945,(__Vtemp1325),128); + __Vtemp1326[0U] = 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vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xaU][2U]; + __Vtemp1333[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xaU][3U]; + vcdp->fullArray(c+56201,(__Vtemp1333),128); + __Vtemp1334[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xbU][0U]; + __Vtemp1334[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xbU][1U]; + __Vtemp1334[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xbU][2U]; + __Vtemp1334[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xbU][3U]; + vcdp->fullArray(c+56233,(__Vtemp1334),128); + __Vtemp1335[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][0U]; + __Vtemp1335[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][1U]; + __Vtemp1335[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][2U]; + __Vtemp1335[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xcU][3U]; + vcdp->fullArray(c+56265,(__Vtemp1335),128); + __Vtemp1336[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][0U]; + __Vtemp1336[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][1U]; + __Vtemp1336[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][2U]; + __Vtemp1336[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xdU][3U]; + vcdp->fullArray(c+56297,(__Vtemp1336),128); + __Vtemp1337[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][0U]; + __Vtemp1337[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][1U]; + __Vtemp1337[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][2U]; + __Vtemp1337[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xeU][3U]; + vcdp->fullArray(c+56329,(__Vtemp1337),128); + __Vtemp1338[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][0U]; + __Vtemp1338[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][1U]; + __Vtemp1338[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][2U]; + __Vtemp1338[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [0xfU][3U]; + vcdp->fullArray(c+56361,(__Vtemp1338),128); + vcdp->fullBus(c+56393,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); + vcdp->fullBus(c+56394,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); + vcdp->fullBus(c+56395,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); + vcdp->fullBus(c+56396,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); + vcdp->fullBus(c+56397,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); + vcdp->fullBus(c+56398,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); + vcdp->fullBus(c+56399,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); + vcdp->fullBus(c+56400,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); + vcdp->fullBus(c+56401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); + vcdp->fullBus(c+56402,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); + vcdp->fullBus(c+56403,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); + vcdp->fullBus(c+56404,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); + vcdp->fullBus(c+56405,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); + vcdp->fullBus(c+56406,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); + vcdp->fullBus(c+56407,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); + vcdp->fullBus(c+56408,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); + vcdp->fullBus(c+56521,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0U]),16); + vcdp->fullBus(c+56529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [1U]),16); + vcdp->fullBus(c+56537,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [2U]),16); + vcdp->fullBus(c+56545,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [3U]),16); + vcdp->fullBus(c+56553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [4U]),16); + vcdp->fullBus(c+56561,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [5U]),16); + vcdp->fullBus(c+56569,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [6U]),16); + vcdp->fullBus(c+56577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [7U]),16); + vcdp->fullBus(c+56585,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [8U]),16); + vcdp->fullBus(c+56593,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [9U]),16); + vcdp->fullBus(c+56601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xaU]),16); + vcdp->fullBus(c+56609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xbU]),16); + vcdp->fullBus(c+56617,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xcU]),16); + vcdp->fullBus(c+56625,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xdU]),16); + vcdp->fullBus(c+56633,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xeU]),16); + vcdp->fullBus(c+56641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [0xfU]),16); + vcdp->fullBus(c+56649,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); + vcdp->fullBus(c+56657,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); + vcdp->fullBus(c+56665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+56673,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+56681,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); + vcdp->fullArray(c+56729,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+56809,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+56812,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+56815,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+56818,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+56821,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+56824,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+56827,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+56830,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+56833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+56836,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+56839,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+56842,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+56845,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+56848,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+56851,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+56854,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+57193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); + vcdp->fullBus(c+57297,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+57305,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+57313,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+57321,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+57329,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+57337,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+57345,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+57353,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); + vcdp->fullArray(c+57361,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+57364,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+57367,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+57370,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+57373,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); + vcdp->fullArray(c+57376,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); + vcdp->fullArray(c+57379,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); + vcdp->fullArray(c+57382,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); + vcdp->fullArray(c+57553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+57577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+57601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); + vcdp->fullBus(c+57609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); + vcdp->fullBus(c+57617,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); + vcdp->fullBit(c+57625,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+57633,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+57641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); + vcdp->fullArray(c+57648,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); + vcdp->fullArray(c+57655,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); + vcdp->fullArray(c+57662,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); + vcdp->fullArray(c+57865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); + vcdp->fullArray(c+57921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); + vcdp->fullBus(c+57977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+57985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+57993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+58001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+58009,(vlTOPp->clk)); + vcdp->fullBit(c+58017,(vlTOPp->reset)); + vcdp->fullBus(c+58025,(vlTOPp->core_req_valid),4); + vcdp->fullBus(c+58033,(vlTOPp->core_req_rw),4); + vcdp->fullBus(c+58041,(vlTOPp->core_req_byteen),16); + vcdp->fullArray(c+58049,(vlTOPp->core_req_addr),120); + vcdp->fullArray(c+58081,(vlTOPp->core_req_data),128); + vcdp->fullQuad(c+58113,(vlTOPp->core_req_tag),42); + vcdp->fullBit(c+58129,(vlTOPp->core_req_ready)); + vcdp->fullBus(c+58137,(vlTOPp->core_rsp_valid),4); + vcdp->fullArray(c+58145,(vlTOPp->core_rsp_data),128); + vcdp->fullQuad(c+58177,(vlTOPp->core_rsp_tag),42); + vcdp->fullBit(c+58193,(vlTOPp->core_rsp_ready)); + vcdp->fullBit(c+58201,(vlTOPp->dram_req_valid)); + vcdp->fullBit(c+58209,(vlTOPp->dram_req_rw)); + vcdp->fullBus(c+58217,(vlTOPp->dram_req_byteen),16); + vcdp->fullBus(c+58225,(vlTOPp->dram_req_addr),28); + vcdp->fullArray(c+58233,(vlTOPp->dram_req_data),128); + vcdp->fullBus(c+58265,(vlTOPp->dram_req_tag),28); + vcdp->fullBit(c+58273,(vlTOPp->dram_req_ready)); + vcdp->fullBit(c+58281,(vlTOPp->dram_rsp_valid)); + vcdp->fullArray(c+58289,(vlTOPp->dram_rsp_data),128); + vcdp->fullBus(c+58321,(vlTOPp->dram_rsp_tag),28); + vcdp->fullBit(c+58329,(vlTOPp->dram_rsp_ready)); + vcdp->fullBit(c+58337,(vlTOPp->snp_req_valid)); + vcdp->fullBus(c+58345,(vlTOPp->snp_req_addr),28); + vcdp->fullBit(c+58353,(vlTOPp->snp_req_invalidate)); + vcdp->fullBus(c+58361,(vlTOPp->snp_req_tag),28); + vcdp->fullBit(c+58369,(vlTOPp->snp_req_ready)); + vcdp->fullBit(c+58377,(vlTOPp->snp_rsp_valid)); + vcdp->fullBus(c+58385,(vlTOPp->snp_rsp_tag),28); + vcdp->fullBit(c+58393,(vlTOPp->snp_rsp_ready)); + vcdp->fullBus(c+58401,(vlTOPp->snp_fwdout_valid),2); + vcdp->fullQuad(c+58409,(vlTOPp->snp_fwdout_addr),56); + vcdp->fullBus(c+58425,(vlTOPp->snp_fwdout_invalidate),2); + vcdp->fullBus(c+58433,(vlTOPp->snp_fwdout_tag),2); + vcdp->fullBus(c+58441,(vlTOPp->snp_fwdout_ready),2); + vcdp->fullBus(c+58449,(vlTOPp->snp_fwdin_valid),2); + vcdp->fullBus(c+58457,(vlTOPp->snp_fwdin_tag),2); + vcdp->fullBus(c+58465,(vlTOPp->snp_fwdin_ready),2); + vcdp->fullBit(c+58473,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58481,(((IData)(vlTOPp->dram_rsp_valid) + & (0U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBus(c+58489,((0x1ffffffU & (vlTOPp->dram_rsp_tag + >> 3U))),25); + vcdp->fullBit(c+58497,(((IData)(vlTOPp->snp_req_valid) + & (0U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBus(c+58505,((0x1ffffffU & (vlTOPp->snp_req_addr + >> 3U))),25); + vcdp->fullBit(c+58513,(((IData)(vlTOPp->dram_rsp_valid) + & (1U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+58521,(((IData)(vlTOPp->snp_req_valid) + & (1U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58529,(((IData)(vlTOPp->dram_rsp_valid) + & (2U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+58537,(((IData)(vlTOPp->snp_req_valid) + & (2U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58545,(((IData)(vlTOPp->dram_rsp_valid) + & (3U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+58553,(((IData)(vlTOPp->snp_req_valid) + & (3U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58561,(((IData)(vlTOPp->dram_rsp_valid) + & (4U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+58569,(((IData)(vlTOPp->snp_req_valid) + & (4U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58577,(((IData)(vlTOPp->dram_rsp_valid) + & (5U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+58585,(((IData)(vlTOPp->snp_req_valid) + & (5U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58593,(((IData)(vlTOPp->dram_rsp_valid) + & (6U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+58601,(((IData)(vlTOPp->snp_req_valid) + & (6U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58609,(((IData)(vlTOPp->dram_rsp_valid) + & (7U == (7U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+58617,(((IData)(vlTOPp->snp_req_valid) + & (7U == (7U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+58625,(((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))))); + vcdp->fullBit(c+58633,((((IData)(vlTOPp->dram_req_valid) + & (~ (IData)(vlTOPp->dram_req_rw))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+58641,(0U),32); + vcdp->fullBus(c+58649,(0x800U),32); + vcdp->fullBus(c+58657,(0x10U),32); + vcdp->fullBus(c+58665,(8U),32); + vcdp->fullBus(c+58673,(4U),32); + vcdp->fullBus(c+58681,(1U),32); + vcdp->fullBus(c+58689,(0x2aU),32); + vcdp->fullBus(c+58697,(0x1cU),32); + vcdp->fullBus(c+58705,(2U),32); + vcdp->fullBus(c+58713,(4U),32); + vcdp->fullBit(c+58721,(0U)); + vcdp->fullBus(c+58729,(0xe8U),32); + vcdp->fullBus(c+58737,(8U),32); + vcdp->fullBus(c+58745,(0U),32); + vcdp->fullBus(c+58753,(1U),32); + vcdp->fullBus(c+58761,(0x36U),32); + vcdp->fullBus(c+58769,(0x99U),32); + vcdp->fullBus(c+58777,(0x13aU),32); + vcdp->fullBus(c+58785,(0xf2U),32); + vcdp->fullBus(c+58793,(0xa7U),32); + vcdp->fullBus(c+58801,(0x13cU),32); + vcdp->fullBus(c+58809,(0x4cU),32); + vcdp->fullBus(c+58817,(0xc7U),32); + vcdp->fullBus(c+58825,(2U),32); + vcdp->fullBus(c+58833,(3U),32); + vcdp->fullBus(c+58841,(5U),32); + vcdp->fullBus(c+58849,(6U),32); + vcdp->fullBus(c+58857,(7U),32); + } +} diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk b/hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk new file mode 100644 index 00000000..ddfe0f03 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache_classes.mk @@ -0,0 +1,43 @@ +# Verilated -*- Makefile -*- +# DESCRIPTION: Verilator output: Make include file with class lists +# +# This file lists generated Verilated files, for including in higher level makefiles. +# See VVX_cache.mk for the caller. + +### Switches... +# Coverage output mode? 0/1 (from --coverage) +VM_COVERAGE = 0 +# Threaded output mode? 0/1/N threads (from --threads) +VM_THREADS = 0 +# Tracing output mode? 0/1 (from --trace) +VM_TRACE = 1 +# Tracing threaded output mode? 0/1 (from --trace-fst-thread) +VM_TRACE_THREADED = 0 + +### Object file lists... +# Generated module classes, fast-path, compile with highest optimization +VM_CLASSES_FAST += \ + VVX_cache \ + +# Generated module classes, non-fast-path, compile with low/medium optimization +VM_CLASSES_SLOW += \ + +# Generated support classes, fast-path, compile with highest optimization +VM_SUPPORT_FAST += \ + VVX_cache__Trace \ + +# Generated support classes, non-fast-path, compile with low/medium optimization +VM_SUPPORT_SLOW += \ + VVX_cache__Syms \ + VVX_cache__Trace__Slow \ + +# Global classes, need linked once per executable, fast-path, compile with highest optimization +VM_GLOBAL_FAST += \ + verilated \ + verilated_vcd_c \ + +# Global classes, need linked once per executable, non-fast-path, compile with low/medium optimization +VM_GLOBAL_SLOW += \ + + +# Verilated -*- Makefile -*- diff --git a/hw/unit_tests/cache/simulator.cpp b/hw/unit_tests/cache/simulator.cpp new file mode 100644 index 00000000..95af8d4f --- /dev/null +++ b/hw/unit_tests/cache/simulator.cpp @@ -0,0 +1,83 @@ +#include "simulator.h" +#include +#include +#include + +uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +Simulator::Simulator() { + // force random values for unitialized signals + Verilated::randReset(1); + + vortex_ = new VVX_priority_encoder(); + +#ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + trace_ = new VerilatedVcdC; + vortex_->trace(trace_, 99); + trace_->open("trace.vcd"); +#endif +} + +Simulator::~Simulator() { +#ifdef VCD_OUTPUT + trace_->close(); +#endif + delete vortex_; +} + + + +void Simulator::step() { + this->eval(); + + this->eval(); +} + + +void Simulator::reset() { +#ifndef NDEBUG + std::cout << timestamp << ": [sim] reset()" << std::endl; +#endif + + this->step(); +} + + +void Simulator::eval() { + vortex_->eval(); +#ifdef VCD_OUTPUT + trace_->dump(timestamp); +#endif + ++timestamp; +} + +void Simulator::wait(uint32_t cycles) { + for (int i = 0; i < cycles; ++i) { + this->step(); + } +} + + + +bool Simulator::run() { + // reset the device + this->reset(); + + // execute program + this->step(); + + + // wait 5 cycles to flush the pipeline + this->wait(5); + + + + return 0; +} + + diff --git a/hw/unit_tests/cache/simulator.h b/hw/unit_tests/cache/simulator.h new file mode 100644 index 00000000..7aa0f0aa --- /dev/null +++ b/hw/unit_tests/cache/simulator.h @@ -0,0 +1,52 @@ +#pragma once + +#include "VVX_priority_encoder.h" +#include "VVX_priority_encoder__Syms.h" +#include "verilated.h" + +#ifdef VCD_OUTPUT +#include +#endif + +//#include + +#include +#include + +class Simulator { +public: + + Simulator(); + virtual ~Simulator(); + + void load_bin(const char* program_file); + void load_ihex(const char* program_file); + + bool is_busy(); + + void reset(); + void step(); + void wait(uint32_t cycles); + void flush_caches(uint32_t mem_addr, uint32_t size); + + + bool run(); + void print_stats(std::ostream& out); + +private: + + void eval(); + + void eval_dram_bus(); + void eval_io_bus(); + void eval_snp_bus(); + + uint32_t snp_req_active_; + uint32_t snp_req_size_; + uint32_t pending_snp_reqs_; + + VVX_priority_encoder *vortex_; +#ifdef VCD_OUTPUT + VerilatedVcdC *trace_; +#endif +}; diff --git a/hw/unit_tests/cache/testbase.cpp b/hw/unit_tests/cache/testbase.cpp new file mode 100644 index 00000000..e0c826c4 --- /dev/null +++ b/hw/unit_tests/cache/testbase.cpp @@ -0,0 +1,59 @@ +#include "VVX_generic_queue.h" +#include "VVX_generic_queue__Syms.h" +#include "verilated.h" + +#include + +#include +#include + +uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +int main(int argc, char **argv){ + Verilated::commandArgs(argc, argv); //passes the command args to the object + + VVX_generic_queue *tb = new VVX_generic_queue; + tb->reset = 1; + tb->eval(); + tb->reset = 0; + unsigned int clk; + bool full; + bool empty; + int size; + int data_out; + tb->data_in = 0xff; + + tb->push = 1; + + for (int i = 0; i < 5; ++i){ + //toggle the clock + tb->eval(); + tb->clk = 1; + + tb->eval(); + tb->clk = 0; + tb->eval(); + + + full = tb->full; + empty = tb->empty; + size = tb->size; + data_out = tb->data_out; + clk = tb->clk; + + std::cout << "clk: " << clk << std::endl; + std::cout << "data_out: " << data_out << std::endl; + std::cout << "empty: " << empty << std::endl; + std::cout << "full: " << full << std::endl; + std::cout << "size: " << size << std::endl; + + } + + delete tb; + + exit(0); +} diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp new file mode 100644 index 00000000..8f8978b3 --- /dev/null +++ b/hw/unit_tests/cache/testbench.cpp @@ -0,0 +1,12 @@ +#include "simulator.h" +#include +#include +#include + +int main(int argc, char **argv) +{ + Simulator simulator; + bool curr = simulator.run(); + + return 0; +} \ No newline at end of file From 83a1695c73dec057cd5f1ce9e590d9d104c39d83 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 30 Jun 2020 18:14:06 -0700 Subject: [PATCH 08/22] OPAE CSR access --- driver/include/vortex.h | 4 +- driver/opae/vortex.cpp | 16 ++++--- driver/rtlsim/Makefile | 2 +- hw/opae/sources.txt | 4 ++ hw/opae/vortex_afu.json | 7 +-- hw/opae/vortex_afu.sv | 44 ++++++++++++++---- hw/opae/vortex_afu.vh | 7 +-- hw/rtl/VX_back_end.v | 35 +++++++------- hw/rtl/VX_cluster.v | 11 ++--- hw/rtl/VX_core.v | 50 +++++++------------- hw/rtl/VX_csr_arb.v | 68 +++++++++++++--------------- hw/rtl/VX_csr_io_arb.v | 35 +++++++------- hw/rtl/VX_define.vh | 1 + hw/rtl/VX_pipeline.v | 36 ++++++++++++--- hw/rtl/Vortex.v | 20 ++++---- hw/rtl/interfaces/VX_csr_io_req_if.v | 16 +++++++ hw/rtl/interfaces/VX_csr_io_rsp_if.v | 14 ++++++ hw/rtl/interfaces/VX_csr_req_if.v | 5 +- hw/rtl/interfaces/VX_wb_if.v | 6 +-- 19 files changed, 224 insertions(+), 157 deletions(-) create mode 100644 hw/rtl/interfaces/VX_csr_io_req_if.v create mode 100644 hw/rtl/interfaces/VX_csr_io_rsp_if.v diff --git a/driver/include/vortex.h b/driver/include/vortex.h index ded648db..d2a00a3f 100644 --- a/driver/include/vortex.h +++ b/driver/include/vortex.h @@ -58,10 +58,10 @@ int vx_start(vx_device_h hdevice); int vx_ready_wait(vx_device_h hdevice, long long timeout); // set device constant registers -int vx_csr_set(vx_device_h hdevice, int address, int value); +int vx_csr_set(vx_device_h hdevice, int core, int address, int value); // get device constant registers -int vx_csr_get(vx_device_h hdevice, int address, int* value); +int vx_csr_get(vx_device_h hdevice, int core, int address, int* value); ////////////////////////////// UTILITY FUNCIONS /////////////////////////////// diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index abb9c5b1..baac1204 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -43,6 +43,7 @@ #define MMIO_MEM_ADDR (AFU_IMAGE_MMIO_MEM_ADDR * 4) #define MMIO_DATA_SIZE (AFU_IMAGE_MMIO_DATA_SIZE * 4) #define MMIO_STATUS (AFU_IMAGE_MMIO_STATUS * 4) +#define MMIO_CSR_CORE (AFU_IMAGE_MMIO_CSR_CORE * 4) #define MMIO_CSR_ADDR (AFU_IMAGE_MMIO_CSR_ADDR * 4) #define MMIO_CSR_DATA (AFU_IMAGE_MMIO_CSR_DATA * 4) #define MMIO_CSR_READ (AFU_IMAGE_MMIO_CSR_READ * 4) @@ -172,10 +173,10 @@ extern int vx_dev_open(vx_device_h* hdevice) { { // Load device CAPS int ret = 0; - ret |= vx_csr_get(device, CSR_IMPL_ID, &device->implementation_id); - ret |= vx_csr_get(device, CSR_NC, &device->num_cores); - ret |= vx_csr_get(device, CSR_NW, &device->num_warps); - ret |= vx_csr_get(device, CSR_NT, &device->num_threads); + ret |= vx_csr_get(device, 0, CSR_IMPL_ID, &device->implementation_id); + ret |= vx_csr_get(device, 0, CSR_NC, &device->num_cores); + ret |= vx_csr_get(device, 0, CSR_NW, &device->num_warps); + ret |= vx_csr_get(device, 0, CSR_NT, &device->num_threads); if (ret != 0) { fpgaClose(accel_handle); return ret; @@ -467,7 +468,7 @@ extern int vx_start(vx_device_h hdevice) { } // set device constant registers -extern int vx_csr_set(vx_device_h hdevice, int address, int value) { +extern int vx_csr_set(vx_device_h hdevice, int core, int address, int value) { if (nullptr == hdevice) return -1; @@ -478,6 +479,7 @@ extern int vx_csr_set(vx_device_h hdevice, int address, int value) { return -1; // write CSR value + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_DATA, value)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_WRITE)); @@ -486,7 +488,7 @@ extern int vx_csr_set(vx_device_h hdevice, int address, int value) { } // get device constant registers -extern int vx_csr_get(vx_device_h hdevice, int address, int* value) { +extern int vx_csr_get(vx_device_h hdevice, int core, int address, int* value) { if (nullptr == hdevice || nullptr == value) return -1; @@ -496,7 +498,9 @@ extern int vx_csr_get(vx_device_h hdevice, int address, int* value) { if (vx_ready_wait(hdevice, -1) != 0) return -1; + // write CSR value + CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_CORE, core)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CSR_ADDR, address)); CHECK_RES(fpgaWriteMMIO64(device->fpga, 0, MMIO_CMD_TYPE, CMD_CSR_READ)); diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 19b39484..82ab979b 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG=1 -AFU=1 +#AFU=1 CFLAGS += -fPIC diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index 0263e558..e8d0480c 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -48,6 +48,8 @@ QI:vortex_afu.qsf ../rtl/interfaces/VX_cache_snp_req_if.v ../rtl/interfaces/VX_cache_snp_rsp_if.v ../rtl/interfaces/VX_csr_req_if.v +../rtl/interfaces/VX_csr_io_req_if.v +../rtl/interfaces/VX_csr_io_rsp_if.v ../rtl/interfaces/VX_exec_unit_req_if.v ../rtl/interfaces/VX_backend_req_if.v ../rtl/interfaces/VX_gpr_read_if.v @@ -90,6 +92,8 @@ QI:vortex_afu.qsf ../rtl/VX_writeback.v ../rtl/VX_csr_pipe.v ../rtl/VX_csr_data.v +../rtl/VX_csr_arb.v +../rtl/VX_csr_io_arb.v ../rtl/VX_warp_sched.v ../rtl/VX_gpr_ram.v ../rtl/VX_gpr_stage.v diff --git a/hw/opae/vortex_afu.json b/hw/opae/vortex_afu.json index f198383c..fb1e908c 100644 --- a/hw/opae/vortex_afu.json +++ b/hw/opae/vortex_afu.json @@ -19,9 +19,10 @@ "mmio-status": 18, "mmio-scope-read": 20, "mmio-scope-write": 22, - "mmio-csr-addr": 24, - "mmio-csr-data": 26, - "mmio-csr-read": 28, + "mmio-csr-core": 24, + "mmio-csr-addr": 26, + "mmio-csr-data": 28, + "mmio-csr-read": 30, "afu-top-interface": { diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index b57a3bc9..89ee968a 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -69,6 +69,7 @@ localparam MMIO_STATUS = `AFU_IMAGE_MMIO_STATUS; localparam MMIO_SCOPE_READ = `AFU_IMAGE_MMIO_SCOPE_READ; localparam MMIO_SCOPE_WRITE = `AFU_IMAGE_MMIO_SCOPE_WRITE; +localparam MMIO_CSR_CORE = `AFU_IMAGE_MMIO_CSR_CORE; localparam MMIO_CSR_ADDR = `AFU_IMAGE_MMIO_CSR_ADDR; localparam MMIO_CSR_DATA = `AFU_IMAGE_MMIO_CSR_DATA; localparam MMIO_CSR_READ = `AFU_IMAGE_MMIO_CSR_READ; @@ -123,7 +124,7 @@ logic [`VX_SNP_TAG_WIDTH-1:0] vx_snp_rsp_tag; logic vx_snp_rsp_ready; logic vx_csr_io_req_valid; -logic [`NC_BITS-1:0] vx_csr_io_req_coreid; +logic [`VX_CSR_ID_WIDTH-1:0] vx_csr_io_req_coreid; logic [11:0] vx_csr_io_req_addr; logic vx_csr_io_req_rw; logic [31:0] vx_csr_io_req_data; @@ -167,6 +168,7 @@ logic cmd_scope_read; logic cmd_scope_write; `endif +logic [`VX_CSR_ID_WIDTH-1:0] cmd_csr_core; logic [11:0] cmd_csr_addr; logic [31:0] cmd_csr_rdata; logic [31:0] cmd_csr_wdata; @@ -238,6 +240,12 @@ begin `endif end `endif + MMIO_CSR_CORE: begin + cmd_csr_core <= $bits(cmd_csr_core)'(cp2af_sRxPort.c0.data); + `ifdef DBG_PRINT_OPAE + $display("%t: MMIO_CSR_CORE: %0h", $time, $bits(cmd_csr_core)'(cp2af_sRxPort.c0.data)); + `endif + end MMIO_CSR_ADDR: begin cmd_csr_addr <= $bits(cmd_csr_addr)'(cp2af_sRxPort.c0.data); `ifdef DBG_PRINT_OPAE @@ -306,8 +314,7 @@ end logic cmd_read_done; logic cmd_write_done; logic cmd_clflush_done; -logic cmd_csr_read_done; -logic cmd_csr_write_done; +logic cmd_csr_done; logic cmd_run_done; always_ff @(posedge clk) @@ -395,13 +402,13 @@ begin end STATE_CSR_READ: begin - if (cmd_csr_read_done) begin + if (cmd_csr_done) begin state <= STATE_IDLE; end end STATE_CSR_WRITE: begin - if (cmd_csr_write_done) begin + if (cmd_csr_done) begin state <= STATE_IDLE; end end @@ -865,8 +872,11 @@ end // CSRs/////////////////////////////////////////////////////////////////////// -assign vx_csr_io_req_valid = (STATE_CSR_READ == state || STATE_CSR_WRITE == state); -assign vx_csr_io_req_coreid = 0; +logic csr_io_req_sent; + +assign vx_csr_io_req_valid = !csr_io_req_sent + && ((STATE_CSR_READ == state || STATE_CSR_WRITE == state)); +assign vx_csr_io_req_coreid = cmd_csr_core; assign vx_csr_io_req_rw = (STATE_CSR_WRITE == state); assign vx_csr_io_req_addr = cmd_csr_addr; assign vx_csr_io_req_data = cmd_csr_wdata; @@ -874,8 +884,22 @@ assign vx_csr_io_req_data = cmd_csr_wdata; assign cmd_csr_rdata = vx_csr_io_rsp_data; assign vx_csr_io_rsp_ready = 1; -assign cmd_csr_read_done = vx_csr_io_rsp_valid; -assign cmd_csr_write_done = vx_csr_io_req_ready; +assign cmd_csr_done = (STATE_CSR_WRITE == state) ? vx_csr_io_req_ready : vx_csr_io_rsp_valid; + +always_ff @(posedge clk) +begin + if (SoftReset) begin + csr_io_req_sent <= 0; + end + else begin + if (vx_csr_io_req_valid && vx_csr_io_req_ready) begin + csr_io_req_sent <= 1; + end + if (cmd_csr_done) begin + csr_io_req_sent <= 0; + end + end +end // Vortex ///////////////////////////////////////////////////////////////////// @@ -890,7 +914,7 @@ Vortex #() vortex ( `SCOPE_SIGNALS_BE_BIND .clk (clk), - .reset (vx_reset), + .reset (SoftReset | vx_reset), // DRAM request .dram_req_valid (vx_dram_req_valid), diff --git a/hw/opae/vortex_afu.vh b/hw/opae/vortex_afu.vh index 2b201bfd..910ea3af 100644 --- a/hw/opae/vortex_afu.vh +++ b/hw/opae/vortex_afu.vh @@ -20,9 +20,10 @@ `define AFU_IMAGE_CMD_MEM_WRITE 2 `define AFU_IMAGE_CMD_RUN 3 `define AFU_IMAGE_MMIO_CMD_TYPE 10 -`define AFU_IMAGE_MMIO_CSR_ADDR 24 -`define AFU_IMAGE_MMIO_CSR_DATA 26 -`define AFU_IMAGE_MMIO_CSR_READ 28 +`define AFU_IMAGE_MMIO_CSR_CORE 24 +`define AFU_IMAGE_MMIO_CSR_ADDR 26 +`define AFU_IMAGE_MMIO_CSR_DATA 28 +`define AFU_IMAGE_MMIO_CSR_READ 30 `define AFU_IMAGE_MMIO_DATA_SIZE 16 `define AFU_IMAGE_MMIO_IO_ADDR 12 `define AFU_IMAGE_MMIO_MEM_ADDR 14 diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index 00b118ee..8b284672 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -9,9 +9,8 @@ module VX_back_end #( input wire clk, input wire reset, - // IO CSR - VX_csr_req_if io_csr_req, - VX_wb_if io_csr_rsp, + VX_csr_io_req_if csr_io_req_if, + VX_csr_io_rsp_if csr_io_rsp_if, input wire schedule_delay, @@ -104,21 +103,23 @@ module VX_back_end #( .warp_ctl_if (warp_ctl_if) ); - VX_csr_req_if issued_csr_req(); + VX_csr_req_if issued_csr_req_if(); - VX_wb_if csr_pipe_rsp(); + VX_wb_if csr_pipe_rsp_if(); - VX_csr_arb csr_arbiter ( - .clk (clk), - .reset (reset), - .csr_pipe_stall(stall_gpr_csr), - .core_csr_req (csr_req_if), - .io_csr_req (io_csr_req), - .issued_csr_req(issued_csr_req), + VX_csr_arb csr_arb ( + .clk (clk), + .reset (reset), - .csr_pipe_rsp (csr_pipe_rsp), - .csr_wb_if (csr_wb_if), - .csr_io_rsp (io_csr_rsp) + .csr_pipe_stall (stall_gpr_csr), + + .csr_core_req_if (csr_req_if), + .csr_io_req_if (csr_io_req_if), + .issued_csr_req_if(issued_csr_req_if), + + .csr_pipe_rsp_if (csr_pipe_rsp_if), + .csr_wb_if (csr_wb_if), + .csr_io_rsp_if (csr_io_rsp_if) ); VX_csr_pipe #( @@ -127,9 +128,9 @@ module VX_back_end #( .clk (clk), .reset (reset), .no_slot_csr (no_slot_csr), - .csr_req_if (issued_csr_req), + .csr_req_if (issued_csr_req_if), .writeback_if (writeback_if), - .csr_wb_if (csr_pipe_rsp), + .csr_wb_if (csr_pipe_rsp_if), .stall_gpr_csr (stall_gpr_csr) ); diff --git a/hw/rtl/VX_cluster.v b/hw/rtl/VX_cluster.v index 9264a7a5..2633bf7d 100644 --- a/hw/rtl/VX_cluster.v +++ b/hw/rtl/VX_cluster.v @@ -123,7 +123,6 @@ module VX_cluster #( wire [`NUM_CORES-1:0] per_core_io_rsp_ready; wire [`NUM_CORES-1:0] per_core_csr_io_req_valid; - wire [`NUM_CORES-1:0][`NC_BITS-1:0] per_core_csr_io_req_coreid; wire [`NUM_CORES-1:0][11:0] per_core_csr_io_req_addr; wire [`NUM_CORES-1:0] per_core_csr_io_req_rw; wire [`NUM_CORES-1:0][31:0] per_core_csr_io_req_data; @@ -199,7 +198,7 @@ module VX_cluster #( .io_rsp_tag (per_core_io_rsp_tag [i]), .io_rsp_ready (per_core_io_rsp_ready [i]), - .csr_io_req_valid (per_core_csr_io_req_valid[i] && (per_core_csr_io_req_coreid[i] == `NC_BITS'(i))), + .csr_io_req_valid (per_core_csr_io_req_valid [i]), .csr_io_req_rw (per_core_csr_io_req_rw [i]), .csr_io_req_addr (per_core_csr_io_req_addr [i]), .csr_io_req_data (per_core_csr_io_req_data [i]), @@ -252,7 +251,7 @@ module VX_cluster #( .out_mem_rsp_tag (io_rsp_tag), .out_mem_rsp_data (io_rsp_data), .out_mem_rsp_ready (io_rsp_ready) - ); + ); VX_csr_io_arb #( .NUM_REQUESTS (`NUM_CORES) @@ -260,9 +259,10 @@ module VX_cluster #( .clk (clk), .reset (reset), + .request_id (csr_io_req_coreid), + // input requests - .in_csr_io_req_valid (csr_io_req_valid), - .in_csr_io_req_coreid (csr_io_req_coreid), + .in_csr_io_req_valid (csr_io_req_valid), .in_csr_io_req_addr (csr_io_req_addr), .in_csr_io_req_rw (csr_io_req_rw), .in_csr_io_req_data (csr_io_req_data), @@ -275,7 +275,6 @@ module VX_cluster #( // output request .out_csr_io_req_valid (per_core_csr_io_req_valid), - .out_csr_io_req_coreid (per_core_csr_io_req_coreid), .out_csr_io_req_addr (per_core_csr_io_req_addr), .out_csr_io_req_rw (per_core_csr_io_req_rw), .out_csr_io_req_data (per_core_csr_io_req_data), diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 6ec07382..7d6dc7a1 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -70,46 +70,22 @@ module VX_core #( input wire [`DCORE_TAG_WIDTH-1:0] io_rsp_tag, output wire io_rsp_ready, - // CSR I/O Request + // CSR I/O request input wire csr_io_req_valid, - input wire[11:0] csr_io_req_addr, + input wire [11:0] csr_io_req_addr, input wire csr_io_req_rw, - input wire[31:0] csr_io_req_data, + input wire [31:0] csr_io_req_data, output wire csr_io_req_ready, - // CSR I/O Response + // CSR I/O response output wire csr_io_rsp_valid, - output wire[31:0] csr_io_rsp_data, + output wire [31:0] csr_io_rsp_data, input wire csr_io_rsp_ready, // Status output wire busy, output wire ebreak ); - - `UNUSED_VAR(csr_io_rsp_ready) - - // IO CSR request - VX_csr_req_if io_csr_req(); - wire temp_io_csr_req_valid = csr_io_req_valid; - assign io_csr_req.valid = {`NUM_THREADS{temp_io_csr_req_valid}}; - assign io_csr_req.is_csr = 1'b1; - assign io_csr_req.csr_address = csr_io_req_addr; - assign io_csr_req.alu_op = csr_io_req_rw ? `ALU_CSR_RW : `ALU_CSR_RS; - assign io_csr_req.csr_mask = csr_io_req_rw ? csr_io_req_data : 32'b0; - - VX_wb_if io_csr_rsp(); - assign csr_io_req_ready = io_csr_rsp.is_io; - assign csr_io_rsp_valid = io_csr_rsp.valid[0]; - assign csr_io_rsp_data = io_csr_rsp.data[0]; - -`IGNORE_WARNINGS_BEGIN - wire [4:0] unused_rd = io_csr_rsp.rd; - wire [1:0] unused_wb = io_csr_rsp.wb; - wire [31:0] unused_curr_PC = io_csr_rsp.curr_PC; -`IGNORE_WARNINGS_END - - // Dcache Interfaces VX_cache_dram_req_if #( .DRAM_LINE_WIDTH(`DDRAM_LINE_WIDTH), .DRAM_ADDR_WIDTH(`DDRAM_ADDR_WIDTH), @@ -212,10 +188,6 @@ module VX_core #( .clk(clk), .reset(reset), - // IO CSR - .io_csr_req (io_csr_req), - .io_csr_rsp (io_csr_rsp), - // Dcache core request .dcache_req_valid (core_dcache_req_if.core_req_valid), .dcache_req_rw (core_dcache_req_if.core_req_rw), @@ -246,6 +218,18 @@ module VX_core #( .icache_rsp_tag (core_icache_rsp_if.core_rsp_tag), .icache_rsp_ready (core_icache_rsp_if.core_rsp_ready), + // CSR I/O request + .csr_io_req_valid (csr_io_req_valid), + .csr_io_req_rw (csr_io_req_rw), + .csr_io_req_addr (csr_io_req_addr), + .csr_io_req_data (csr_io_req_data), + .csr_io_req_ready (csr_io_req_ready), + + // CSR I/O response + .csr_io_rsp_valid (csr_io_rsp_valid), + .csr_io_rsp_data (csr_io_rsp_data), + .csr_io_rsp_ready (csr_io_rsp_ready), + // Status .busy(busy), .ebreak(ebreak) diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v index 7abe4f9a..5703d9ac 100644 --- a/hw/rtl/VX_csr_arb.v +++ b/hw/rtl/VX_csr_arb.v @@ -3,56 +3,52 @@ module VX_csr_arb ( input wire clk, input wire reset, - - input wire csr_pipe_stall, - - VX_csr_req_if core_csr_req, - VX_csr_req_if io_csr_req, - VX_csr_req_if issued_csr_req, - VX_wb_if csr_pipe_rsp, + input wire csr_pipe_stall, + + VX_csr_req_if csr_core_req_if, + VX_csr_io_req_if csr_io_req_if, + VX_csr_req_if issued_csr_req_if, + + VX_wb_if csr_pipe_rsp_if, VX_wb_if csr_wb_if, - VX_wb_if csr_io_rsp + VX_csr_io_rsp_if csr_io_rsp_if ); `UNUSED_VAR (clk) `UNUSED_VAR (reset) - wire pick_core = (|core_csr_req.valid); + wire pick_core = (| csr_core_req_if.valid); // Which request to pick - assign issued_csr_req.is_io = !pick_core; + assign issued_csr_req_if.is_io = !pick_core; // Mux between core and io - assign issued_csr_req.valid = pick_core ? core_csr_req.valid : io_csr_req.valid; - assign issued_csr_req.is_csr = pick_core ? core_csr_req.is_csr : io_csr_req.is_csr; - assign issued_csr_req.alu_op = pick_core ? core_csr_req.alu_op : io_csr_req.alu_op; - assign issued_csr_req.csr_address = pick_core ? core_csr_req.csr_address : io_csr_req.csr_address; - assign issued_csr_req.csr_mask = pick_core ? core_csr_req.csr_mask : io_csr_req.csr_mask; + assign issued_csr_req_if.valid = pick_core ? csr_core_req_if.valid : {`NUM_THREADS{csr_io_req_if.valid}}; + assign issued_csr_req_if.is_csr = pick_core ? csr_core_req_if.is_csr : 1'b1; + assign issued_csr_req_if.alu_op = pick_core ? csr_core_req_if.alu_op : (csr_io_req_if.rw ? `ALU_CSR_RW : `ALU_CSR_RS); + assign issued_csr_req_if.csr_address = pick_core ? csr_core_req_if.csr_address : csr_io_req_if.addr; + assign issued_csr_req_if.csr_mask = pick_core ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); + + assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core); // Core arguments - assign issued_csr_req.warp_num = core_csr_req.warp_num; - assign issued_csr_req.rd = core_csr_req.rd; - assign issued_csr_req.wb = core_csr_req.wb; + assign issued_csr_req_if.warp_num = csr_core_req_if.warp_num; + assign issued_csr_req_if.rd = csr_core_req_if.rd; + assign issued_csr_req_if.wb = csr_core_req_if.wb; - // Core Writeback + // Core Writeback + assign csr_wb_if.valid = csr_pipe_rsp_if.valid & {`NUM_THREADS{~csr_pipe_rsp_if.is_io}}; + assign csr_wb_if.data = csr_pipe_rsp_if.data; + assign csr_wb_if.warp_num = csr_pipe_rsp_if.warp_num; + assign csr_wb_if.rd = csr_pipe_rsp_if.rd; + assign csr_wb_if.wb = csr_pipe_rsp_if.wb; + assign csr_wb_if.curr_PC = csr_pipe_rsp_if.curr_PC; - assign csr_wb_if.valid = csr_pipe_rsp.valid & {`NUM_THREADS{~csr_pipe_rsp.is_io}}; - assign csr_wb_if.data = csr_pipe_rsp.data; - assign csr_wb_if.warp_num = csr_pipe_rsp.warp_num; - assign csr_wb_if.rd = csr_pipe_rsp.rd; - assign csr_wb_if.wb = csr_pipe_rsp.wb; - assign csr_wb_if.curr_PC = csr_pipe_rsp.curr_PC; - assign csr_wb_if.is_io = 1'b0; - - // CSR IO WB - - assign csr_io_rsp.valid = csr_pipe_rsp.valid & {`NUM_THREADS{csr_pipe_rsp.is_io}}; - assign csr_io_rsp.data = csr_pipe_rsp.data; - assign csr_io_rsp.warp_num = csr_pipe_rsp.warp_num; - assign csr_io_rsp.rd = csr_pipe_rsp.rd; - assign csr_io_rsp.wb = csr_pipe_rsp.wb; - assign csr_io_rsp.curr_PC = csr_pipe_rsp.curr_PC; - assign csr_io_rsp.is_io = !(csr_pipe_stall || pick_core); + // CSR I/O response + assign csr_io_rsp_if.valid = csr_pipe_rsp_if.valid[0] & csr_pipe_rsp_if.is_io; + assign csr_io_rsp_if.data = csr_pipe_rsp_if.data[0]; + wire x = csr_io_rsp_if.ready; + `UNUSED_VAR(x) endmodule diff --git a/hw/rtl/VX_csr_io_arb.v b/hw/rtl/VX_csr_io_arb.v index 3c5ada5e..bf0d7041 100644 --- a/hw/rtl/VX_csr_io_arb.v +++ b/hw/rtl/VX_csr_io_arb.v @@ -4,12 +4,13 @@ module VX_csr_io_arb #( parameter NUM_REQUESTS = 1, parameter REQS_BITS = `CLOG2(NUM_REQUESTS) ) ( - input wire clk, - input wire reset, + input wire clk, + input wire reset, + + input wire [REQS_BITS-1:0] request_id, // input requests input wire in_csr_io_req_valid, - input wire [`NC_BITS-1:0] in_csr_io_req_coreid, input wire [11:0] in_csr_io_req_addr, input wire in_csr_io_req_rw, input wire [31:0] in_csr_io_req_data, @@ -22,7 +23,6 @@ module VX_csr_io_arb #( // output request output wire [NUM_REQUESTS-1:0] out_csr_io_req_valid, - output wire [NUM_REQUESTS-1:0][`NC_BITS-1:0] out_csr_io_req_coreid, output wire [NUM_REQUESTS-1:0][11:0] out_csr_io_req_addr, output wire [NUM_REQUESTS-1:0] out_csr_io_req_rw, output wire [NUM_REQUESTS-1:0][31:0] out_csr_io_req_data, @@ -39,7 +39,6 @@ module VX_csr_io_arb #( `UNUSED_VAR (reset) assign out_csr_io_req_valid = in_csr_io_req_valid; - assign out_csr_io_req_coreid = in_csr_io_req_coreid; assign out_csr_io_req_rw = in_csr_io_req_rw; assign out_csr_io_req_addr = in_csr_io_req_addr; assign out_csr_io_req_data = in_csr_io_req_data; @@ -51,6 +50,17 @@ module VX_csr_io_arb #( end else begin + genvar i; + + for (i = 0; i < NUM_REQUESTS; i++) begin + assign out_csr_io_req_valid[i] = in_csr_io_req_valid && (request_id == `REQS_BITS'(i)); + assign out_csr_io_req_rw[i] = in_csr_io_req_rw; + assign out_csr_io_req_addr[i] = in_csr_io_req_addr; + assign out_csr_io_req_data[i] = in_csr_io_req_data; + end + + assign in_csr_io_req_ready = out_csr_io_req_ready[request_id]; + reg [REQS_BITS-1:0] bus_rsp_sel; VX_fixed_arbiter #( @@ -65,20 +75,11 @@ module VX_csr_io_arb #( ); assign out_csr_io_rsp_valid = in_csr_io_rsp_valid [bus_rsp_sel]; - assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel]; - assign in_csr_io_rsp_ready [bus_rsp_sel] = out_csr_io_rsp_ready; + assign out_csr_io_rsp_data = in_csr_io_rsp_data [bus_rsp_sel]; - genvar i; - - for (i = 0; i < NUM_REQUESTS; i++) begin - assign out_csr_io_req_valid[i] = in_csr_io_req_valid && in_csr_io_req_ready; - assign out_csr_io_req_coreid[i] = in_csr_io_req_coreid; - assign out_csr_io_req_rw[i] = in_csr_io_req_rw; - assign out_csr_io_req_addr[i] = in_csr_io_req_addr; - assign out_csr_io_req_data[i] = in_csr_io_req_data; + for (i = 0; i < NUM_REQUESTS; i++) begin + assign in_csr_io_rsp_ready[i] = out_csr_io_rsp_ready && (bus_rsp_sel == `REQS_BITS'(i)); end - - assign in_csr_io_req_ready = (& out_csr_io_req_ready); end diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 3ddc4dff..21118a76 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -288,6 +288,7 @@ `define VX_DRAM_TAG_WIDTH `L3DRAM_TAG_WIDTH `define VX_SNP_TAG_WIDTH `L3SNP_TAG_WIDTH `define VX_CORE_TAG_WIDTH `L3CORE_TAG_WIDTH +`define VX_CSR_ID_WIDTH `CLOG2(`NUM_CLUSTERS * `NUM_CORES) `define DRAM_TO_BYTE_ADDR(x) {x, (32-$bits(x))'(0)} diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 1424e06c..83833f3d 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -12,10 +12,6 @@ module VX_pipeline #( input wire clk, input wire reset, - // IO CSR - VX_csr_req_if io_csr_req, - VX_wb_if io_csr_rsp, - // Dcache core request output wire [`NUM_THREADS-1:0] dcache_req_valid, output wire [`NUM_THREADS-1:0] dcache_req_rw, @@ -44,7 +40,19 @@ module VX_pipeline #( input wire icache_rsp_valid, input wire [31:0] icache_rsp_data, input wire [`ICORE_TAG_WIDTH-1:0] icache_rsp_tag, - output wire icache_rsp_ready, + output wire icache_rsp_ready, + + // CSR I/O Request + input wire csr_io_req_valid, + input wire[11:0] csr_io_req_addr, + input wire csr_io_req_rw, + input wire[31:0] csr_io_req_data, + output wire csr_io_req_ready, + + // CSR I/O Response + output wire csr_io_rsp_valid, + output wire[31:0] csr_io_rsp_data, + input wire csr_io_rsp_ready, // Status output wire busy, @@ -90,6 +98,20 @@ module VX_pipeline #( .CORE_TAG_ID_BITS(`ICORE_TAG_ID_BITS) ) core_icache_rsp_if(); + + // CSR I/O + VX_csr_io_req_if csr_io_req_if(); + assign csr_io_req_if.valid = csr_io_req_valid; + assign csr_io_req_if.rw = csr_io_req_rw; + assign csr_io_req_if.addr = csr_io_req_addr; + assign csr_io_req_if.data = csr_io_req_data; + assign csr_io_req_ready = csr_io_req_if.ready; + + VX_csr_io_rsp_if csr_io_rsp_if(); + assign csr_io_rsp_valid = csr_io_rsp_if.valid; + assign csr_io_rsp_data = csr_io_rsp_if.data; + assign csr_io_rsp_if.ready = csr_io_rsp_ready; + // Front-end to Back-end VX_backend_req_if bckE_req_if(); @@ -138,8 +160,8 @@ module VX_pipeline #( .clk (clk), .reset (reset), - .io_csr_req (io_csr_req), - .io_csr_rsp (io_csr_rsp), + .csr_io_req_if (csr_io_req_if), + .csr_io_rsp_if (csr_io_rsp_if), .schedule_delay (schedule_delay), .warp_ctl_if (warp_ctl_if), .bckE_req_if (bckE_req_if), diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index f3c3c56b..a606c15f 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -56,7 +56,7 @@ module Vortex ( // CSR I/O Request input wire csr_io_req_valid, - input wire [`NC_BITS-1:0] csr_io_req_coreid, + input wire [`VX_CSR_ID_WIDTH-1:0] csr_io_req_coreid, input wire [11:0] csr_io_req_addr, input wire csr_io_req_rw, input wire [31:0] csr_io_req_data, @@ -74,7 +74,7 @@ module Vortex ( if (`NUM_CLUSTERS == 1) begin VX_cluster #( - .CLUSTER_ID(`L3CACHE_ID) + .CLUSTER_ID(0) ) cluster ( `SCOPE_SIGNALS_ISTAGE_BIND `SCOPE_SIGNALS_LSU_BIND @@ -148,8 +148,8 @@ module Vortex ( wire l3_core_req_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L3DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L3DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; + wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; @@ -176,7 +176,6 @@ module Vortex ( wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid; - wire [`NUM_CLUSTERS-1:0][`NC_BITS-1:0] per_cluster_csr_io_req_coreid; wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr; wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw; wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data; @@ -189,6 +188,9 @@ module Vortex ( wire [`NUM_CLUSTERS-1:0] per_cluster_busy; wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; + wire [`CLOG2(`NUM_CLUSTERS)-1:0] csr_io_request_id = `CLOG2(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CLUSTERS)); + wire [`NC_BITS-1:0] per_cluster_csr_io_req_coreid = `NC_BITS'(csr_io_req_coreid); + genvar i; for (i = 0; i < `NUM_CLUSTERS; i++) begin VX_cluster #( @@ -241,7 +243,7 @@ module Vortex ( .io_rsp_ready (per_cluster_io_rsp_ready [i]), .csr_io_req_valid (per_cluster_csr_io_req_valid[i]), - .csr_io_req_coreid (per_cluster_csr_io_req_coreid[i]), + .csr_io_req_coreid (per_cluster_csr_io_req_coreid), .csr_io_req_rw (per_cluster_csr_io_req_rw [i]), .csr_io_req_addr (per_cluster_csr_io_req_addr[i]), .csr_io_req_data (per_cluster_csr_io_req_data[i]), @@ -302,9 +304,10 @@ module Vortex ( .clk (clk), .reset (reset), + .request_id (csr_io_request_id), + // input requests - .in_csr_io_req_valid (csr_io_req_valid), - .in_csr_io_req_coreid (csr_io_req_coreid), + .in_csr_io_req_valid (csr_io_req_valid), .in_csr_io_req_addr (csr_io_req_addr), .in_csr_io_req_rw (csr_io_req_rw), .in_csr_io_req_data (csr_io_req_data), @@ -317,7 +320,6 @@ module Vortex ( // output request .out_csr_io_req_valid (per_cluster_csr_io_req_valid), - .out_csr_io_req_coreid (per_cluster_csr_io_req_coreid), .out_csr_io_req_addr (per_cluster_csr_io_req_addr), .out_csr_io_req_rw (per_cluster_csr_io_req_rw), .out_csr_io_req_data (per_cluster_csr_io_req_data), diff --git a/hw/rtl/interfaces/VX_csr_io_req_if.v b/hw/rtl/interfaces/VX_csr_io_req_if.v new file mode 100644 index 00000000..ce8d2fed --- /dev/null +++ b/hw/rtl/interfaces/VX_csr_io_req_if.v @@ -0,0 +1,16 @@ +`ifndef VX_CSR_IO_REQ_IF +`define VX_CSR_IO_REQ_IF + +`include "VX_define.vh" + +interface VX_csr_io_req_if (); + + wire valid; + wire rw; + wire [11:0] addr; + wire [31:0] data; + wire ready; + +endinterface + +`endif diff --git a/hw/rtl/interfaces/VX_csr_io_rsp_if.v b/hw/rtl/interfaces/VX_csr_io_rsp_if.v new file mode 100644 index 00000000..7c4c8f6d --- /dev/null +++ b/hw/rtl/interfaces/VX_csr_io_rsp_if.v @@ -0,0 +1,14 @@ +`ifndef VX_CSR_IO_RSP_IF +`define VX_CSR_IO_RSP_IF + +`include "VX_define.vh" + +interface VX_csr_io_rsp_if (); + + wire valid; + wire [31:0] data; + wire ready; + +endinterface + +`endif diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index 902f3833..a661e38f 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -15,9 +15,8 @@ interface VX_csr_req_if (); wire csr_immed; wire [31:0] csr_mask; -`IGNORE_WARNINGS_BEGIN - wire is_io; -`IGNORE_WARNINGS_END + wire is_io; + endinterface `endif diff --git a/hw/rtl/interfaces/VX_wb_if.v b/hw/rtl/interfaces/VX_wb_if.v index c9e57085..96b8acef 100644 --- a/hw/rtl/interfaces/VX_wb_if.v +++ b/hw/rtl/interfaces/VX_wb_if.v @@ -10,11 +10,9 @@ interface VX_wb_if (); wire [`NW_BITS-1:0] warp_num; wire [4:0] rd; wire [1:0] wb; - wire [31:0] curr_PC; - -`IGNORE_WARNINGS_BEGIN + wire [31:0] curr_PC; wire is_io; -`IGNORE_WARNINGS_END + endinterface `endif From 9d1762e5e55cd95a1e4096828f3e3d4e9f326975 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 30 Jun 2020 18:27:37 -0700 Subject: [PATCH 09/22] reverting stall_gpr_csr --- hw/rtl/VX_csr_pipe.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index 52b6ff94..dd80a811 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -77,6 +77,6 @@ module VX_csr_pipe #( csr_read_data_s2; end - assign stall_gpr_csr = no_slot_csr; + assign stall_gpr_csr = no_slot_csr && csr_req_if.is_csr && (| csr_req_if.valid); endmodule From e155c8a9b3f28f0de71ba4b30f0212bf898e7bc6 Mon Sep 17 00:00:00 2001 From: trmontgomery Date: Tue, 30 Jun 2020 22:40:14 -0400 Subject: [PATCH 10/22] cache makfile changes --- hw/unit_tests/cache/Makefile | 3 ++- hw/unit_tests/cache/cache_sim.cpp | 1 + hw/unit_tests/cache/obj_dir/VVX_cache.mk | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/unit_tests/cache/Makefile b/hw/unit_tests/cache/Makefile index 343fd281..b7e71682 100644 --- a/hw/unit_tests/cache/Makefile +++ b/hw/unit_tests/cache/Makefile @@ -1,4 +1,5 @@ -PARAM += +PARAM += -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DWORD_SIZE=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 + # control RTL debug print states diff --git a/hw/unit_tests/cache/cache_sim.cpp b/hw/unit_tests/cache/cache_sim.cpp index 1931fd8a..4f2767ce 100644 --- a/hw/unit_tests/cache/cache_sim.cpp +++ b/hw/unit_tests/cache/cache_sim.cpp @@ -72,3 +72,4 @@ int main(int argc, char **argv){ exit(0); } + diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.mk b/hw/unit_tests/cache/obj_dir/VVX_cache.mk index a00727e3..a7ab278e 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache.mk +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.mk @@ -33,7 +33,7 @@ VM_PREFIX = VVX_cache VM_MODPREFIX = VVX_cache # User CFLAGS (from -CFLAGS on Verilator command line) VM_USER_CFLAGS = \ - -std=c++11 -fms-extensions -I../.. -DNDEBUG -DDATAW=4 -DSIZE=4 \ + -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DWORD_SIZE=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \ # User LDLIBS (from -LDFLAGS on Verilator command line) VM_USER_LDLIBS = \ From e92029c31ab4a1a793f4a730bd68879cd1002707 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Tue, 30 Jun 2020 20:51:09 -0700 Subject: [PATCH 11/22] simX cleanup --- simX/riscv_tests/rv32ui-p-add.hex | 109 ----------------------- simX/riscv_tests/rv32ui-p-addi.hex | 69 --------------- simX/riscv_tests/rv32ui-p-and.hex | 105 ---------------------- simX/riscv_tests/rv32ui-p-andi.hex | 57 ------------ simX/riscv_tests/rv32ui-p-auipc.hex | 36 -------- simX/riscv_tests/rv32ui-p-beq.hex | 73 ---------------- simX/riscv_tests/rv32ui-p-bge.hex | 81 ----------------- simX/riscv_tests/rv32ui-p-bgeu.hex | 85 ------------------ simX/riscv_tests/rv32ui-p-blt.hex | 73 ---------------- simX/riscv_tests/rv32ui-p-bltu.hex | 77 ---------------- simX/riscv_tests/rv32ui-p-bne.hex | 73 ---------------- simX/riscv_tests/rv32ui-p-fence_i.hex | 44 ---------- simX/riscv_tests/rv32ui-p-jal.hex | 37 -------- simX/riscv_tests/rv32ui-p-jalr.hex | 45 ---------- simX/riscv_tests/rv32ui-p-lb.hex | 70 --------------- simX/riscv_tests/rv32ui-p-lbu.hex | 70 --------------- simX/riscv_tests/rv32ui-p-lh.hex | 70 --------------- simX/riscv_tests/rv32ui-p-lhu.hex | 70 --------------- simX/riscv_tests/rv32ui-p-lui.hex | 37 -------- simX/riscv_tests/rv32ui-p-lw.hex | 74 ---------------- simX/riscv_tests/rv32ui-p-or.hex | 105 ---------------------- simX/riscv_tests/rv32ui-p-ori.hex | 61 ------------- simX/riscv_tests/rv32ui-p-sb.hex | 94 -------------------- simX/riscv_tests/rv32ui-p-sh.hex | 103 ---------------------- simX/riscv_tests/rv32ui-p-simple.hex | 29 ------ simX/riscv_tests/rv32ui-p-sll.hex | 117 ------------------------- simX/riscv_tests/rv32ui-p-slli.hex | 69 --------------- simX/riscv_tests/rv32ui-p-slt.hex | 105 ---------------------- simX/riscv_tests/rv32ui-p-slti.hex | 69 --------------- simX/riscv_tests/rv32ui-p-sltiu.hex | 69 --------------- simX/riscv_tests/rv32ui-p-sltu.hex | 105 ---------------------- simX/riscv_tests/rv32ui-p-sra.hex | 121 -------------------------- simX/riscv_tests/rv32ui-p-srai.hex | 73 ---------------- simX/riscv_tests/rv32ui-p-srl.hex | 117 ------------------------- simX/riscv_tests/rv32ui-p-srli.hex | 73 ---------------- simX/riscv_tests/rv32ui-p-sub.hex | 105 ---------------------- simX/riscv_tests/rv32ui-p-sw.hex | 104 ---------------------- simX/riscv_tests/rv32ui-p-xor.hex | 105 ---------------------- simX/riscv_tests/rv32ui-p-xori.hex | 61 ------------- simX/riscv_tests/rv32um-p-div.hex | 45 ---------- simX/riscv_tests/rv32um-p-divu.hex | 45 ---------- simX/riscv_tests/rv32um-p-mul.hex | 105 ---------------------- simX/riscv_tests/rv32um-p-mulh.hex | 105 ---------------------- simX/riscv_tests/rv32um-p-mulhsu.hex | 105 ---------------------- simX/riscv_tests/rv32um-p-mulhu.hex | 105 ---------------------- simX/riscv_tests/rv32um-p-rem.hex | 45 ---------- simX/riscv_tests/rv32um-p-remu.hex | 45 ---------- 47 files changed, 3640 deletions(-) delete mode 100644 simX/riscv_tests/rv32ui-p-add.hex delete mode 100644 simX/riscv_tests/rv32ui-p-addi.hex delete mode 100644 simX/riscv_tests/rv32ui-p-and.hex delete mode 100644 simX/riscv_tests/rv32ui-p-andi.hex delete mode 100644 simX/riscv_tests/rv32ui-p-auipc.hex delete mode 100644 simX/riscv_tests/rv32ui-p-beq.hex delete mode 100644 simX/riscv_tests/rv32ui-p-bge.hex delete mode 100644 simX/riscv_tests/rv32ui-p-bgeu.hex delete mode 100644 simX/riscv_tests/rv32ui-p-blt.hex delete mode 100644 simX/riscv_tests/rv32ui-p-bltu.hex delete mode 100644 simX/riscv_tests/rv32ui-p-bne.hex delete mode 100644 simX/riscv_tests/rv32ui-p-fence_i.hex delete mode 100644 simX/riscv_tests/rv32ui-p-jal.hex delete mode 100644 simX/riscv_tests/rv32ui-p-jalr.hex delete mode 100644 simX/riscv_tests/rv32ui-p-lb.hex delete mode 100644 simX/riscv_tests/rv32ui-p-lbu.hex delete mode 100644 simX/riscv_tests/rv32ui-p-lh.hex delete mode 100644 simX/riscv_tests/rv32ui-p-lhu.hex delete mode 100644 simX/riscv_tests/rv32ui-p-lui.hex delete mode 100644 simX/riscv_tests/rv32ui-p-lw.hex delete mode 100644 simX/riscv_tests/rv32ui-p-or.hex delete mode 100644 simX/riscv_tests/rv32ui-p-ori.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sb.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sh.hex delete mode 100644 simX/riscv_tests/rv32ui-p-simple.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sll.hex delete mode 100644 simX/riscv_tests/rv32ui-p-slli.hex delete mode 100644 simX/riscv_tests/rv32ui-p-slt.hex delete mode 100644 simX/riscv_tests/rv32ui-p-slti.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sltiu.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sltu.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sra.hex delete mode 100644 simX/riscv_tests/rv32ui-p-srai.hex delete mode 100644 simX/riscv_tests/rv32ui-p-srl.hex delete mode 100644 simX/riscv_tests/rv32ui-p-srli.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sub.hex delete mode 100644 simX/riscv_tests/rv32ui-p-sw.hex delete mode 100644 simX/riscv_tests/rv32ui-p-xor.hex delete mode 100644 simX/riscv_tests/rv32ui-p-xori.hex delete mode 100644 simX/riscv_tests/rv32um-p-div.hex delete mode 100644 simX/riscv_tests/rv32um-p-divu.hex delete mode 100644 simX/riscv_tests/rv32um-p-mul.hex delete mode 100644 simX/riscv_tests/rv32um-p-mulh.hex delete mode 100644 simX/riscv_tests/rv32um-p-mulhsu.hex delete mode 100644 simX/riscv_tests/rv32um-p-mulhu.hex delete mode 100644 simX/riscv_tests/rv32um-p-rem.hex delete mode 100644 simX/riscv_tests/rv32um-p-remu.hex diff --git a/simX/riscv_tests/rv32ui-p-add.hex b/simX/riscv_tests/rv32ui-p-add.hex deleted file mode 100644 index 04bf8c08..00000000 --- a/simX/riscv_tests/rv32ui-p-add.hex +++ /dev/null @@ -1,109 +0,0 @@ -:0200000480007A -:100000006F00C004732F2034930F8000630AFF0336 -:10001000930F90006306FF03930FB0006302FF038A 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-:1000500063100500970200009382020173905230F2 -:10006000735000189702000093820202739052307E -:10007000B70200809382F2FF7390023B9302F0017B -:100080007390023A9702000093828201739052307B -:100090007350203073503030735040309301000063 -:1000A00097020000938242F67390523013051000BD -:1000B0001315F501634C05000F00F00F93011000BC -:1000C0009308D0051305000073000000970200801C -:1000D000938242F3638E020073905210B7B2000015 -:1000E000938292107390223073232030E39862F44D -:1000F00073500030970200009382420173901234D3 -:10010000732540F17300203093004001130160001B -:1001100033F72002930E2000930120006314D70DC3 -:100120009300C0FE1301600033F72002930E2000FD -:10013000930130006318D70B930040011301A0FF17 -:1001400033F72002930E400193014000631CD7094E -:100150009300C0FE1301A0FF33F72002930EC0FEF0 -:10016000930150006310D709B700008013011000FD -:1001700033F72002930E0000930160006314D70749 -:10018000B70000801301F0FF33F72002B70E0080A4 -:10019000930170006318D705B700008013010000B9 -:1001A00033F72002B70E008093018000631CD70351 -:1001B000930010001301000033F72002930E10008B -:1001C000930190006310D703930000001301000017 -:1001D00033F72002930E00009301A0006314D701AF -:1001E000631030020F00F00F638001009391110043 -:1001F00093E111009308D0051385010073000000FE -:100200000F00F00F930110009308D00513050000B4 -:1002100073000000731000C0000000000000000028 -:1002200000000000000000000000000000000000CE -:1002300000000000000000000000000000000000BE -:0402400000000000BA -:1010000000000000000000000000000000000000E0 -:1010100000000000000000000000000000000000D0 -:1010200000000000000000000000000000000000C0 -:1010300000000000000000000000000000000000B0 -:081040000000000000000000A8 -:040000058000000077 -:00000001FF From 5d088d67c8686a9bba763936f8777cbd1d06087f Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 1 Jul 2020 09:30:12 -0700 Subject: [PATCH 12/22] Gather FPGA perf stats --- benchmarks/opencl/vecadd/main.cc | 22 ----------------- driver/include/vortex.h | 4 ++-- driver/opae/vortex.cpp | 40 +++++++++++++++++++++++++------ driver/tests/demo/kernel.bin | Bin 6812 -> 6852 bytes hw/opae/vortex_afu.sv | 7 +++++- hw/rtl/VX_alu_unit.v | 2 +- hw/rtl/VX_csr_arb.v | 21 +++++++--------- hw/rtl/VX_csr_pipe.v | 1 - hw/rtl/VX_decode.v | 2 +- hw/rtl/VX_gpr_stage.v | 1 - hw/rtl/libs/VX_divide.v | 2 +- hw/rtl/libs/VX_mult.v | 4 ++-- 12 files changed, 55 insertions(+), 51 deletions(-) diff --git a/benchmarks/opencl/vecadd/main.cc b/benchmarks/opencl/vecadd/main.cc index 237924ba..68c9675a 100644 --- a/benchmarks/opencl/vecadd/main.cc +++ b/benchmarks/opencl/vecadd/main.cc @@ -30,28 +30,6 @@ _ret; \ }) -/*#include -#ifdef __cplusplus -extern "C" { -#endif -int _pocl_register_kernel(const char* name, const void* pfn, uint32_t num_args, uint32_t num_locals, const uint8_t* arg_types, const uint32_t* local_sizes); -void _pocl_kernel_vecadd_workgroup(uint8_t* args, uint8_t*, uint32_t, uint32_t, uint32_t); -#ifdef __cplusplus -} -#endif - -namespace { -class auto_register_kernel_t { -public: - auto_register_kernel_t() { - static uint8_t arg_types[] = {1, 1, 1}; - static uint32_t local_sizes[] = {}; - _pocl_register_kernel("vecadd", (void*)_pocl_kernel_vecadd_workgroup, 3, 0, arg_types, local_sizes); - } -}; -static auto_register_kernel_t __x__; -}*/ - int exitcode = 0; cl_context context = NULL; cl_command_queue commandQueue = NULL; diff --git a/driver/include/vortex.h b/driver/include/vortex.h index d2a00a3f..a9597253 100644 --- a/driver/include/vortex.h +++ b/driver/include/vortex.h @@ -58,10 +58,10 @@ int vx_start(vx_device_h hdevice); int vx_ready_wait(vx_device_h hdevice, long long timeout); // set device constant registers -int vx_csr_set(vx_device_h hdevice, int core, int address, int value); +int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value); // get device constant registers -int vx_csr_get(vx_device_h hdevice, int core, int address, int* value); +int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value); ////////////////////////////// UTILITY FUNCIONS /////////////////////////////// diff --git a/driver/opae/vortex.cpp b/driver/opae/vortex.cpp index baac1204..07e0385c 100755 --- a/driver/opae/vortex.cpp +++ b/driver/opae/vortex.cpp @@ -53,10 +53,10 @@ typedef struct vx_device_ { fpga_handle fpga; size_t mem_allocation; - int implementation_id; - int num_cores; - int num_warps; - int num_threads; + unsigned implementation_id; + unsigned num_cores; + unsigned num_warps; + unsigned num_threads; } vx_device_t; typedef struct vx_buffer_ { @@ -181,6 +181,9 @@ extern int vx_dev_open(vx_device_h* hdevice) { fpgaClose(accel_handle); return ret; } + + fprintf(stdout, "DEVCAPS: version=%d, num_cores=%d, num_warps=%d, num_threads=%d\n", + device->implementation_id, device->num_cores, device->num_warps, device->num_threads); } #ifdef SCOPE @@ -208,6 +211,29 @@ extern int vx_dev_close(vx_device_h hdevice) { vx_scope_stop(device->fpga, 0); #endif + { + // Dump performance stats + uint64_t instrs, cycles; + unsigned value; + + int ret = 0; + ret |= vx_csr_get(hdevice, 0, CSR_INSTR_H, &value); + instrs = value; + ret |= vx_csr_get(hdevice, 0, CSR_INSTR_L, &value); + instrs = (instrs << 32) | value; + + ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_H, &value); + cycles = value; + ret |= vx_csr_get(hdevice, 0, CSR_CYCLE_L, &value); + cycles = (cycles << 32) | value; + + float IPC = (float)(double(instrs) / double(cycles)); + + fprintf(stdout, "PERF: instrs=%ld, cycles=%ld, IPC=%f\n", instrs, cycles, IPC); + + assert(ret == 0); + } + fpgaClose(device->fpga); free(device); @@ -468,7 +494,7 @@ extern int vx_start(vx_device_h hdevice) { } // set device constant registers -extern int vx_csr_set(vx_device_h hdevice, int core, int address, int value) { +extern int vx_csr_set(vx_device_h hdevice, int core, int address, unsigned value) { if (nullptr == hdevice) return -1; @@ -488,7 +514,7 @@ extern int vx_csr_set(vx_device_h hdevice, int core, int address, int value) { } // get device constant registers -extern int vx_csr_get(vx_device_h hdevice, int core, int address, int* value) { +extern int vx_csr_get(vx_device_h hdevice, int core, int address, unsigned* value) { if (nullptr == hdevice || nullptr == value) return -1; @@ -510,7 +536,7 @@ extern int vx_csr_get(vx_device_h hdevice, int core, int address, int* value) { uint64_t value64; CHECK_RES(fpgaReadMMIO64(device->fpga, 0, MMIO_CSR_READ, &value64)); - *value = (int)value64; + *value = (unsigned)value64; return 0; } \ No newline at end of file diff --git a/driver/tests/demo/kernel.bin b/driver/tests/demo/kernel.bin index aea7c0615c62b4a6f8e72b230346e4d7ff1681dd..06939d4c46190f07fb214341beca87cb3a6ec952 100644 GIT binary patch delta 337 zcmZ9GF-yZx6h^-!@1+C;+diArQbn37W>CaXItdYs;x33T6*`3qMg0S>v{BdaL_0Y9 z2ZHF}(5l^BI}5rBT|{tEUphKm&T!A=p6kkUrFKOD5&G<8{y=S{Z!vwv1l)6&~|*Z%ONypkUW?alq8&qUXIoNF!mHvQ3hgHU7usROiFUUa;SH7 zxO4z9%z>FE-Y@BoxKK9>uW#cLS#f89SEuAdvJr^0tw4OL`?Dlqh7q{Nw>OS0MPPf5 tSBIf8LIQE9mCQuh9xMM=`S?M*&rWov!9V2e6u`xi-i`AX*GSg{{{yW|SF8X4 delta 300 zcmX?NI>$7AIx7Ri|`gjod`vKd$zgj)|D5^iHWY|OUIVKPwN zdxi!paUdpJuzNctU+or zI|D;<2Rnl~D?JL&s6` diff --git a/hw/opae/vortex_afu.sv b/hw/opae/vortex_afu.sv index 89ee968a..5f13fd77 100644 --- a/hw/opae/vortex_afu.sv +++ b/hw/opae/vortex_afu.sv @@ -881,7 +881,6 @@ assign vx_csr_io_req_rw = (STATE_CSR_WRITE == state); assign vx_csr_io_req_addr = cmd_csr_addr; assign vx_csr_io_req_data = cmd_csr_wdata; -assign cmd_csr_rdata = vx_csr_io_rsp_data; assign vx_csr_io_rsp_ready = 1; assign cmd_csr_done = (STATE_CSR_WRITE == state) ? vx_csr_io_req_ready : vx_csr_io_rsp_valid; @@ -890,6 +889,7 @@ always_ff @(posedge clk) begin if (SoftReset) begin csr_io_req_sent <= 0; + cmd_csr_rdata <= 0; end else begin if (vx_csr_io_req_valid && vx_csr_io_req_ready) begin @@ -898,6 +898,11 @@ begin if (cmd_csr_done) begin csr_io_req_sent <= 0; end + if ((STATE_CSR_READ == state) + && vx_csr_io_rsp_ready + && vx_csr_io_rsp_valid) begin + cmd_csr_rdata <= vx_csr_io_rsp_data; + end end end diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index b0d0c20f..39c1334f 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -119,7 +119,7 @@ module VX_alu_unit ( VX_mult #( .WIDTHA(33), .WIDTHB(33), - .WIDTHP(64), + .WIDTHP(66), .SIGNED(1), .PIPELINE(`MUL_LATENCY) ) multiplier ( diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v index 5703d9ac..84dafa8c 100644 --- a/hw/rtl/VX_csr_arb.v +++ b/hw/rtl/VX_csr_arb.v @@ -18,24 +18,21 @@ module VX_csr_arb ( `UNUSED_VAR (clk) `UNUSED_VAR (reset) - wire pick_core = (| csr_core_req_if.valid); - - // Which request to pick - assign issued_csr_req_if.is_io = !pick_core; + wire pick_core = (| csr_core_req_if.valid); // Mux between core and io assign issued_csr_req_if.valid = pick_core ? csr_core_req_if.valid : {`NUM_THREADS{csr_io_req_if.valid}}; assign issued_csr_req_if.is_csr = pick_core ? csr_core_req_if.is_csr : 1'b1; assign issued_csr_req_if.alu_op = pick_core ? csr_core_req_if.alu_op : (csr_io_req_if.rw ? `ALU_CSR_RW : `ALU_CSR_RS); - assign issued_csr_req_if.csr_address = pick_core ? csr_core_req_if.csr_address : csr_io_req_if.addr; - assign issued_csr_req_if.csr_mask = pick_core ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); - - assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core); - - // Core arguments - assign issued_csr_req_if.warp_num = csr_core_req_if.warp_num; + assign issued_csr_req_if.csr_address = pick_core ? csr_core_req_if.csr_address : csr_io_req_if.addr; + assign issued_csr_req_if.csr_immed = pick_core ? csr_core_req_if.csr_immed : 0; + assign issued_csr_req_if.csr_mask = pick_core ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); + assign issued_csr_req_if.is_io = !pick_core; + assign issued_csr_req_if.warp_num = csr_core_req_if.warp_num; assign issued_csr_req_if.rd = csr_core_req_if.rd; - assign issued_csr_req_if.wb = csr_core_req_if.wb; + assign issued_csr_req_if.wb = csr_core_req_if.wb; + + assign csr_io_req_if.ready = !(csr_pipe_stall || pick_core); // Core Writeback assign csr_wb_if.valid = csr_pipe_rsp_if.valid & {`NUM_THREADS{~csr_pipe_rsp_if.is_io}}; diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index dd80a811..04185d40 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -38,7 +38,6 @@ module VX_csr_pipe #( .wb_valid (| writeback_if.valid) ); - // wire hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; wire car_hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; assign csr_read_data = car_hazard ? csr_updated_data_s2 : csr_read_data_unqual; diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 0c8d4410..1c001482 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -104,7 +104,7 @@ module VX_decode( assign is_lui = (curr_opcode == `INST_LUI); assign is_auipc = (curr_opcode == `INST_AUIPC); assign is_csr = (curr_opcode == `INST_SYS) && (func3 != 0); - assign is_csr_immed = (is_csr) && (func3[2] == 1); + assign is_csr_immed = is_csr && (func3[2] == 1); assign is_gpgpu = (curr_opcode == `INST_GPGPU); diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index 5c7c628d..aed5b7e5 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -30,7 +30,6 @@ module VX_gpr_stage ( wire is_jal = bckE_req_if.is_jal; `DEBUG_END - assign csr_req_if.is_io = 1'b0; // GPR only issues csr requests coming from core VX_gpr_read_if gpr_read_if(); diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index 09da8dd8..f32aeb13 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -35,7 +35,7 @@ module VX_divide #( quartus_div.lpm_widthd = WIDTHD, quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", - quartus_div.lpm_hint = "LPM_REMAINDERPOSITIVE=FALSE,MAXIMIZE_SPEED=9", + quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", quartus_div.lpm_pipeline = PIPELINE; `else diff --git a/hw/rtl/libs/VX_mult.v b/hw/rtl/libs/VX_mult.v index 466f4213..16d47d6d 100644 --- a/hw/rtl/libs/VX_mult.v +++ b/hw/rtl/libs/VX_mult.v @@ -23,9 +23,9 @@ module VX_mult #( .dataa (dataa), .datab (datab), .result (result), + .sclr (reset), .aclr (1'b0), .clken (1'b1), - .sclr (1'b0), .sum (1'b0) ); @@ -35,7 +35,7 @@ module VX_mult #( quartus_mult.lpm_widthp = WIDTHP, quartus_mult.lpm_representation = SIGNED ? "SIGNED" : "UNSIGNED", quartus_mult.lpm_pipeline = PIPELINE, - quartus_mult.lpm_hint = "MAXIMIZE_SPEED=9"; + quartus_mult.lpm_hint = "DEDICATED_MULTIPLIER_CIRCUITRY=YES,MAXIMIZE_SPEED=9"; `else wire [WIDTHP-1:0] result_unqual; From ba43e2d33a16476c4032e6f1d518e6190a4e422e Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Wed, 1 Jul 2020 09:39:53 -0700 Subject: [PATCH 13/22] LKG FPGA build - Passed basic, demo, vecadd kernels --- RELEASE | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 RELEASE diff --git a/RELEASE b/RELEASE new file mode 100644 index 00000000..48ae100a --- /dev/null +++ b/RELEASE @@ -0,0 +1,4 @@ + +Release Notes! + +* 07/01/2020 - LKG FPGA build - Passed basic, demo, vecadd kernels. \ No newline at end of file From c5a64a0eed9687b291ebf06adeda992679d312ee Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 2 Jul 2020 19:31:55 -0700 Subject: [PATCH 14/22] interfaces refactoring --- benchmarks/opencl/vecadd/main.cc | 2 +- driver/rtlsim/Makefile | 2 +- driver/tests/basic/Makefile | 2 +- driver/tests/demo/Makefile | 2 +- hw/rtl/VX_alu_unit.v | 2 +- hw/rtl/VX_core.v | 130 +++++++++++------------ hw/rtl/VX_dcache_arb.v | 38 +++---- hw/rtl/VX_decode.v | 6 +- hw/rtl/VX_exec_unit.v | 25 +++-- hw/rtl/VX_fetch.v | 8 +- hw/rtl/VX_icache_stage.v | 56 +++++----- hw/rtl/VX_lsu_unit.v | 52 ++++----- hw/rtl/VX_mem_unit.v | 130 +++++++++++------------ hw/rtl/VX_pipeline.v | 44 ++++---- hw/rtl/VX_scheduler.v | 1 + hw/rtl/VX_warp_sched.v | 4 +- hw/rtl/interfaces/VX_backend_req_if.v | 8 +- hw/rtl/interfaces/VX_branch_rsp_if.v | 2 +- hw/rtl/interfaces/VX_cache_core_req_if.v | 14 +-- hw/rtl/interfaces/VX_cache_core_rsp_if.v | 8 +- hw/rtl/interfaces/VX_cache_dram_req_if.v | 14 +-- hw/rtl/interfaces/VX_cache_dram_rsp_if.v | 8 +- hw/rtl/interfaces/VX_cache_snp_req_if.v | 10 +- hw/rtl/interfaces/VX_cache_snp_rsp_if.v | 6 +- hw/rtl/interfaces/VX_inst_meta_if.v | 6 +- hw/rtl/interfaces/VX_jal_rsp_if.v | 2 +- hw/rtl/interfaces/VX_join_if.v | 2 +- hw/rtl/pipe_regs/VX_f_d_reg.v | 4 +- hw/rtl/pipe_regs/VX_i_d_reg.v | 4 +- 29 files changed, 295 insertions(+), 297 deletions(-) diff --git a/benchmarks/opencl/vecadd/main.cc b/benchmarks/opencl/vecadd/main.cc index 68c9675a..3b6f889b 100644 --- a/benchmarks/opencl/vecadd/main.cc +++ b/benchmarks/opencl/vecadd/main.cc @@ -4,7 +4,7 @@ #include #include -#define SIZE 4 +#define SIZE 4096 #define NUM_WORK_GROUPS 2 #define KERNEL_NAME "vecadd" diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 82ab979b..19b39484 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG=1 -#AFU=1 +AFU=1 CFLAGS += -fPIC diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile index a3792edc..71e38862 100644 --- a/driver/tests/basic/Makefile +++ b/driver/tests/basic/Makefile @@ -38,7 +38,7 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 4096 run-ase: $(PROJECT) ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 diff --git a/driver/tests/demo/Makefile b/driver/tests/demo/Makefile index 0368e5b3..bfd6bec0 100644 --- a/driver/tests/demo/Makefile +++ b/driver/tests/demo/Makefile @@ -36,7 +36,7 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 128 run-ase: $(PROJECT) ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index 39c1334f..b0d0c20f 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -119,7 +119,7 @@ module VX_alu_unit ( VX_mult #( .WIDTHA(33), .WIDTHB(33), - .WIDTHP(66), + .WIDTHP(64), .SIGNED(1), .PIPELINE(`MUL_LATENCY) ) multiplier ( diff --git a/hw/rtl/VX_core.v b/hw/rtl/VX_core.v index 7d6dc7a1..c437c398 100644 --- a/hw/rtl/VX_core.v +++ b/hw/rtl/VX_core.v @@ -97,18 +97,18 @@ module VX_core #( .DRAM_TAG_WIDTH(`DDRAM_TAG_WIDTH) ) dcache_dram_rsp_if(); - assign D_dram_req_valid = dcache_dram_req_if.dram_req_valid; - assign D_dram_req_rw = dcache_dram_req_if.dram_req_rw; - assign D_dram_req_byteen= dcache_dram_req_if.dram_req_byteen; - assign D_dram_req_addr = dcache_dram_req_if.dram_req_addr; - assign D_dram_req_data = dcache_dram_req_if.dram_req_data; - assign D_dram_req_tag = dcache_dram_req_if.dram_req_tag; - assign dcache_dram_req_if.dram_req_ready = D_dram_req_ready; + assign D_dram_req_valid = dcache_dram_req_if.valid; + assign D_dram_req_rw = dcache_dram_req_if.rw; + assign D_dram_req_byteen= dcache_dram_req_if.byteen; + assign D_dram_req_addr = dcache_dram_req_if.addr; + assign D_dram_req_data = dcache_dram_req_if.data; + assign D_dram_req_tag = dcache_dram_req_if.tag; + assign dcache_dram_req_if.ready = D_dram_req_ready; - assign dcache_dram_rsp_if.dram_rsp_valid = D_dram_rsp_valid; - assign dcache_dram_rsp_if.dram_rsp_data = D_dram_rsp_data; - assign dcache_dram_rsp_if.dram_rsp_tag = D_dram_rsp_tag; - assign D_dram_rsp_ready = dcache_dram_rsp_if.dram_rsp_ready; + assign dcache_dram_rsp_if.valid = D_dram_rsp_valid; + assign dcache_dram_rsp_if.data = D_dram_rsp_data; + assign dcache_dram_rsp_if.tag = D_dram_rsp_tag; + assign D_dram_rsp_ready = dcache_dram_rsp_if.ready; VX_cache_core_req_if #( .NUM_REQUESTS(`DNUM_REQUESTS), @@ -124,18 +124,18 @@ module VX_core #( .CORE_TAG_ID_BITS(`DCORE_TAG_ID_BITS) ) core_dcache_rsp_if(), arb_dcache_rsp_if(), arb_io_rsp_if(); - assign io_req_valid = arb_io_req_if.core_req_valid[0]; - assign io_req_rw = arb_io_req_if.core_req_rw[0]; - assign io_req_byteen = arb_io_req_if.core_req_byteen[0]; - assign io_req_addr = arb_io_req_if.core_req_addr[0]; - assign io_req_data = arb_io_req_if.core_req_data[0]; - assign io_req_tag = arb_io_req_if.core_req_tag[0]; - assign arb_io_req_if.core_req_ready = io_req_ready; + assign io_req_valid = arb_io_req_if.valid[0]; + assign io_req_rw = arb_io_req_if.rw[0]; + assign io_req_byteen = arb_io_req_if.byteen[0]; + assign io_req_addr = arb_io_req_if.addr[0]; + assign io_req_data = arb_io_req_if.data[0]; + assign io_req_tag = arb_io_req_if.tag[0]; + assign arb_io_req_if.ready = io_req_ready; - assign arb_io_rsp_if.core_rsp_valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; - assign arb_io_rsp_if.core_rsp_data[0] = io_rsp_data; - assign arb_io_rsp_if.core_rsp_tag = io_rsp_tag; - assign io_rsp_ready = arb_io_rsp_if.core_rsp_ready; + assign arb_io_rsp_if.valid = {{(`NUM_THREADS-1){1'b0}}, io_rsp_valid}; + assign arb_io_rsp_if.data[0] = io_rsp_data; + assign arb_io_rsp_if.tag = io_rsp_tag; + assign io_rsp_ready = arb_io_rsp_if.ready; // Icache interfaces @@ -150,18 +150,18 @@ module VX_core #( .DRAM_TAG_WIDTH(`IDRAM_TAG_WIDTH) ) icache_dram_rsp_if(); - assign I_dram_req_valid = icache_dram_req_if.dram_req_valid; - assign I_dram_req_rw = icache_dram_req_if.dram_req_rw; - assign I_dram_req_byteen= icache_dram_req_if.dram_req_byteen; - assign I_dram_req_addr = icache_dram_req_if.dram_req_addr; - assign I_dram_req_data = icache_dram_req_if.dram_req_data; - assign I_dram_req_tag = icache_dram_req_if.dram_req_tag; - assign icache_dram_req_if.dram_req_ready = I_dram_req_ready; + assign I_dram_req_valid = icache_dram_req_if.valid; + assign I_dram_req_rw = icache_dram_req_if.rw; + assign I_dram_req_byteen= icache_dram_req_if.byteen; + assign I_dram_req_addr = icache_dram_req_if.addr; + assign I_dram_req_data = icache_dram_req_if.data; + assign I_dram_req_tag = icache_dram_req_if.tag; + assign icache_dram_req_if.ready = I_dram_req_ready; - assign icache_dram_rsp_if.dram_rsp_valid = I_dram_rsp_valid; - assign icache_dram_rsp_if.dram_rsp_data = I_dram_rsp_data; - assign icache_dram_rsp_if.dram_rsp_tag = I_dram_rsp_tag; - assign I_dram_rsp_ready = icache_dram_rsp_if.dram_rsp_ready; + assign icache_dram_rsp_if.valid = I_dram_rsp_valid; + assign icache_dram_rsp_if.data = I_dram_rsp_data; + assign icache_dram_rsp_if.tag = I_dram_rsp_tag; + assign I_dram_rsp_ready = icache_dram_rsp_if.ready; VX_cache_core_req_if #( .NUM_REQUESTS(`INUM_REQUESTS), @@ -189,34 +189,34 @@ module VX_core #( .reset(reset), // Dcache core request - .dcache_req_valid (core_dcache_req_if.core_req_valid), - .dcache_req_rw (core_dcache_req_if.core_req_rw), - .dcache_req_byteen (core_dcache_req_if.core_req_byteen), - .dcache_req_addr (core_dcache_req_if.core_req_addr), - .dcache_req_data (core_dcache_req_if.core_req_data), - .dcache_req_tag (core_dcache_req_if.core_req_tag), - .dcache_req_ready (core_dcache_req_if.core_req_ready), + .dcache_req_valid (core_dcache_req_if.valid), + .dcache_req_rw (core_dcache_req_if.rw), + .dcache_req_byteen (core_dcache_req_if.byteen), + .dcache_req_addr (core_dcache_req_if.addr), + .dcache_req_data (core_dcache_req_if.data), + .dcache_req_tag (core_dcache_req_if.tag), + .dcache_req_ready (core_dcache_req_if.ready), // Dcache core reponse - .dcache_rsp_valid (core_dcache_rsp_if.core_rsp_valid), - .dcache_rsp_data (core_dcache_rsp_if.core_rsp_data), - .dcache_rsp_tag (core_dcache_rsp_if.core_rsp_tag), - .dcache_rsp_ready (core_dcache_rsp_if.core_rsp_ready), + .dcache_rsp_valid (core_dcache_rsp_if.valid), + .dcache_rsp_data (core_dcache_rsp_if.data), + .dcache_rsp_tag (core_dcache_rsp_if.tag), + .dcache_rsp_ready (core_dcache_rsp_if.ready), // Dcache core request - .icache_req_valid (core_icache_req_if.core_req_valid), - .icache_req_rw (core_icache_req_if.core_req_rw), - .icache_req_byteen (core_icache_req_if.core_req_byteen), - .icache_req_addr (core_icache_req_if.core_req_addr), - .icache_req_data (core_icache_req_if.core_req_data), - .icache_req_tag (core_icache_req_if.core_req_tag), - .icache_req_ready (core_icache_req_if.core_req_ready), + .icache_req_valid (core_icache_req_if.valid), + .icache_req_rw (core_icache_req_if.rw), + .icache_req_byteen (core_icache_req_if.byteen), + .icache_req_addr (core_icache_req_if.addr), + .icache_req_data (core_icache_req_if.data), + .icache_req_tag (core_icache_req_if.tag), + .icache_req_ready (core_icache_req_if.ready), // Dcache core reponse - .icache_rsp_valid (core_icache_rsp_if.core_rsp_valid), - .icache_rsp_data (core_icache_rsp_if.core_rsp_data), - .icache_rsp_tag (core_icache_rsp_if.core_rsp_tag), - .icache_rsp_ready (core_icache_rsp_if.core_rsp_ready), + .icache_rsp_valid (core_icache_rsp_if.valid), + .icache_rsp_data (core_icache_rsp_if.data), + .icache_rsp_tag (core_icache_rsp_if.tag), + .icache_rsp_ready (core_icache_rsp_if.ready), // CSR I/O request .csr_io_req_valid (csr_io_req_valid), @@ -246,15 +246,15 @@ module VX_core #( .SNP_TAG_WIDTH(`DSNP_TAG_WIDTH) ) dcache_snp_rsp_if(); - assign dcache_snp_req_if.snp_req_valid = snp_req_valid; - assign dcache_snp_req_if.snp_req_addr = snp_req_addr; - assign dcache_snp_req_if.snp_req_invalidate = snp_req_invalidate; - assign dcache_snp_req_if.snp_req_tag = snp_req_tag; - assign snp_req_ready = dcache_snp_req_if.snp_req_ready; + assign dcache_snp_req_if.valid = snp_req_valid; + assign dcache_snp_req_if.addr = snp_req_addr; + assign dcache_snp_req_if.invalidate = snp_req_invalidate; + assign dcache_snp_req_if.tag = snp_req_tag; + assign snp_req_ready = dcache_snp_req_if.ready; - assign snp_rsp_valid = dcache_snp_rsp_if.snp_rsp_valid; - assign snp_rsp_tag = dcache_snp_rsp_if.snp_rsp_tag; - assign dcache_snp_rsp_if.snp_rsp_ready = snp_rsp_ready; + assign snp_rsp_valid = dcache_snp_rsp_if.valid; + assign snp_rsp_tag = dcache_snp_rsp_if.tag; + assign dcache_snp_rsp_if.ready = snp_rsp_ready; VX_mem_unit #( .CORE_ID(CORE_ID) @@ -284,8 +284,8 @@ module VX_core #( ); // select io address - wire is_io_addr = ({core_dcache_req_if.core_req_addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); - wire io_select = (| core_dcache_req_if.core_req_valid) ? is_io_addr : 0; + wire is_io_addr = ({core_dcache_req_if.addr[0], 2'b0} >= `IO_BUS_BASE_ADDR); + wire io_select = (| core_dcache_req_if.valid) ? is_io_addr : 0; VX_dcache_arb dcache_io_arb ( .req_select (io_select), diff --git a/hw/rtl/VX_dcache_arb.v b/hw/rtl/VX_dcache_arb.v index 264c91e1..1431be60 100644 --- a/hw/rtl/VX_dcache_arb.v +++ b/hw/rtl/VX_dcache_arb.v @@ -21,28 +21,28 @@ module VX_dcache_arb ( // output response VX_cache_core_rsp_if out_core_rsp_if ); - assign out0_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{~req_select}}; - assign out0_core_req_if.core_req_rw = in_core_req_if.core_req_rw; - assign out0_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen; - assign out0_core_req_if.core_req_addr = in_core_req_if.core_req_addr; - assign out0_core_req_if.core_req_data = in_core_req_if.core_req_data; - assign out0_core_req_if.core_req_tag = in_core_req_if.core_req_tag; + assign out0_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{~req_select}}; + assign out0_core_req_if.rw = in_core_req_if.rw; + assign out0_core_req_if.byteen = in_core_req_if.byteen; + assign out0_core_req_if.addr = in_core_req_if.addr; + assign out0_core_req_if.data = in_core_req_if.data; + assign out0_core_req_if.tag = in_core_req_if.tag; - assign out1_core_req_if.core_req_valid = in_core_req_if.core_req_valid & {`NUM_THREADS{req_select}}; - assign out1_core_req_if.core_req_rw = in_core_req_if.core_req_rw; - assign out1_core_req_if.core_req_byteen = in_core_req_if.core_req_byteen; - assign out1_core_req_if.core_req_addr = in_core_req_if.core_req_addr; - assign out1_core_req_if.core_req_data = in_core_req_if.core_req_data; - assign out1_core_req_if.core_req_tag = in_core_req_if.core_req_tag; + assign out1_core_req_if.valid = in_core_req_if.valid & {`NUM_THREADS{req_select}}; + assign out1_core_req_if.rw = in_core_req_if.rw; + assign out1_core_req_if.byteen = in_core_req_if.byteen; + assign out1_core_req_if.addr = in_core_req_if.addr; + assign out1_core_req_if.data = in_core_req_if.data; + assign out1_core_req_if.tag = in_core_req_if.tag; - assign in_core_req_if.core_req_ready = req_select ? out1_core_req_if.core_req_ready : out0_core_req_if.core_req_ready; + assign in_core_req_if.ready = req_select ? out1_core_req_if.ready : out0_core_req_if.ready; - wire rsp_select0 = (| in0_core_rsp_if.core_rsp_valid); + wire rsp_select0 = (| in0_core_rsp_if.valid); - assign out_core_rsp_if.core_rsp_valid = rsp_select0 ? in0_core_rsp_if.core_rsp_valid : in1_core_rsp_if.core_rsp_valid; - assign out_core_rsp_if.core_rsp_data = rsp_select0 ? in0_core_rsp_if.core_rsp_data : in1_core_rsp_if.core_rsp_data; - assign out_core_rsp_if.core_rsp_tag = rsp_select0 ? in0_core_rsp_if.core_rsp_tag : in1_core_rsp_if.core_rsp_tag; - assign in0_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && rsp_select0; - assign in1_core_rsp_if.core_rsp_ready = out_core_rsp_if.core_rsp_ready && !rsp_select0; + assign out_core_rsp_if.valid = rsp_select0 ? in0_core_rsp_if.valid : in1_core_rsp_if.valid; + assign out_core_rsp_if.data = rsp_select0 ? in0_core_rsp_if.data : in1_core_rsp_if.data; + assign out_core_rsp_if.tag = rsp_select0 ? in0_core_rsp_if.tag : in1_core_rsp_if.tag; + assign in0_core_rsp_if.ready = out_core_rsp_if.ready && rsp_select0; + assign in1_core_rsp_if.ready = out_core_rsp_if.ready && !rsp_select0; endmodule \ No newline at end of file diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index 1c001482..dd7e1d1c 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -12,7 +12,7 @@ module VX_decode( ); wire in_valid = (| fd_inst_meta_de.valid); wire[31:0] in_instruction = fd_inst_meta_de.instruction; - wire[31:0] in_curr_PC = fd_inst_meta_de.inst_pc; + wire[31:0] in_curr_PC = fd_inst_meta_de.curr_PC; wire[`NW_BITS-1:0] in_warp_num = fd_inst_meta_de.warp_num; assign frE_to_bckE_req_if.curr_PC = in_curr_PC; @@ -114,8 +114,8 @@ module VX_decode( assign is_split = is_gpgpu && (func3 == 2); // Goes to BE assign is_join = is_gpgpu && (func3 == 3); // Doesn't go to BE - assign join_if.is_join = is_join && in_valid; - assign join_if.join_warp_num = in_warp_num; + assign join_if.is_join = is_join && in_valid; + assign join_if.warp_num = in_warp_num; assign frE_to_bckE_req_if.is_wspawn = is_wspawn; assign frE_to_bckE_req_if.is_tmc = is_tmc; diff --git a/hw/rtl/VX_exec_unit.v b/hw/rtl/VX_exec_unit.v index 51f2da61..d89b4e48 100644 --- a/hw/rtl/VX_exec_unit.v +++ b/hw/rtl/VX_exec_unit.v @@ -61,8 +61,7 @@ module VX_exec_unit ( end endgenerate - wire internal_stall; - assign internal_stall = (| alu_stall); + wire internal_stall = (| alu_stall); assign delay = no_slot_exec || internal_stall; @@ -116,15 +115,15 @@ module VX_exec_unit ( assign inst_exec_wb_if.curr_PC = in_curr_PC; // Jal rsp - assign jal_rsp_temp_if.jal = in_jal; - assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); - assign jal_rsp_temp_if.jal_warp_num = exec_unit_req_if.warp_num; + assign jal_rsp_temp_if.jal = in_jal; + assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); + assign jal_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; // Branch rsp - assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); - assign branch_rsp_temp_if.branch_dir = temp_branch_dir; - assign branch_rsp_temp_if.branch_warp_num = exec_unit_req_if.warp_num; - assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset + assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); + assign branch_rsp_temp_if.branch_dir = temp_branch_dir; + assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; + assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset VX_generic_register #( .N(33 + `NW_BITS-1 + 1) @@ -133,8 +132,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({jal_rsp_temp_if.jal, jal_rsp_temp_if.jal_dest, jal_rsp_temp_if.jal_warp_num}), - .out ({jal_rsp_if.jal , jal_rsp_if.jal_dest , jal_rsp_if.jal_warp_num}) + .in ({jal_rsp_temp_if.jal, jal_rsp_temp_if.jal_dest, jal_rsp_temp_if.warp_num}), + .out ({jal_rsp_if.jal , jal_rsp_if.jal_dest , jal_rsp_if.warp_num}) ); VX_generic_register #( @@ -144,8 +143,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({branch_rsp_temp_if.valid_branch, branch_rsp_temp_if.branch_dir, branch_rsp_temp_if.branch_warp_num, branch_rsp_temp_if.branch_dest}), - .out ({branch_rsp_if.valid_branch , branch_rsp_if.branch_dir , branch_rsp_if.branch_warp_num , branch_rsp_if.branch_dest }) + .in ({branch_rsp_temp_if.valid_branch, branch_rsp_temp_if.branch_dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.branch_dest}), + .out ({branch_rsp_if.valid_branch , branch_rsp_if.branch_dir , branch_rsp_if.warp_num , branch_rsp_if.branch_dest }) ); endmodule : VX_exec_unit \ No newline at end of file diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index 1247dac0..e17443f4 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -57,7 +57,7 @@ module VX_fetch ( // Join .is_join (join_if.is_join), - .join_warp_num (join_if.join_warp_num), + .join_warp_num (join_if.warp_num), // Split .is_split (warp_ctl_if.is_split), @@ -70,13 +70,13 @@ module VX_fetch ( // JAL .jal (jal_rsp_if.jal), .jal_dest (jal_rsp_if.jal_dest), - .jal_warp_num (jal_rsp_if.jal_warp_num), + .jal_warp_num (jal_rsp_if.warp_num), // Branch .branch_valid (branch_rsp_if.valid_branch), .branch_dir (branch_rsp_if.branch_dir), .branch_dest (branch_rsp_if.branch_dest), - .branch_warp_num (branch_rsp_if.branch_warp_num), + .branch_warp_num (branch_rsp_if.warp_num), // Outputs .thread_mask (thread_mask), @@ -89,7 +89,7 @@ module VX_fetch ( assign fe_inst_meta_fi.warp_num = warp_num; assign fe_inst_meta_fi.valid = thread_mask; assign fe_inst_meta_fi.instruction = 32'h0; - assign fe_inst_meta_fi.inst_pc = warp_pc; + assign fe_inst_meta_fi.curr_PC = warp_pc; `DEBUG_BEGIN wire start_mat_add = scheduled_warp && (warp_pc == 32'h80000ed8) && (warp_num == 0); diff --git a/hw/rtl/VX_icache_stage.v b/hw/rtl/VX_icache_stage.v index 3985fe05..5232f943 100644 --- a/hw/rtl/VX_icache_stage.v +++ b/hw/rtl/VX_icache_stage.v @@ -25,10 +25,10 @@ module VX_icache_stage #( wire [`LOG2UP(`ICREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire mrq_full; - wire mrq_push = icache_req_if.core_req_valid && icache_req_if.core_req_ready; - wire mrq_pop = icache_rsp_if.core_rsp_valid && icache_rsp_if.core_rsp_ready; + wire mrq_push = icache_req_if.valid && icache_req_if.ready; + wire mrq_pop = icache_rsp_if.valid && icache_rsp_if.ready; - assign mrq_read_addr = icache_rsp_if.core_rsp_tag[0][`LOG2UP(`ICREQ_SIZE)-1:0]; + assign mrq_read_addr = icache_rsp_if.tag[0][`LOG2UP(`ICREQ_SIZE)-1:0]; VX_indexable_queue #( .DATAW (`LOG2UP(`ICREQ_SIZE) + 32 + `NW_BITS), @@ -36,13 +36,13 @@ module VX_icache_stage #( ) mem_req_queue ( .clk (clk), .reset (reset), - .write_data ({mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num}), + .write_data ({mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num}), .write_addr (mrq_write_addr), .push (mrq_push), .full (mrq_full), .pop (mrq_pop), .read_addr (mrq_read_addr), - .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num}), + .read_data ({dbg_mrq_write_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num}), `UNUSED_PIN (empty) ); @@ -56,48 +56,48 @@ module VX_icache_stage #( end // Icache Request - assign icache_req_if.core_req_valid = valid_inst && !mrq_full; - assign icache_req_if.core_req_rw = 0; - assign icache_req_if.core_req_byteen = 4'b1111; - assign icache_req_if.core_req_addr = fe_inst_meta_fi.inst_pc[31:2]; - assign icache_req_if.core_req_data = 0; + assign icache_req_if.valid = valid_inst && !mrq_full; + assign icache_req_if.rw = 0; + assign icache_req_if.byteen = 4'b1111; + assign icache_req_if.addr = fe_inst_meta_fi.curr_PC[31:2]; + assign icache_req_if.data = 0; // Can't accept new request - assign icache_stage_delay = mrq_full || !icache_req_if.core_req_ready; + assign icache_stage_delay = mrq_full || !icache_req_if.ready; `ifdef DBG_CORE_REQ_INFO - assign icache_req_if.core_req_tag = {fe_inst_meta_fi.inst_pc, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr}; + assign icache_req_if.tag = {fe_inst_meta_fi.curr_PC, 2'b1, 5'b0, fe_inst_meta_fi.warp_num, mrq_write_addr}; `else - assign icache_req_if.core_req_tag = mrq_write_addr; + assign icache_req_if.tag = mrq_write_addr; `endif - assign fe_inst_meta_id.instruction = icache_rsp_if.core_rsp_valid ? icache_rsp_if.core_rsp_data[0] : 0; - assign fe_inst_meta_id.valid = icache_rsp_if.core_rsp_valid ? valid_threads[fe_inst_meta_id.warp_num] : 0; + assign fe_inst_meta_id.instruction = icache_rsp_if.valid ? icache_rsp_if.data[0] : 0; + assign fe_inst_meta_id.valid = icache_rsp_if.valid ? valid_threads[fe_inst_meta_id.warp_num] : 0; assign icache_stage_response = mrq_pop; assign icache_stage_wid = fe_inst_meta_id.warp_num; // Can't accept new response - assign icache_rsp_if.core_rsp_ready = !total_freeze; + assign icache_rsp_if.ready = !total_freeze; - `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_if.core_req_valid); + `SCOPE_ASSIGN(scope_icache_req_valid, icache_req_if.valid); `SCOPE_ASSIGN(scope_icache_req_warp_num, fe_inst_meta_fi.warp_num); - `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_if.core_req_addr, 2'b0}); - `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_if.core_req_tag); - `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_if.core_req_ready); + `SCOPE_ASSIGN(scope_icache_req_addr, {icache_req_if.addr, 2'b0}); + `SCOPE_ASSIGN(scope_icache_req_tag, icache_req_if.tag); + `SCOPE_ASSIGN(scope_icache_req_ready, icache_req_if.ready); - `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_if.core_rsp_valid); - `SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_if.core_rsp_data); - `SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_if.core_rsp_tag); - `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.core_rsp_ready); + `SCOPE_ASSIGN(scope_icache_rsp_valid, icache_rsp_if.valid); + `SCOPE_ASSIGN(scope_icache_rsp_data, icache_rsp_if.data); + `SCOPE_ASSIGN(scope_icache_rsp_tag, icache_rsp_if.tag); + `SCOPE_ASSIGN(scope_icache_rsp_ready, icache_rsp_if.ready); `ifdef DBG_PRINT_CORE_ICACHE always @(posedge clk) begin - if (icache_req_if.core_req_valid && icache_req_if.core_req_ready) begin - $display("%t: I%0d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.inst_pc, fe_inst_meta_fi.warp_num); + if (icache_req_if.valid && icache_req_if.ready) begin + $display("%t: I%0d$ req: tag=%0h, pc=%0h, warp=%0d", $time, CORE_ID, mrq_write_addr, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num); end - if (icache_rsp_if.core_rsp_valid && icache_rsp_if.core_rsp_ready) begin - $display("%t: I%0d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.inst_pc, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction); + if (icache_rsp_if.valid && icache_rsp_if.ready) begin + $display("%t: I%0d$ rsp: tag=%0h, pc=%0h, warp=%0d, instr=%0h", $time, CORE_ID, mrq_read_addr, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.instruction); end end `endif diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 640640b3..4482ab75 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -83,14 +83,14 @@ module VX_lsu_unit #( wire [`LOG2UP(`DCREQ_SIZE)-1:0] mrq_write_addr, mrq_read_addr, dbg_mrq_write_addr; wire mrq_full; - wire mrq_push = (| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready + wire mrq_push = (| dcache_req_if.valid) && dcache_req_if.ready && (0 == core_req_rw); // only push read requests - wire mrq_pop_part = (| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready; + wire mrq_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready; - assign mrq_read_addr = dcache_rsp_if.core_rsp_tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; + assign mrq_read_addr = dcache_rsp_if.tag[0][`LOG2UP(`DCREQ_SIZE)-1:0]; - wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.core_rsp_valid; + wire [`NUM_THREADS-1:0] mem_rsp_mask_upd = mem_rsp_mask[mrq_read_addr] & ~dcache_rsp_if.valid; wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_upd); @@ -122,20 +122,20 @@ module VX_lsu_unit #( // Core Request - assign dcache_req_if.core_req_valid = use_valid & {`NUM_THREADS{~mrq_full}}; - assign dcache_req_if.core_req_rw = {`NUM_THREADS{core_req_rw}}; - assign dcache_req_if.core_req_byteen= mem_req_byteen; - assign dcache_req_if.core_req_addr = mem_req_addr; - assign dcache_req_if.core_req_data = mem_req_data; + assign dcache_req_if.valid = use_valid & {`NUM_THREADS{~mrq_full}}; + assign dcache_req_if.rw = {`NUM_THREADS{core_req_rw}}; + assign dcache_req_if.byteen= mem_req_byteen; + assign dcache_req_if.addr = mem_req_addr; + assign dcache_req_if.data = mem_req_data; `ifdef DBG_CORE_REQ_INFO - assign dcache_req_if.core_req_tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; + assign dcache_req_if.tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; `else - assign dcache_req_if.core_req_tag = mrq_write_addr; + assign dcache_req_if.tag = mrq_write_addr; `endif // Can't accept new request - assign delay = mrq_full || !dcache_req_if.core_req_ready; + assign delay = mrq_full || !dcache_req_if.ready; // Core Response @@ -143,7 +143,7 @@ module VX_lsu_unit #( wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; for (i = 0; i < `NUM_THREADS; ++i) begin - assign rsp_data_shifted[i] = (dcache_rsp_if.core_rsp_data[i] >> mem_rsp_offset[i]); + assign rsp_data_shifted[i] = (dcache_rsp_if.data[i] >> mem_rsp_offset[i]); always @(*) begin case (core_rsp_mem_read) `BYTE_EN_SB: core_rsp_data[i] = rsp_data_shifted[i][7] ? (rsp_data_shifted[i] | 32'hFFFFFF00) : (rsp_data_shifted[i] & 32'h000000FF); @@ -155,11 +155,11 @@ module VX_lsu_unit #( end end - assign mem_wb_if.valid = dcache_rsp_if.core_rsp_valid; + assign mem_wb_if.valid = dcache_rsp_if.valid; assign mem_wb_if.data = core_rsp_data; // Can't accept new response - assign dcache_rsp_if.core_rsp_ready = !(no_slot_mem & (|mem_wb_if_p1.valid)); + assign dcache_rsp_if.ready = !(no_slot_mem & (|mem_wb_if_p1.valid)); // From LSU to WB localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32; @@ -172,28 +172,28 @@ module VX_lsu_unit #( .out ({mem_wb_if_p1.valid, mem_wb_if_p1.data, mem_wb_if_p1.warp_num, mem_wb_if_p1.rd, mem_wb_if_p1.wb, mem_wb_if_p1.curr_PC}) ); - `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.core_req_valid); + `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid); `SCOPE_ASSIGN(scope_dcache_req_warp_num, use_warp_num); `SCOPE_ASSIGN(scope_dcache_req_curr_PC, use_pc); `SCOPE_ASSIGN(scope_dcache_req_addr, use_address); `SCOPE_ASSIGN(scope_dcache_req_rw, core_req_rw); - `SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.core_req_byteen); - `SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.core_req_data); - `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.core_req_tag); - `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.core_req_ready); + `SCOPE_ASSIGN(scope_dcache_req_byteen,dcache_req_if.byteen); + `SCOPE_ASSIGN(scope_dcache_req_data, dcache_req_if.data); + `SCOPE_ASSIGN(scope_dcache_req_tag, dcache_req_if.tag); + `SCOPE_ASSIGN(scope_dcache_req_ready, dcache_req_if.ready); - `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.core_rsp_valid); - `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.core_rsp_data); - `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.core_rsp_tag); - `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.core_rsp_ready); + `SCOPE_ASSIGN(scope_dcache_rsp_valid, dcache_rsp_if.valid); + `SCOPE_ASSIGN(scope_dcache_rsp_data, dcache_rsp_if.data); + `SCOPE_ASSIGN(scope_dcache_rsp_tag, dcache_rsp_if.tag); + `SCOPE_ASSIGN(scope_dcache_rsp_ready, dcache_rsp_if.ready); `ifdef DBG_PRINT_CORE_DCACHE always @(posedge clk) begin - if ((| dcache_req_if.core_req_valid) && dcache_req_if.core_req_ready) begin + if ((| dcache_req_if.valid) && dcache_req_if.ready) begin $display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, mem_req_byteen, mem_req_data); end - if ((| dcache_rsp_if.core_rsp_valid) && dcache_rsp_if.core_rsp_ready) begin + if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin $display("%t: D%0d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", $time, CORE_ID, mem_wb_if.valid, mrq_read_addr, mem_wb_if.curr_PC, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data); end diff --git a/hw/rtl/VX_mem_unit.v b/hw/rtl/VX_mem_unit.v index 6b3c3888..af626723 100644 --- a/hw/rtl/VX_mem_unit.v +++ b/hw/rtl/VX_mem_unit.v @@ -41,8 +41,8 @@ module VX_mem_unit # ( ) core_dcache_rsp_qual_if(), core_smem_rsp_if(); // select shared memory address - wire is_smem_addr = (({core_dcache_req_if.core_req_addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); - wire smem_select = (| core_dcache_req_if.core_req_valid) ? is_smem_addr : 0; + wire is_smem_addr = (({core_dcache_req_if.addr[0], 2'b0} - `SHARED_MEM_BASE_ADDR) <= `SCACHE_SIZE); + wire smem_select = (| core_dcache_req_if.valid) ? is_smem_addr : 0; VX_dcache_arb dcache_smem_arb ( .req_select (smem_select), @@ -84,19 +84,19 @@ module VX_mem_unit # ( .reset (reset), // Core request - .core_req_valid (core_smem_req_if.core_req_valid), - .core_req_rw (core_smem_req_if.core_req_rw), - .core_req_byteen (core_smem_req_if.core_req_byteen), - .core_req_addr (core_smem_req_if.core_req_addr), - .core_req_data (core_smem_req_if.core_req_data), - .core_req_tag (core_smem_req_if.core_req_tag), - .core_req_ready (core_smem_req_if.core_req_ready), + .core_req_valid (core_smem_req_if.valid), + .core_req_rw (core_smem_req_if.rw), + .core_req_byteen (core_smem_req_if.byteen), + .core_req_addr (core_smem_req_if.addr), + .core_req_data (core_smem_req_if.data), + .core_req_tag (core_smem_req_if.tag), + .core_req_ready (core_smem_req_if.ready), // Core response - .core_rsp_valid (core_smem_rsp_if.core_rsp_valid), - .core_rsp_data (core_smem_rsp_if.core_rsp_data), - .core_rsp_tag (core_smem_rsp_if.core_rsp_tag), - .core_rsp_ready (core_smem_rsp_if.core_rsp_ready), + .core_rsp_valid (core_smem_rsp_if.valid), + .core_rsp_data (core_smem_rsp_if.data), + .core_rsp_tag (core_smem_rsp_if.tag), + .core_rsp_ready (core_smem_rsp_if.ready), // DRAM request `UNUSED_PIN (dram_req_valid), @@ -169,46 +169,46 @@ module VX_mem_unit # ( .reset (reset), // Core req - .core_req_valid (core_dcache_req_qual_if.core_req_valid), - .core_req_rw (core_dcache_req_qual_if.core_req_rw), - .core_req_byteen (core_dcache_req_qual_if.core_req_byteen), - .core_req_addr (core_dcache_req_qual_if.core_req_addr), - .core_req_data (core_dcache_req_qual_if.core_req_data), - .core_req_tag (core_dcache_req_qual_if.core_req_tag), - .core_req_ready (core_dcache_req_qual_if.core_req_ready), + .core_req_valid (core_dcache_req_qual_if.valid), + .core_req_rw (core_dcache_req_qual_if.rw), + .core_req_byteen (core_dcache_req_qual_if.byteen), + .core_req_addr (core_dcache_req_qual_if.addr), + .core_req_data (core_dcache_req_qual_if.data), + .core_req_tag (core_dcache_req_qual_if.tag), + .core_req_ready (core_dcache_req_qual_if.ready), // Core response - .core_rsp_valid (core_dcache_rsp_qual_if.core_rsp_valid), - .core_rsp_data (core_dcache_rsp_qual_if.core_rsp_data), - .core_rsp_tag (core_dcache_rsp_qual_if.core_rsp_tag), - .core_rsp_ready (core_dcache_rsp_qual_if.core_rsp_ready), + .core_rsp_valid (core_dcache_rsp_qual_if.valid), + .core_rsp_data (core_dcache_rsp_qual_if.data), + .core_rsp_tag (core_dcache_rsp_qual_if.tag), + .core_rsp_ready (core_dcache_rsp_qual_if.ready), // DRAM request - .dram_req_valid (dcache_dram_req_if.dram_req_valid), - .dram_req_rw (dcache_dram_req_if.dram_req_rw), - .dram_req_byteen (dcache_dram_req_if.dram_req_byteen), - .dram_req_addr (dcache_dram_req_if.dram_req_addr), - .dram_req_data (dcache_dram_req_if.dram_req_data), - .dram_req_tag (dcache_dram_req_if.dram_req_tag), - .dram_req_ready (dcache_dram_req_if.dram_req_ready), + .dram_req_valid (dcache_dram_req_if.valid), + .dram_req_rw (dcache_dram_req_if.rw), + .dram_req_byteen (dcache_dram_req_if.byteen), + .dram_req_addr (dcache_dram_req_if.addr), + .dram_req_data (dcache_dram_req_if.data), + .dram_req_tag (dcache_dram_req_if.tag), + .dram_req_ready (dcache_dram_req_if.ready), // DRAM response - .dram_rsp_valid (dcache_dram_rsp_if.dram_rsp_valid), - .dram_rsp_data (dcache_dram_rsp_if.dram_rsp_data), - .dram_rsp_tag (dcache_dram_rsp_if.dram_rsp_tag), - .dram_rsp_ready (dcache_dram_rsp_if.dram_rsp_ready), + .dram_rsp_valid (dcache_dram_rsp_if.valid), + .dram_rsp_data (dcache_dram_rsp_if.data), + .dram_rsp_tag (dcache_dram_rsp_if.tag), + .dram_rsp_ready (dcache_dram_rsp_if.ready), // Snoop request - .snp_req_valid (dcache_snp_req_if.snp_req_valid), - .snp_req_addr (dcache_snp_req_if.snp_req_addr), - .snp_req_invalidate (dcache_snp_req_if.snp_req_invalidate), - .snp_req_tag (dcache_snp_req_if.snp_req_tag), - .snp_req_ready (dcache_snp_req_if.snp_req_ready), + .snp_req_valid (dcache_snp_req_if.valid), + .snp_req_addr (dcache_snp_req_if.addr), + .snp_req_invalidate (dcache_snp_req_if.invalidate), + .snp_req_tag (dcache_snp_req_if.tag), + .snp_req_ready (dcache_snp_req_if.ready), // Snoop response - .snp_rsp_valid (dcache_snp_rsp_if.snp_rsp_valid), - .snp_rsp_tag (dcache_snp_rsp_if.snp_rsp_tag), - .snp_rsp_ready (dcache_snp_rsp_if.snp_rsp_ready), + .snp_rsp_valid (dcache_snp_rsp_if.valid), + .snp_rsp_tag (dcache_snp_rsp_if.tag), + .snp_rsp_ready (dcache_snp_rsp_if.ready), // Snoop forward out `UNUSED_PIN (snp_fwdout_valid), @@ -253,34 +253,34 @@ module VX_mem_unit # ( .reset (reset), // Core request - .core_req_valid (core_icache_req_if.core_req_valid), - .core_req_rw (core_icache_req_if.core_req_rw), - .core_req_byteen (core_icache_req_if.core_req_byteen), - .core_req_addr (core_icache_req_if.core_req_addr), - .core_req_data (core_icache_req_if.core_req_data), - .core_req_tag (core_icache_req_if.core_req_tag), - .core_req_ready (core_icache_req_if.core_req_ready), + .core_req_valid (core_icache_req_if.valid), + .core_req_rw (core_icache_req_if.rw), + .core_req_byteen (core_icache_req_if.byteen), + .core_req_addr (core_icache_req_if.addr), + .core_req_data (core_icache_req_if.data), + .core_req_tag (core_icache_req_if.tag), + .core_req_ready (core_icache_req_if.ready), // Core response - .core_rsp_valid (core_icache_rsp_if.core_rsp_valid), - .core_rsp_data (core_icache_rsp_if.core_rsp_data), - .core_rsp_tag (core_icache_rsp_if.core_rsp_tag), - .core_rsp_ready (core_icache_rsp_if.core_rsp_ready), + .core_rsp_valid (core_icache_rsp_if.valid), + .core_rsp_data (core_icache_rsp_if.data), + .core_rsp_tag (core_icache_rsp_if.tag), + .core_rsp_ready (core_icache_rsp_if.ready), // DRAM Req - .dram_req_valid (icache_dram_req_if.dram_req_valid), - .dram_req_rw (icache_dram_req_if.dram_req_rw), - .dram_req_byteen (icache_dram_req_if.dram_req_byteen), - .dram_req_addr (icache_dram_req_if.dram_req_addr), - .dram_req_data (icache_dram_req_if.dram_req_data), - .dram_req_tag (icache_dram_req_if.dram_req_tag), - .dram_req_ready (icache_dram_req_if.dram_req_ready), + .dram_req_valid (icache_dram_req_if.valid), + .dram_req_rw (icache_dram_req_if.rw), + .dram_req_byteen (icache_dram_req_if.byteen), + .dram_req_addr (icache_dram_req_if.addr), + .dram_req_data (icache_dram_req_if.data), + .dram_req_tag (icache_dram_req_if.tag), + .dram_req_ready (icache_dram_req_if.ready), // DRAM response - .dram_rsp_valid (icache_dram_rsp_if.dram_rsp_valid), - .dram_rsp_data (icache_dram_rsp_if.dram_rsp_data), - .dram_rsp_tag (icache_dram_rsp_if.dram_rsp_tag), - .dram_rsp_ready (icache_dram_rsp_if.dram_rsp_ready), + .dram_rsp_valid (icache_dram_rsp_if.valid), + .dram_rsp_data (icache_dram_rsp_if.data), + .dram_rsp_tag (icache_dram_rsp_if.tag), + .dram_rsp_ready (icache_dram_rsp_if.ready), // Snoop request .snp_req_valid (0), diff --git a/hw/rtl/VX_pipeline.v b/hw/rtl/VX_pipeline.v index 83833f3d..72c6ee2d 100644 --- a/hw/rtl/VX_pipeline.v +++ b/hw/rtl/VX_pipeline.v @@ -176,31 +176,31 @@ module VX_pipeline #( .ebreak (ebreak) ); - assign dcache_req_valid = core_dcache_req_if.core_req_valid; - assign dcache_req_rw = core_dcache_req_if.core_req_rw; - assign dcache_req_byteen = core_dcache_req_if.core_req_byteen; - assign dcache_req_addr = core_dcache_req_if.core_req_addr; - assign dcache_req_data = core_dcache_req_if.core_req_data; - assign dcache_req_tag = core_dcache_req_if.core_req_tag; - assign core_dcache_req_if.core_req_ready = dcache_req_ready; + assign dcache_req_valid = core_dcache_req_if.valid; + assign dcache_req_rw = core_dcache_req_if.rw; + assign dcache_req_byteen = core_dcache_req_if.byteen; + assign dcache_req_addr = core_dcache_req_if.addr; + assign dcache_req_data = core_dcache_req_if.data; + assign dcache_req_tag = core_dcache_req_if.tag; + assign core_dcache_req_if.ready = dcache_req_ready; - assign core_dcache_rsp_if.core_rsp_valid = dcache_rsp_valid; - assign core_dcache_rsp_if.core_rsp_data = dcache_rsp_data; - assign core_dcache_rsp_if.core_rsp_tag = dcache_rsp_tag; - assign dcache_rsp_ready = core_dcache_rsp_if.core_rsp_ready; + assign core_dcache_rsp_if.valid = dcache_rsp_valid; + assign core_dcache_rsp_if.data = dcache_rsp_data; + assign core_dcache_rsp_if.tag = dcache_rsp_tag; + assign dcache_rsp_ready = core_dcache_rsp_if.ready; - assign icache_req_valid = core_icache_req_if.core_req_valid; - assign icache_req_rw = core_icache_req_if.core_req_rw; - assign icache_req_byteen = core_icache_req_if.core_req_byteen; - assign icache_req_addr = core_icache_req_if.core_req_addr; - assign icache_req_data = core_icache_req_if.core_req_data; - assign icache_req_tag = core_icache_req_if.core_req_tag; - assign core_icache_req_if.core_req_ready = icache_req_ready; + assign icache_req_valid = core_icache_req_if.valid; + assign icache_req_rw = core_icache_req_if.rw; + assign icache_req_byteen = core_icache_req_if.byteen; + assign icache_req_addr = core_icache_req_if.addr; + assign icache_req_data = core_icache_req_if.data; + assign icache_req_tag = core_icache_req_if.tag; + assign core_icache_req_if.ready = icache_req_ready; - assign core_icache_rsp_if.core_rsp_valid = icache_rsp_valid; - assign core_icache_rsp_if.core_rsp_data = icache_rsp_data; - assign core_icache_rsp_if.core_rsp_tag = icache_rsp_tag; - assign icache_rsp_ready = core_icache_rsp_if.core_rsp_ready; + assign core_icache_rsp_if.valid = icache_rsp_valid; + assign core_icache_rsp_if.data = icache_rsp_data; + assign core_icache_rsp_if.tag = icache_rsp_tag; + assign icache_rsp_ready = core_icache_rsp_if.ready; `SCOPE_ASSIGN(scope_busy, busy); `SCOPE_ASSIGN(scope_schedule_delay, schedule_delay); diff --git a/hw/rtl/VX_scheduler.v b/hw/rtl/VX_scheduler.v index fb31cbd9..52810bcc 100644 --- a/hw/rtl/VX_scheduler.v +++ b/hw/rtl/VX_scheduler.v @@ -51,6 +51,7 @@ module VX_scheduler ( integer i, w; wire acquire_rd = (| bckE_req_if.valid) && (bckE_req_if.wb != 0) && (bckE_req_if.rd != 0) && !schedule_delay; + wire release_rd = (| writeback_if.valid) && (writeback_if.wb != 0) && (writeback_if.rd != 0); wire [`NUM_THREADS-1:0] valid_wb_new_mask = rename_table[writeback_if.warp_num][writeback_if.rd] & ~writeback_if.valid; diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 6869f3b0..4e0b7aed 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -282,8 +282,6 @@ module VX_warp_sched ( end endgenerate - // wire should_stall = stall || (jal && (warp_to_schedule == jal_warp_num)) || (branch_dir && (warp_to_schedule == branch_warp_num)); - wire should_jal = (jal && (warp_to_schedule == jal_warp_num)); wire should_bra = (branch_valid && branch_dir && (warp_to_schedule == branch_warp_num)); @@ -308,7 +306,7 @@ module VX_warp_sched ( assign use_active = (count_visible_active != 0) ? visible_active : (warp_active & (~warp_stalled) & (~total_barrier_stall) & (~warp_lock)); // Choosing a warp to schedule - VX_rr_arbiter #( + VX_fixed_arbiter #( .N(`NUM_WARPS) ) choose_schedule ( .clk (clk), diff --git a/hw/rtl/interfaces/VX_backend_req_if.v b/hw/rtl/interfaces/VX_backend_req_if.v index 31ab83a8..df0ea5b3 100644 --- a/hw/rtl/interfaces/VX_backend_req_if.v +++ b/hw/rtl/interfaces/VX_backend_req_if.v @@ -5,6 +5,9 @@ interface VX_backend_req_if (); + wire [`NUM_THREADS-1:0] valid; + wire [`NW_BITS-1:0] warp_num; + wire [31:0] curr_PC; wire [11:0] csr_address; wire is_csr; wire csr_immed; @@ -20,14 +23,11 @@ interface VX_backend_req_if (); wire [`BYTE_EN_BITS-1:0] mem_write; wire [2:0] branch_type; wire [19:0] upper_immed; - wire [31:0] curr_PC; wire is_etype; wire is_jal; wire jal; wire [31:0] jal_offset; - wire [31:0] next_PC; - wire [`NUM_THREADS-1:0] valid; - wire [`NW_BITS-1:0] warp_num; + wire [31:0] next_PC; // GPGPU stuff wire is_wspawn; diff --git a/hw/rtl/interfaces/VX_branch_rsp_if.v b/hw/rtl/interfaces/VX_branch_rsp_if.v index 45370ca1..00ac18f1 100644 --- a/hw/rtl/interfaces/VX_branch_rsp_if.v +++ b/hw/rtl/interfaces/VX_branch_rsp_if.v @@ -8,7 +8,7 @@ interface VX_branch_rsp_if (); wire valid_branch; wire branch_dir; wire [31:0] branch_dest; - wire [`NW_BITS-1:0] branch_warp_num; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_cache_core_req_if.v b/hw/rtl/interfaces/VX_cache_core_req_if.v index 451418d3..57de39f4 100644 --- a/hw/rtl/interfaces/VX_cache_core_req_if.v +++ b/hw/rtl/interfaces/VX_cache_core_req_if.v @@ -10,13 +10,13 @@ interface VX_cache_core_req_if #( parameter CORE_TAG_ID_BITS = 0 ) (); - wire [NUM_REQUESTS-1:0] core_req_valid; - wire [NUM_REQUESTS-1:0] core_req_rw; - wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] core_req_byteen; - wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] core_req_addr; - wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_req_data; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_req_tag; - wire core_req_ready; + wire [NUM_REQUESTS-1:0] valid; + wire [NUM_REQUESTS-1:0] rw; + wire [NUM_REQUESTS-1:0][WORD_SIZE-1:0] byteen; + wire [NUM_REQUESTS-1:0][`WORD_ADDR_WIDTH-1:0] addr; + wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data; + wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_core_rsp_if.v b/hw/rtl/interfaces/VX_cache_core_rsp_if.v index 7de31217..5b70f5ee 100644 --- a/hw/rtl/interfaces/VX_cache_core_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_core_rsp_if.v @@ -10,10 +10,10 @@ interface VX_cache_core_rsp_if #( parameter CORE_TAG_ID_BITS = 0 ) (); - wire [NUM_REQUESTS-1:0] core_rsp_valid; - wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] core_rsp_data; - wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] core_rsp_tag; - wire core_rsp_ready; + wire [NUM_REQUESTS-1:0] valid; + wire [NUM_REQUESTS-1:0][`WORD_WIDTH-1:0] data; + wire [`CORE_REQ_TAG_COUNT-1:0][CORE_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_dram_req_if.v b/hw/rtl/interfaces/VX_cache_dram_req_if.v index 5de4fefc..d92b9912 100644 --- a/hw/rtl/interfaces/VX_cache_dram_req_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_req_if.v @@ -9,13 +9,13 @@ interface VX_cache_dram_req_if #( parameter DRAM_TAG_WIDTH = 1 ) (); - wire dram_req_valid; - wire dram_req_rw; - wire [(DRAM_LINE_WIDTH/8)-1:0] dram_req_byteen; - wire [DRAM_ADDR_WIDTH-1:0] dram_req_addr; - wire [DRAM_LINE_WIDTH-1:0] dram_req_data; - wire [DRAM_TAG_WIDTH-1:0] dram_req_tag; - wire dram_req_ready; + wire valid; + wire rw; + wire [(DRAM_LINE_WIDTH/8)-1:0] byteen; + wire [DRAM_ADDR_WIDTH-1:0] addr; + wire [DRAM_LINE_WIDTH-1:0] data; + wire [DRAM_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v index ac299c27..9e994d3a 100644 --- a/hw/rtl/interfaces/VX_cache_dram_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_dram_rsp_if.v @@ -8,10 +8,10 @@ interface VX_cache_dram_rsp_if #( parameter DRAM_TAG_WIDTH = 1 ) (); - wire dram_rsp_valid; - wire [DRAM_LINE_WIDTH-1:0] dram_rsp_data; - wire [DRAM_TAG_WIDTH-1:0] dram_rsp_tag; - wire dram_rsp_ready; + wire valid; + wire [DRAM_LINE_WIDTH-1:0] data; + wire [DRAM_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_snp_req_if.v b/hw/rtl/interfaces/VX_cache_snp_req_if.v index fce768b8..6134b02d 100644 --- a/hw/rtl/interfaces/VX_cache_snp_req_if.v +++ b/hw/rtl/interfaces/VX_cache_snp_req_if.v @@ -8,11 +8,11 @@ interface VX_cache_snp_req_if #( parameter SNP_TAG_WIDTH = 0 ) (); - wire snp_req_valid; - wire [DRAM_ADDR_WIDTH-1:0] snp_req_addr; - wire snp_req_invalidate; - wire [SNP_TAG_WIDTH-1:0] snp_req_tag; - wire snp_req_ready; + wire valid; + wire [DRAM_ADDR_WIDTH-1:0] addr; + wire invalidate; + wire [SNP_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_cache_snp_rsp_if.v b/hw/rtl/interfaces/VX_cache_snp_rsp_if.v index 12f6f733..a553c48d 100644 --- a/hw/rtl/interfaces/VX_cache_snp_rsp_if.v +++ b/hw/rtl/interfaces/VX_cache_snp_rsp_if.v @@ -7,9 +7,9 @@ interface VX_cache_snp_rsp_if #( parameter SNP_TAG_WIDTH = 0 ) (); - wire snp_rsp_valid; - wire [SNP_TAG_WIDTH-1:0] snp_rsp_tag; - wire snp_rsp_ready; + wire valid; + wire [SNP_TAG_WIDTH-1:0] tag; + wire ready; endinterface diff --git a/hw/rtl/interfaces/VX_inst_meta_if.v b/hw/rtl/interfaces/VX_inst_meta_if.v index 9cab988f..8ebfa87f 100644 --- a/hw/rtl/interfaces/VX_inst_meta_if.v +++ b/hw/rtl/interfaces/VX_inst_meta_if.v @@ -5,10 +5,10 @@ interface VX_inst_meta_if (); - wire [31:0] instruction; - wire [31:0] inst_pc; - wire [`NW_BITS-1:0] warp_num; wire [`NUM_THREADS-1:0] valid; + wire [31:0] curr_PC; + wire [`NW_BITS-1:0] warp_num; + wire [31:0] instruction; endinterface diff --git a/hw/rtl/interfaces/VX_jal_rsp_if.v b/hw/rtl/interfaces/VX_jal_rsp_if.v index 61e0d73b..c4e2d230 100644 --- a/hw/rtl/interfaces/VX_jal_rsp_if.v +++ b/hw/rtl/interfaces/VX_jal_rsp_if.v @@ -8,7 +8,7 @@ interface VX_jal_rsp_if (); wire jal; wire [31:0] jal_dest; - wire [`NW_BITS-1:0] jal_warp_num; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_join_if.v b/hw/rtl/interfaces/VX_join_if.v index 337fc0c0..bc48bfee 100644 --- a/hw/rtl/interfaces/VX_join_if.v +++ b/hw/rtl/interfaces/VX_join_if.v @@ -7,7 +7,7 @@ interface VX_join_if (); wire is_join; - wire [`NW_BITS-1:0] join_warp_num; + wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/pipe_regs/VX_f_d_reg.v index a2dfba0c..59cf4506 100644 --- a/hw/rtl/pipe_regs/VX_f_d_reg.v +++ b/hw/rtl/pipe_regs/VX_f_d_reg.v @@ -20,8 +20,8 @@ module VX_f_d_reg ( .reset (reset), .stall (stall), .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) + .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), + .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); endmodule \ No newline at end of file diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/pipe_regs/VX_i_d_reg.v index 9963883f..2df17107 100644 --- a/hw/rtl/pipe_regs/VX_i_d_reg.v +++ b/hw/rtl/pipe_regs/VX_i_d_reg.v @@ -20,8 +20,8 @@ module VX_i_d_reg ( .reset (reset), .stall (stall), .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.inst_pc, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.inst_pc, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) + .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), + .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); endmodule \ No newline at end of file From a5f4eb3d133ee25708462a07e267abfa32d91228 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 2 Jul 2020 19:44:32 -0700 Subject: [PATCH 15/22] interfaces refactoring --- driver/rtlsim/Makefile | 2 +- driver/tests/basic/Makefile | 2 +- driver/tests/demo/Makefile | 2 +- hw/rtl/VX_exec_unit.v | 20 ++++++++++---------- hw/rtl/VX_fetch.v | 10 +++++----- hw/rtl/VX_warp.v | 4 ++-- hw/rtl/VX_warp_sched.v | 4 ++-- hw/rtl/interfaces/VX_branch_rsp_if.v | 6 +++--- hw/rtl/interfaces/VX_jal_rsp_if.v | 4 ++-- 9 files changed, 27 insertions(+), 27 deletions(-) diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 19b39484..82ab979b 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -21,7 +21,7 @@ DBG_FLAGS += -DDBG_CORE_REQ_INFO #CONFIGS += -DNUM_CLUSTERS=1 -DNUM_CORES=2 #DEBUG=1 -AFU=1 +#AFU=1 CFLAGS += -fPIC diff --git a/driver/tests/basic/Makefile b/driver/tests/basic/Makefile index 71e38862..a3792edc 100644 --- a/driver/tests/basic/Makefile +++ b/driver/tests/basic/Makefile @@ -38,7 +38,7 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 4096 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 run-ase: $(PROJECT) ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 256 diff --git a/driver/tests/demo/Makefile b/driver/tests/demo/Makefile index bfd6bec0..0368e5b3 100644 --- a/driver/tests/demo/Makefile +++ b/driver/tests/demo/Makefile @@ -36,7 +36,7 @@ $(PROJECT): $(SRCS) $(CXX) $(CXXFLAGS) $^ $(LDFLAGS) -L../../stub -lvortex -o $@ run-fpga: $(PROJECT) - LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 128 + LD_LIBRARY_PATH=../../opae:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 run-ase: $(PROJECT) ASE_LOG=0 LD_LIBRARY_PATH=../../opae/ase:$(LD_LIBRARY_PATH) ./$(PROJECT) -n 16 diff --git a/hw/rtl/VX_exec_unit.v b/hw/rtl/VX_exec_unit.v index d89b4e48..133b0869 100644 --- a/hw/rtl/VX_exec_unit.v +++ b/hw/rtl/VX_exec_unit.v @@ -115,15 +115,15 @@ module VX_exec_unit ( assign inst_exec_wb_if.curr_PC = in_curr_PC; // Jal rsp - assign jal_rsp_temp_if.jal = in_jal; - assign jal_rsp_temp_if.jal_dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); + assign jal_rsp_temp_if.valid = in_jal; + assign jal_rsp_temp_if.dest = $signed(in_a_reg_data[jal_branch_use_index]) + $signed(in_jal_offset); assign jal_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; // Branch rsp - assign branch_rsp_temp_if.valid_branch = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); - assign branch_rsp_temp_if.branch_dir = temp_branch_dir; - assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; - assign branch_rsp_temp_if.branch_dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset + assign branch_rsp_temp_if.valid = (exec_unit_req_if.branch_type != `BR_NO) && (| exec_unit_req_if.valid); + assign branch_rsp_temp_if.dir = temp_branch_dir; + assign branch_rsp_temp_if.warp_num = exec_unit_req_if.warp_num; + assign branch_rsp_temp_if.dest = $signed(exec_unit_req_if.curr_PC) + ($signed(exec_unit_req_if.itype_immed) << 1); // itype_immed = branch_offset VX_generic_register #( .N(33 + `NW_BITS-1 + 1) @@ -132,8 +132,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({jal_rsp_temp_if.jal, jal_rsp_temp_if.jal_dest, jal_rsp_temp_if.warp_num}), - .out ({jal_rsp_if.jal , jal_rsp_if.jal_dest , jal_rsp_if.warp_num}) + .in ({jal_rsp_temp_if.valid, jal_rsp_temp_if.dest, jal_rsp_temp_if.warp_num}), + .out ({jal_rsp_if.valid , jal_rsp_if.dest , jal_rsp_if.warp_num}) ); VX_generic_register #( @@ -143,8 +143,8 @@ module VX_exec_unit ( .reset (reset), .stall (1'b0), .flush (1'b0), - .in ({branch_rsp_temp_if.valid_branch, branch_rsp_temp_if.branch_dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.branch_dest}), - .out ({branch_rsp_if.valid_branch , branch_rsp_if.branch_dir , branch_rsp_if.warp_num , branch_rsp_if.branch_dest }) + .in ({branch_rsp_temp_if.valid, branch_rsp_temp_if.dir, branch_rsp_temp_if.warp_num, branch_rsp_temp_if.dest}), + .out ({branch_rsp_if.valid , branch_rsp_if.dir , branch_rsp_if.warp_num , branch_rsp_if.dest }) ); endmodule : VX_exec_unit \ No newline at end of file diff --git a/hw/rtl/VX_fetch.v b/hw/rtl/VX_fetch.v index e17443f4..810f0317 100644 --- a/hw/rtl/VX_fetch.v +++ b/hw/rtl/VX_fetch.v @@ -68,14 +68,14 @@ module VX_fetch ( .split_warp_num (warp_ctl_if.warp_num), // JAL - .jal (jal_rsp_if.jal), - .jal_dest (jal_rsp_if.jal_dest), + .jal (jal_rsp_if.valid), + .dest (jal_rsp_if.dest), .jal_warp_num (jal_rsp_if.warp_num), // Branch - .branch_valid (branch_rsp_if.valid_branch), - .branch_dir (branch_rsp_if.branch_dir), - .branch_dest (branch_rsp_if.branch_dest), + .branch_valid (branch_rsp_if.valid), + .branch_dir (branch_rsp_if.dir), + .branch_dest (branch_rsp_if.dest), .branch_warp_num (branch_rsp_if.warp_num), // Outputs diff --git a/hw/rtl/VX_warp.v b/hw/rtl/VX_warp.v index 53e4e549..b780d760 100644 --- a/hw/rtl/VX_warp.v +++ b/hw/rtl/VX_warp.v @@ -9,7 +9,7 @@ module VX_warp ( input wire[`NUM_THREADS-1:0] thread_mask, input wire change_mask, input wire jal, - input wire[31:0] jal_dest, + input wire[31:0] dest, input wire branch_dir, input wire[31:0] branch_dest, input wire wspawn, @@ -43,7 +43,7 @@ module VX_warp ( always @(*) begin if (jal == 1'b1) begin - temp_PC = jal_dest; + temp_PC = dest; end else if (branch_dir) begin temp_PC = branch_dest; end else begin diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 4e0b7aed..81825e54 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -44,7 +44,7 @@ module VX_warp_sched ( // JAL input wire jal, - input wire[31:0] jal_dest, + input wire[31:0] dest, input wire[`NW_BITS-1:0] jal_warp_num, // Branch @@ -203,7 +203,7 @@ module VX_warp_sched ( // Jal if (jal) begin - warp_pcs[jal_warp_num] <= jal_dest; + warp_pcs[jal_warp_num] <= dest; warp_stalled[jal_warp_num] <= 0; end diff --git a/hw/rtl/interfaces/VX_branch_rsp_if.v b/hw/rtl/interfaces/VX_branch_rsp_if.v index 00ac18f1..a8f01d44 100644 --- a/hw/rtl/interfaces/VX_branch_rsp_if.v +++ b/hw/rtl/interfaces/VX_branch_rsp_if.v @@ -5,9 +5,9 @@ interface VX_branch_rsp_if (); - wire valid_branch; - wire branch_dir; - wire [31:0] branch_dest; + wire valid; + wire dir; + wire [31:0] dest; wire [`NW_BITS-1:0] warp_num; endinterface diff --git a/hw/rtl/interfaces/VX_jal_rsp_if.v b/hw/rtl/interfaces/VX_jal_rsp_if.v index c4e2d230..3f6796a0 100644 --- a/hw/rtl/interfaces/VX_jal_rsp_if.v +++ b/hw/rtl/interfaces/VX_jal_rsp_if.v @@ -6,8 +6,8 @@ interface VX_jal_rsp_if (); - wire jal; - wire [31:0] jal_dest; + wire valid; + wire [31:0] dest; wire [`NW_BITS-1:0] warp_num; endinterface From bca36e213e6f3fdf00736020230468c8e74bf6c7 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Thu, 2 Jul 2020 20:43:52 -0700 Subject: [PATCH 16/22] interfaces refactoring --- hw/rtl/VX_back_end.v | 2 +- hw/rtl/VX_csr_arb.v | 2 +- hw/rtl/VX_csr_pipe.v | 16 ++++----- hw/rtl/VX_decode.v | 2 +- hw/rtl/VX_gpr_stage.v | 44 ++++++++++++------------- hw/rtl/VX_inst_multiplex.v | 4 +-- hw/rtl/VX_lsu_unit.v | 2 +- hw/rtl/interfaces/VX_backend_req_if.v | 2 +- hw/rtl/interfaces/VX_csr_req_if.v | 2 +- hw/rtl/interfaces/VX_exec_unit_req_if.v | 2 +- hw/rtl/interfaces/VX_lsu_req_if.v | 4 +-- hw/rtl/pipe_regs/VX_d_e_reg.v | 4 +-- 12 files changed, 43 insertions(+), 43 deletions(-) diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index 8b284672..82c42d83 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -67,7 +67,7 @@ module VX_back_end #( // End new .memory_delay (mem_delay), .exec_delay (exec_delay), - .gpr_stage_delay (gpr_stage_delay) + .delay (gpr_stage_delay) ); assign ebreak = exec_unit_req_if.is_etype && (| exec_unit_req_if.valid); diff --git a/hw/rtl/VX_csr_arb.v b/hw/rtl/VX_csr_arb.v index 84dafa8c..58327ee3 100644 --- a/hw/rtl/VX_csr_arb.v +++ b/hw/rtl/VX_csr_arb.v @@ -24,7 +24,7 @@ module VX_csr_arb ( assign issued_csr_req_if.valid = pick_core ? csr_core_req_if.valid : {`NUM_THREADS{csr_io_req_if.valid}}; assign issued_csr_req_if.is_csr = pick_core ? csr_core_req_if.is_csr : 1'b1; assign issued_csr_req_if.alu_op = pick_core ? csr_core_req_if.alu_op : (csr_io_req_if.rw ? `ALU_CSR_RW : `ALU_CSR_RS); - assign issued_csr_req_if.csr_address = pick_core ? csr_core_req_if.csr_address : csr_io_req_if.addr; + assign issued_csr_req_if.csr_addr = pick_core ? csr_core_req_if.csr_addr : csr_io_req_if.addr; assign issued_csr_req_if.csr_immed = pick_core ? csr_core_req_if.csr_immed : 0; assign issued_csr_req_if.csr_mask = pick_core ? csr_core_req_if.csr_mask : (csr_io_req_if.rw ? csr_io_req_if.data : 32'b0); assign issued_csr_req_if.is_io = !pick_core; diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index 04185d40..beb8638f 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -17,7 +17,7 @@ module VX_csr_pipe #( wire[4:0] rd_s2; wire[1:0] wb_s2; wire is_csr_s2; - wire[`CSR_ADDR_SIZE-1:0] csr_address_s2; + wire[`CSR_ADDR_SIZE-1:0] csr_addr_s2; wire[31:0] csr_read_data_s2; wire[31:0] csr_updated_data_s2; @@ -29,16 +29,16 @@ module VX_csr_pipe #( ) csr_data ( .clk (clk), .reset (reset), - .read_addr (csr_req_if.csr_address), + .read_addr (csr_req_if.csr_addr), .read_data (csr_read_data_unqual), .write_enable (is_csr_s2), .write_data (csr_updated_data_s2[`CSR_WIDTH-1:0]), - .write_addr (csr_address_s2), + .write_addr (csr_addr_s2), .warp_num (csr_req_if.warp_num), .wb_valid (| writeback_if.valid) ); - wire car_hazard = (csr_address_s2 == csr_req_if.csr_address) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; + wire car_hazard = (csr_addr_s2 == csr_req_if.csr_addr) & (warp_num_s2 == csr_req_if.warp_num) & |(valid_s2) & is_csr_s2; assign csr_read_data = car_hazard ? csr_updated_data_s2 : csr_read_data_unqual; @@ -60,8 +60,8 @@ module VX_csr_pipe #( .reset(reset), .stall(no_slot_csr), .flush(1'b0), - .in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_address, csr_req_if.is_io, csr_read_data , csr_updated_data }), - .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_address_s2 , csr_wb_if.is_io , csr_read_data_s2, csr_updated_data_s2}) + .in ({csr_req_if.valid, csr_req_if.warp_num, csr_req_if.rd, csr_req_if.wb, csr_req_if.is_csr, csr_req_if.csr_addr, csr_req_if.is_io, csr_read_data , csr_updated_data }), + .out ({valid_s2 , warp_num_s2 , rd_s2 , wb_s2 , is_csr_s2 , csr_addr_s2 , csr_wb_if.is_io , csr_read_data_s2, csr_updated_data_s2}) ); assign csr_wb_if.valid = valid_s2; @@ -71,8 +71,8 @@ module VX_csr_pipe #( genvar i; for (i = 0; i < `NUM_THREADS; i++) begin - assign csr_wb_if.data[i] = (csr_address_s2 == `CSR_LTID) ? i : - (csr_address_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) : + assign csr_wb_if.data[i] = (csr_addr_s2 == `CSR_LTID) ? i : + (csr_addr_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) : csr_read_data_s2; end diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index dd7e1d1c..af7afed5 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -204,7 +204,7 @@ module VX_decode( assign csr_cond1 = func3 != 3'h0; assign csr_cond2 = u_12 >= 12'h2; - assign frE_to_bckE_req_if.csr_address = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; + assign frE_to_bckE_req_if.csr_addr = (csr_cond1 && csr_cond2) ? u_12 : 12'h55; // ITYPE IMEED assign alu_shift_i = (func3 == 3'h1) || (func3 == 3'h5); diff --git a/hw/rtl/VX_gpr_stage.v b/hw/rtl/VX_gpr_stage.v index aed5b7e5..e0f5f865 100644 --- a/hw/rtl/VX_gpr_stage.v +++ b/hw/rtl/VX_gpr_stage.v @@ -8,7 +8,7 @@ module VX_gpr_stage ( input wire memory_delay, input wire exec_delay, input wire stall_gpr_csr, - output wire gpr_stage_delay, + output wire delay, // decodee inputs VX_backend_req_if bckE_req_if, @@ -81,7 +81,7 @@ module VX_gpr_stage ( wire stall_csr = stall_gpr_csr && bckE_req_if.is_csr && (| bckE_req_if.valid); - assign gpr_stage_delay = stall_lsu || stall_exec || stall_csr; + assign delay = stall_lsu || stall_exec || stall_csr; `ifdef ASIC wire delayed_lsu_last_cycle; @@ -99,10 +99,10 @@ module VX_gpr_stage ( ); wire [`NUM_THREADS-1:0][31:0] temp_store_data; - wire [`NUM_THREADS-1:0][31:0] temp_base_address; // A reg data + wire [`NUM_THREADS-1:0][31:0] temp_base_addr; // A reg data wire [`NUM_THREADS-1:0][31:0] real_store_data; - wire [`NUM_THREADS-1:0][31:0] real_base_address; // A reg data + wire [`NUM_THREADS-1:0][31:0] real_base_addr; // A reg data wire store_curr_real = !delayed_lsu_last_cycle && stall_lsu; @@ -113,15 +113,15 @@ module VX_gpr_stage ( .reset (reset), .stall (!store_curr_real), .flush (stall_rest), - .in ({real_store_data, real_base_address}), - .out ({temp_store_data, temp_base_address}) + .in ({real_store_data, real_base_addr}), + .out ({temp_store_data, temp_base_addr}) ); - assign real_store_data = lsu_req_temp_if.store_data; - assign real_base_address = lsu_req_temp_if.base_address; + assign real_store_data = lsu_req_temp_if.store_data; + assign real_base_addr = lsu_req_temp_if.base_addr; - assign lsu_req_if.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; - assign lsu_req_if.base_address = (delayed_lsu_last_cycle) ? temp_base_address : real_base_address; + assign lsu_req_if.store_data = (delayed_lsu_last_cycle) ? temp_store_data : real_store_data; + assign lsu_req_if.base_addr = (delayed_lsu_last_cycle) ? temp_base_addr : real_base_addr; VX_generic_register #( .N(77 + `NW_BITS-1 + 1 + (`NUM_THREADS)) @@ -141,11 +141,11 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_exec), .flush (flush_exec), - .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), - .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) + .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_addr, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), + .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_addr , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) ); - assign exec_unit_req_if.a_reg_data = real_base_address; + assign exec_unit_req_if.a_reg_data = real_base_addr; assign exec_unit_req_if.b_reg_data = real_store_data; VX_generic_register #( @@ -159,7 +159,7 @@ module VX_gpr_stage ( .out ({gpu_inst_req_if.valid , gpu_inst_req_if.warp_num , gpu_inst_req_if.is_wspawn , gpu_inst_req_if.is_tmc , gpu_inst_req_if.is_split , gpu_inst_req_if.is_barrier , gpu_inst_req_if.next_PC }) ); - assign gpu_inst_req_if.a_reg_data = real_base_address; + assign gpu_inst_req_if.a_reg_data = real_base_addr; assign gpu_inst_req_if.rd2 = real_store_data; VX_generic_register #( @@ -169,8 +169,8 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_gpr_csr), .flush (flush_rest), - .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), - .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask }) + .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_addr, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), + .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_addr , csr_req_if.csr_immed , csr_req_if.csr_mask }) ); @@ -184,8 +184,8 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_lsu), .flush (flush_lsu), - .in ({lsu_req_temp_if.valid, lsu_req_temp_if.curr_PC, lsu_req_temp_if.warp_num, lsu_req_temp_if.store_data, lsu_req_temp_if.base_address, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}), - .out ({lsu_req_if.valid , lsu_req_if.curr_PC , lsu_req_if.warp_num , lsu_req_if.store_data , lsu_req_if.base_address , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb }) + .in ({lsu_req_temp_if.valid, lsu_req_temp_if.curr_PC, lsu_req_temp_if.warp_num, lsu_req_temp_if.store_data, lsu_req_temp_if.base_addr, lsu_req_temp_if.offset, lsu_req_temp_if.mem_read, lsu_req_temp_if.mem_write, lsu_req_temp_if.rd, lsu_req_temp_if.wb}), + .out ({lsu_req_if.valid , lsu_req_if.curr_PC , lsu_req_if.warp_num , lsu_req_if.store_data , lsu_req_if.base_addr , lsu_req_if.offset , lsu_req_if.mem_read , lsu_req_if.mem_write , lsu_req_if.rd , lsu_req_if.wb }) ); VX_generic_register #( @@ -195,8 +195,8 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_exec), .flush (flush_exec), - .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.a_reg_data, exec_unit_req_temp_if.b_reg_data, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_address, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), - .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.a_reg_data , exec_unit_req_if.b_reg_data , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_address , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) + .in ({exec_unit_req_temp_if.valid, exec_unit_req_temp_if.warp_num, exec_unit_req_temp_if.curr_PC, exec_unit_req_temp_if.next_PC, exec_unit_req_temp_if.rd, exec_unit_req_temp_if.wb, exec_unit_req_temp_if.a_reg_data, exec_unit_req_temp_if.b_reg_data, exec_unit_req_temp_if.alu_op, exec_unit_req_temp_if.rs1, exec_unit_req_temp_if.rs2, exec_unit_req_temp_if.rs2_src, exec_unit_req_temp_if.itype_immed, exec_unit_req_temp_if.upper_immed, exec_unit_req_temp_if.branch_type, exec_unit_req_temp_if.is_jal, exec_unit_req_temp_if.jal, exec_unit_req_temp_if.jal_offset, exec_unit_req_temp_if.is_etype, exec_unit_req_temp_if.wspawn, exec_unit_req_temp_if.is_csr, exec_unit_req_temp_if.csr_addr, exec_unit_req_temp_if.csr_immed, exec_unit_req_temp_if.csr_mask}), + .out ({exec_unit_req_if.valid , exec_unit_req_if.warp_num , exec_unit_req_if.curr_PC , exec_unit_req_if.next_PC , exec_unit_req_if.rd , exec_unit_req_if.wb , exec_unit_req_if.a_reg_data , exec_unit_req_if.b_reg_data , exec_unit_req_if.alu_op , exec_unit_req_if.rs1 , exec_unit_req_if.rs2 , exec_unit_req_if.rs2_src , exec_unit_req_if.itype_immed , exec_unit_req_if.upper_immed , exec_unit_req_if.branch_type , exec_unit_req_if.is_jal , exec_unit_req_if.jal , exec_unit_req_if.jal_offset , exec_unit_req_if.is_etype , exec_unit_req_if.wspawn , exec_unit_req_if.is_csr , exec_unit_req_if.csr_addr , exec_unit_req_if.csr_immed , exec_unit_req_if.csr_mask }) ); VX_generic_register #( @@ -217,8 +217,8 @@ module VX_gpr_stage ( .reset (reset), .stall (stall_gpr_csr), .flush (flush_rest), - .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_address, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), - .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_address , csr_req_if.csr_immed , csr_req_if.csr_mask }) + .in ({csr_req_temp_if.valid, csr_req_temp_if.warp_num, csr_req_temp_if.rd, csr_req_temp_if.wb, csr_req_temp_if.alu_op, csr_req_temp_if.is_csr, csr_req_temp_if.csr_addr, csr_req_temp_if.csr_immed, csr_req_temp_if.csr_mask}), + .out ({csr_req_if.valid , csr_req_if.warp_num , csr_req_if.rd , csr_req_if.wb , csr_req_if.alu_op , csr_req_if.is_csr , csr_req_if.csr_addr , csr_req_if.csr_immed , csr_req_if.csr_mask }) ); `endif diff --git a/hw/rtl/VX_inst_multiplex.v b/hw/rtl/VX_inst_multiplex.v index 57cf3387..73225085 100644 --- a/hw/rtl/VX_inst_multiplex.v +++ b/hw/rtl/VX_inst_multiplex.v @@ -33,7 +33,7 @@ module VX_inst_multiplex ( // LSU Unit assign lsu_req_if.valid = bckE_req_if.valid & is_mem_mask; assign lsu_req_if.warp_num = bckE_req_if.warp_num; - assign lsu_req_if.base_address = gpr_read_if.a_reg_data; + assign lsu_req_if.base_addr = gpr_read_if.a_reg_data; assign lsu_req_if.store_data = gpr_read_if.b_reg_data; assign lsu_req_if.offset = bckE_req_if.itype_immed; @@ -83,7 +83,7 @@ module VX_inst_multiplex ( assign csr_req_if.wb = bckE_req_if.wb; assign csr_req_if.alu_op = bckE_req_if.alu_op; assign csr_req_if.is_csr = bckE_req_if.is_csr; - assign csr_req_if.csr_address = bckE_req_if.csr_address; + assign csr_req_if.csr_addr = bckE_req_if.csr_addr; assign csr_req_if.csr_immed = bckE_req_if.csr_immed; assign csr_req_if.csr_mask = bckE_req_if.csr_mask; diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index 4482ab75..cb773cde 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -38,7 +38,7 @@ module VX_lsu_unit #( // Generate Full Addresses wire[`NUM_THREADS-1:0][31:0] full_address; for (i = 0; i < `NUM_THREADS; i++) begin - assign full_address[i] = lsu_req_if.base_address[i] + lsu_req_if.offset; + assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset; end VX_generic_register #( diff --git a/hw/rtl/interfaces/VX_backend_req_if.v b/hw/rtl/interfaces/VX_backend_req_if.v index df0ea5b3..f153f1b6 100644 --- a/hw/rtl/interfaces/VX_backend_req_if.v +++ b/hw/rtl/interfaces/VX_backend_req_if.v @@ -8,7 +8,7 @@ interface VX_backend_req_if (); wire [`NUM_THREADS-1:0] valid; wire [`NW_BITS-1:0] warp_num; wire [31:0] curr_PC; - wire [11:0] csr_address; + wire [11:0] csr_addr; wire is_csr; wire csr_immed; wire [31:0] csr_mask; diff --git a/hw/rtl/interfaces/VX_csr_req_if.v b/hw/rtl/interfaces/VX_csr_req_if.v index a661e38f..6eeddf74 100644 --- a/hw/rtl/interfaces/VX_csr_req_if.v +++ b/hw/rtl/interfaces/VX_csr_req_if.v @@ -11,7 +11,7 @@ interface VX_csr_req_if (); wire [1:0] wb; wire [4:0] alu_op; wire is_csr; - wire [11:0] csr_address; + wire [11:0] csr_addr; wire csr_immed; wire [31:0] csr_mask; diff --git a/hw/rtl/interfaces/VX_exec_unit_req_if.v b/hw/rtl/interfaces/VX_exec_unit_req_if.v index b87fe1b0..918cb456 100644 --- a/hw/rtl/interfaces/VX_exec_unit_req_if.v +++ b/hw/rtl/interfaces/VX_exec_unit_req_if.v @@ -38,7 +38,7 @@ interface VX_exec_unit_req_if (); // CSR info wire is_csr; - wire [11:0] csr_address; + wire [11:0] csr_addr; wire csr_immed; wire [31:0] csr_mask; diff --git a/hw/rtl/interfaces/VX_lsu_req_if.v b/hw/rtl/interfaces/VX_lsu_req_if.v index 636b6afd..216853cf 100644 --- a/hw/rtl/interfaces/VX_lsu_req_if.v +++ b/hw/rtl/interfaces/VX_lsu_req_if.v @@ -10,8 +10,8 @@ interface VX_lsu_req_if (); wire [31:0] curr_PC; wire [`NW_BITS-1:0] warp_num; wire [`NUM_THREADS-1:0][31:0] store_data; - wire [`NUM_THREADS-1:0][31:0] base_address; // A reg data - wire [31:0] offset; // itype_immed + wire [`NUM_THREADS-1:0][31:0] base_addr; // A reg data + wire [31:0] offset; // itype_immed wire [`BYTE_EN_BITS-1:0] mem_read; wire [`BYTE_EN_BITS-1:0] mem_write; wire [4:0] rd; // dest register diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/pipe_regs/VX_d_e_reg.v index 35139f4d..93ae5ac0 100644 --- a/hw/rtl/pipe_regs/VX_d_e_reg.v +++ b/hw/rtl/pipe_regs/VX_d_e_reg.v @@ -19,8 +19,8 @@ module VX_d_e_reg ( .reset (reset), .stall (stall), .flush (flush), - .in ({frE_to_bckE_req_if.csr_address, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}), - .out ({bckE_req_if.csr_address , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier }) + .in ({frE_to_bckE_req_if.csr_addr, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}), + .out ({bckE_req_if.csr_addr , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier }) ); endmodule From 77c3b2d45f689639b7cd19f188c7b1e7096eb965 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 10 Jul 2020 11:23:34 -0700 Subject: [PATCH 17/22] lsu_unit refactoring to reduce critical path --- hw/rtl/VX_alu_unit.v | 5 +- hw/rtl/VX_back_end.v | 2 +- hw/rtl/VX_csr_pipe.v | 2 +- hw/rtl/VX_decode.v | 8 +- hw/rtl/VX_define.vh | 2 +- hw/rtl/VX_exec_unit.v | 39 ++++---- hw/rtl/VX_lsu_unit.v | 128 +++++++++++++------------ hw/rtl/VX_warp_sched.v | 46 ++++----- hw/rtl/cache/VX_cache_core_rsp_merge.v | 15 ++- 9 files changed, 124 insertions(+), 123 deletions(-) diff --git a/hw/rtl/VX_alu_unit.v b/hw/rtl/VX_alu_unit.v index b0d0c20f..d1b30016 100644 --- a/hw/rtl/VX_alu_unit.v +++ b/hw/rtl/VX_alu_unit.v @@ -25,7 +25,7 @@ module VX_alu_unit ( wire[31:0] alu_in2 = (src_rs2 == `RS2_IMMED) ? itype_immed : src_b; wire[31:0] upper_immed_s = {upper_immed, {12{1'b0}}}; - + reg [7:0] inst_delay; reg [7:0] curr_inst_delay; @@ -70,7 +70,6 @@ module VX_alu_unit ( `ALU_SUBU: alu_result = (alu_in1 >= alu_in2) ? 32'h0 : 32'hffffffff; `ALU_LUI: alu_result = upper_immed_s; `ALU_AUIPC: alu_result = $signed(curr_PC) + $signed(upper_immed_s); - // TODO: profitable to roll these exceptional cases into inst_delay_tmp to avoid pipeline when possible? `ALU_MUL: alu_result = mul_result[31:0]; `ALU_MULH: alu_result = mul_result[63:32]; `ALU_MULHSU: alu_result = mul_result[63:32]; @@ -80,7 +79,7 @@ module VX_alu_unit ( `ALU_REM: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_signed; `ALU_REMU: alu_result = (alu_in2 == 0) ? alu_in1 : rem_result_unsigned; default: alu_result = 32'h0; - endcase // alu_op + endcase end VX_divide #( diff --git a/hw/rtl/VX_back_end.v b/hw/rtl/VX_back_end.v index 82c42d83..3da014ce 100644 --- a/hw/rtl/VX_back_end.v +++ b/hw/rtl/VX_back_end.v @@ -80,7 +80,7 @@ module VX_back_end #( .clk (clk), .reset (reset), .lsu_req_if (lsu_req_if), - .mem_wb_if_p1 (mem_wb_if), + .mem_wb_if (mem_wb_if), .dcache_req_if (dcache_req_if), .dcache_rsp_if (dcache_rsp_if), .delay (mem_delay), diff --git a/hw/rtl/VX_csr_pipe.v b/hw/rtl/VX_csr_pipe.v index beb8638f..aa6980ab 100644 --- a/hw/rtl/VX_csr_pipe.v +++ b/hw/rtl/VX_csr_pipe.v @@ -73,7 +73,7 @@ module VX_csr_pipe #( for (i = 0; i < `NUM_THREADS; i++) begin assign csr_wb_if.data[i] = (csr_addr_s2 == `CSR_LTID) ? i : (csr_addr_s2 == `CSR_GTID) ? (csr_read_data_s2 * `NUM_THREADS + i) : - csr_read_data_s2; + csr_read_data_s2; end assign stall_gpr_csr = no_slot_csr && csr_req_if.is_csr && (| csr_req_if.valid); diff --git a/hw/rtl/VX_decode.v b/hw/rtl/VX_decode.v index af7afed5..deb3f44b 100644 --- a/hw/rtl/VX_decode.v +++ b/hw/rtl/VX_decode.v @@ -227,7 +227,7 @@ module VX_decode( case (curr_opcode) `INST_B: begin // $display("BRANCH IN DECODE"); - temp_branch_stall = 1'b1 && in_valid; + temp_branch_stall = in_valid; case (func3) 3'h0: temp_branch_type = `BR_EQ; 3'h1: temp_branch_type = `BR_NE; @@ -240,15 +240,15 @@ module VX_decode( end `INST_JAL: begin temp_branch_type = `BR_NO; - temp_branch_stall = 1'b1 && in_valid; + temp_branch_stall = in_valid; end `INST_JALR: begin temp_branch_type = `BR_NO; - temp_branch_stall = 1'b1 && in_valid; + temp_branch_stall = in_valid; end default: begin temp_branch_type = `BR_NO; - temp_branch_stall = 1'b0 && in_valid; + temp_branch_stall = 1'b0; end endcase end diff --git a/hw/rtl/VX_define.vh b/hw/rtl/VX_define.vh index 21118a76..21da158e 100644 --- a/hw/rtl/VX_define.vh +++ b/hw/rtl/VX_define.vh @@ -72,7 +72,7 @@ `define CSR_WIDTH 12 -`define DIV_LATENCY 18 +`define DIV_LATENCY 22 `define MUL_LATENCY 2 diff --git a/hw/rtl/VX_exec_unit.v b/hw/rtl/VX_exec_unit.v index 133b0869..0b4259b5 100644 --- a/hw/rtl/VX_exec_unit.v +++ b/hw/rtl/VX_exec_unit.v @@ -15,18 +15,18 @@ module VX_exec_unit ( output wire delay ); - wire[`NUM_THREADS-1:0][31:0] in_a_reg_data; - wire[`NUM_THREADS-1:0][31:0] in_b_reg_data; - wire[4:0] in_alu_op; - wire in_rs2_src; - wire[31:0] in_itype_immed; + wire [`NUM_THREADS-1:0][31:0] in_a_reg_data; + wire [`NUM_THREADS-1:0][31:0] in_b_reg_data; + wire [4:0] in_alu_op; + wire in_rs2_src; + wire [31:0] in_itype_immed; `DEBUG_BEGIN - wire[2:0] in_branch_type; + wire [2:0] in_branch_type; `DEBUG_END - wire[19:0] in_upper_immed; - wire in_jal; - wire[31:0] in_jal_offset; - wire[31:0] in_curr_PC; + wire [19:0] in_upper_immed; + wire in_jal; + wire [31:0] in_jal_offset; + wire [31:0] in_curr_PC; assign in_a_reg_data = exec_unit_req_if.a_reg_data; assign in_b_reg_data = exec_unit_req_if.b_reg_data; @@ -39,12 +39,12 @@ module VX_exec_unit ( assign in_jal_offset = exec_unit_req_if.jal_offset; assign in_curr_PC = exec_unit_req_if.curr_PC; - wire[`NUM_THREADS-1:0][31:0] alu_result; - wire[`NUM_THREADS-1:0] alu_stall; + wire [`NUM_THREADS-1:0][31:0] alu_result; + wire [`NUM_THREADS-1:0] alu_stall; genvar i; generate - for (i = 0; i < `NUM_THREADS; i++) begin : alu_defs + for (i = 0; i < `NUM_THREADS; i++) begin VX_alu_unit alu_unit ( .clk (clk), .reset (reset), @@ -65,20 +65,17 @@ module VX_exec_unit ( assign delay = no_slot_exec || internal_stall; -`DEBUG_BEGIN wire [$clog2(`NUM_THREADS)-1:0] jal_branch_use_index; - wire jal_branch_found_valid; -`DEBUG_END VX_priority_encoder #( .N(`NUM_THREADS) ) choose_alu_result ( - .data_in (exec_unit_req_if.valid), - .data_out (jal_branch_use_index), - .valid_out (jal_branch_found_valid) + .data_in (exec_unit_req_if.valid), + .data_out (jal_branch_use_index), + `UNUSED_PIN (valid_out) ); - wire[31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; + wire [31:0] branch_use_alu_result = alu_result[jal_branch_use_index]; reg temp_branch_dir; always @(*) @@ -95,7 +92,7 @@ module VX_exec_unit ( endcase // in_branch_type end - wire[`NUM_THREADS-1:0][31:0] duplicate_PC_data; + wire [`NUM_THREADS-1:0][31:0] duplicate_PC_data; generate for (i = 0; i < `NUM_THREADS; i++) begin diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index cb773cde..f2f8af73 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -12,7 +12,7 @@ module VX_lsu_unit #( VX_lsu_req_if lsu_req_if, // Write back to GPR - VX_wb_if mem_wb_if_p1, + VX_wb_if mem_wb_if, // Dcache interface VX_cache_core_req_if dcache_req_if, @@ -21,62 +21,68 @@ module VX_lsu_unit #( output wire delay ); - VX_wb_if mem_wb_if(); + VX_wb_if mem_wb_unqual_if(); - wire[`NUM_THREADS-1:0][31:0] use_address; - wire[`NUM_THREADS-1:0][31:0] use_store_data; - wire[`NUM_THREADS-1:0] use_valid; - wire[`BYTE_EN_BITS-1:0] use_mem_read; - wire[`BYTE_EN_BITS-1:0] use_mem_write; - wire[4:0] use_rd; - wire[`NW_BITS-1:0] use_warp_num; - wire[1:0] use_wb; - wire[31:0] use_pc; + wire [`NUM_THREADS-1:0] use_valid; + wire use_req_rw; + wire [`NUM_THREADS-1:0][29:0] use_req_addr; + wire [`NUM_THREADS-1:0][1:0] use_req_offset; + wire [`NUM_THREADS-1:0][3:0] use_req_byteen; + wire [`NUM_THREADS-1:0][31:0] use_req_data; + wire [`BYTE_EN_BITS-1:0] use_mem_read; + wire [4:0] use_rd; + wire [`NW_BITS-1:0] use_warp_num; + wire [1:0] use_wb; + wire [31:0] use_pc; genvar i; // Generate Full Addresses - wire[`NUM_THREADS-1:0][31:0] full_address; + wire[`NUM_THREADS-1:0][31:0] full_address; for (i = 0; i < `NUM_THREADS; i++) begin assign full_address[i] = lsu_req_if.base_addr[i] + lsu_req_if.offset; end - VX_generic_register #( - .N(45 + `NW_BITS-1 + 1 + `NUM_THREADS*65) - ) lsu_buffer ( - .clk (clk), - .reset (reset), - .stall (delay), - .flush (1'b0), - .in ({full_address,lsu_req_if.store_data, lsu_req_if.valid, lsu_req_if.mem_read, lsu_req_if.mem_write, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}), - .out ({use_address, use_store_data , use_valid , use_mem_read , use_mem_write , use_rd , use_warp_num , use_wb , use_pc }) - ); - - wire core_req_rw = (use_mem_write != `BYTE_EN_NO); - - wire [`NUM_THREADS-1:0][4:0] mem_req_offset; - wire [`NUM_THREADS-1:0][29:0] mem_req_addr; - wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; - wire [`NUM_THREADS-1:0][31:0] mem_req_data; - - wire [`NUM_THREADS-1:0][4:0] mem_rsp_offset; - wire[2:0] core_rsp_mem_read; + wire mem_req_rw = (lsu_req_if.mem_write != `BYTE_EN_NO); reg [3:0] wmask; always @(*) begin - case ((core_req_rw ? use_mem_write[1:0] : use_mem_read[1:0])) + case ((mem_req_rw ? lsu_req_if.mem_write[1:0] : lsu_req_if.mem_read[1:0])) 0: wmask = 4'b0001; 1: wmask = 4'b0011; default : wmask = 4'b1111; endcase end + wire [`NUM_THREADS-1:0][29:0] mem_req_addr; + wire [`NUM_THREADS-1:0][1:0] mem_req_offset; + wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; + wire [`NUM_THREADS-1:0][31:0] mem_req_data; + for (i = 0; i < `NUM_THREADS; ++i) begin - assign mem_req_addr[i] = use_address[i][31:2]; - assign mem_req_offset[i] = (5'(use_address[i][1:0])) << 3; - assign mem_req_byteen[i] = (wmask << use_address[i][1:0]); - assign mem_req_data[i] = (use_store_data[i] << mem_req_offset[i]); - end + assign mem_req_addr[i] = full_address[i][31:2]; + assign mem_req_offset[i] = full_address[i][1:0]; + assign mem_req_byteen[i] = wmask << full_address[i][1:0]; + assign mem_req_data[i] = lsu_req_if.store_data[i] << {mem_req_offset[i], 3'b0}; + end + +`IGNORE_WARNINGS_BEGIN + wire[`NUM_THREADS-1:0][31:0] use_address; +`IGNORE_WARNINGS_END + + VX_generic_register #( + .N((`NUM_THREADS * 1) + (`NUM_THREADS * 32) + `BYTE_EN_BITS + 1 + (`NUM_THREADS * (30 + 2 + 4 + 32)) + 5 + `NW_BITS + 2 + 32) + ) lsu_buffer ( + .clk (clk), + .reset (reset), + .stall (delay), + .flush (1'b0), + .in ({lsu_req_if.valid, full_address, lsu_req_if.mem_read, mem_req_rw, mem_req_addr, mem_req_offset, mem_req_byteen, mem_req_data, lsu_req_if.rd, lsu_req_if.warp_num, lsu_req_if.wb, lsu_req_if.curr_PC}), + .out ({use_valid , use_address, use_mem_read , use_req_rw, use_req_addr, use_req_offset, use_req_byteen, use_req_data, use_rd , use_warp_num , use_wb , use_pc}) + ); + + wire [`NUM_THREADS-1:0][1:0] mem_rsp_offset; + wire [`BYTE_EN_BITS-1:0] core_rsp_mem_read; reg [`NUM_THREADS-1:0] mem_rsp_mask[`DCREQ_SIZE-1:0]; @@ -84,7 +90,7 @@ module VX_lsu_unit #( wire mrq_full; wire mrq_push = (| dcache_req_if.valid) && dcache_req_if.ready - && (0 == core_req_rw); // only push read requests + && (0 == use_req_rw); // only push read requests wire mrq_pop_part = (| dcache_rsp_if.valid) && dcache_rsp_if.ready; @@ -95,18 +101,18 @@ module VX_lsu_unit #( wire mrq_pop = mrq_pop_part && (0 == mem_rsp_mask_upd); VX_indexable_queue #( - .DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 5) + `BYTE_EN_BITS + 5 + `NW_BITS), + .DATAW (`LOG2UP(`DCREQ_SIZE) + 32 + 2 + (`NUM_THREADS * 2) + `BYTE_EN_BITS + 5 + `NW_BITS), .SIZE (`DCREQ_SIZE) ) mem_req_queue ( .clk (clk), .reset (reset), - .write_data ({mrq_write_addr, use_pc, use_wb, mem_req_offset, use_mem_read, use_rd, use_warp_num}), + .write_data ({mrq_write_addr, use_pc, use_wb, use_req_offset, use_mem_read, use_rd, use_warp_num}), .write_addr (mrq_write_addr), .push (mrq_push), .full (mrq_full), .pop (mrq_pop), .read_addr (mrq_read_addr), - .read_data ({dbg_mrq_write_addr, mem_wb_if.curr_PC, mem_wb_if.wb, mem_rsp_offset, core_rsp_mem_read, mem_wb_if.rd, mem_wb_if.warp_num}), + .read_data ({dbg_mrq_write_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.wb, mem_rsp_offset, core_rsp_mem_read, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num}), `UNUSED_PIN (empty) ); @@ -122,11 +128,11 @@ module VX_lsu_unit #( // Core Request - assign dcache_req_if.valid = use_valid & {`NUM_THREADS{~mrq_full}}; - assign dcache_req_if.rw = {`NUM_THREADS{core_req_rw}}; - assign dcache_req_if.byteen= mem_req_byteen; - assign dcache_req_if.addr = mem_req_addr; - assign dcache_req_if.data = mem_req_data; + assign dcache_req_if.valid = use_valid & {`NUM_THREADS{~mrq_full}}; + assign dcache_req_if.rw = {`NUM_THREADS{use_req_rw}}; + assign dcache_req_if.byteen = use_req_byteen; + assign dcache_req_if.addr = use_req_addr; + assign dcache_req_if.data = use_req_data; `ifdef DBG_CORE_REQ_INFO assign dcache_req_if.tag = {use_pc, use_wb, use_rd, use_warp_num, mrq_write_addr}; @@ -143,33 +149,33 @@ module VX_lsu_unit #( wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; for (i = 0; i < `NUM_THREADS; ++i) begin - assign rsp_data_shifted[i] = (dcache_rsp_if.data[i] >> mem_rsp_offset[i]); + assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0}; always @(*) begin case (core_rsp_mem_read) - `BYTE_EN_SB: core_rsp_data[i] = rsp_data_shifted[i][7] ? (rsp_data_shifted[i] | 32'hFFFFFF00) : (rsp_data_shifted[i] & 32'h000000FF); - `BYTE_EN_SH: core_rsp_data[i] = rsp_data_shifted[i][15] ? (rsp_data_shifted[i] | 32'hFFFF0000) : (rsp_data_shifted[i] & 32'h0000FFFF); - `BYTE_EN_UB: core_rsp_data[i] = (rsp_data_shifted[i] & 32'h000000FF); - `BYTE_EN_UH: core_rsp_data[i] = (rsp_data_shifted[i] & 32'h0000FFFF); + `BYTE_EN_SB: core_rsp_data[i] = {{24{rsp_data_shifted[i][7]}}, rsp_data_shifted[i][7:0]}; + `BYTE_EN_SH: core_rsp_data[i] = {{16{rsp_data_shifted[i][15]}}, rsp_data_shifted[i][15:0]}; + `BYTE_EN_UB: core_rsp_data[i] = 32'(rsp_data_shifted[i][7:0]); + `BYTE_EN_UH: core_rsp_data[i] = 32'(rsp_data_shifted[i][15:0]); default : core_rsp_data[i] = rsp_data_shifted[i]; endcase end end - assign mem_wb_if.valid = dcache_rsp_if.valid; - assign mem_wb_if.data = core_rsp_data; + assign mem_wb_unqual_if.valid = dcache_rsp_if.valid; + assign mem_wb_unqual_if.data = core_rsp_data; // Can't accept new response - assign dcache_rsp_if.ready = !(no_slot_mem & (|mem_wb_if_p1.valid)); + assign dcache_rsp_if.ready = !(no_slot_mem & (|mem_wb_if.valid)); // From LSU to WB localparam WB_REQ_SIZE = (`NUM_THREADS) + (`NUM_THREADS * 32) + (`NW_BITS) + (5) + (2) + 32; - VX_generic_register #(.N(WB_REQ_SIZE)) lsu_to_wb( + VX_generic_register #(.N(WB_REQ_SIZE)) lsu_to_wb ( .clk (clk), .reset (reset), .stall (no_slot_mem), .flush (1'b0), - .in ({mem_wb_if.valid , mem_wb_if.data , mem_wb_if.warp_num , mem_wb_if.rd , mem_wb_if.wb , mem_wb_if.curr_PC }), - .out ({mem_wb_if_p1.valid, mem_wb_if_p1.data, mem_wb_if_p1.warp_num, mem_wb_if_p1.rd, mem_wb_if_p1.wb, mem_wb_if_p1.curr_PC}) + .in ({mem_wb_unqual_if.valid, mem_wb_unqual_if.data, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.rd, mem_wb_unqual_if.wb, mem_wb_unqual_if.curr_PC}), + .out ({mem_wb_if.valid, mem_wb_if.data, mem_wb_if.warp_num, mem_wb_if.rd, mem_wb_if.wb, mem_wb_if.curr_PC}) ); `SCOPE_ASSIGN(scope_dcache_req_valid, dcache_req_if.valid); @@ -190,12 +196,12 @@ module VX_lsu_unit #( `ifdef DBG_PRINT_CORE_DCACHE always @(posedge clk) begin if ((| dcache_req_if.valid) && dcache_req_if.ready) begin - $display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, r=%0d, w=%0d, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", - $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_mem_read, use_mem_write, use_pc, use_rd, use_warp_num, mem_req_byteen, mem_req_data); + $display("%t: D%0d$ req: valid=%b, addr=%0h, tag=%0h, rw=%0b, pc=%0h, rd=%0d, warp=%0d, byteen=%0h, data=%0h", + $time, CORE_ID, use_valid, use_address, mrq_write_addr, use_req_rw, use_pc, use_rd, use_warp_num, use_req_byteen, use_req_data); end if ((| dcache_rsp_if.valid) && dcache_rsp_if.ready) begin $display("%t: D%0d$ rsp: valid=%b, tag=%0h, pc=%0h, rd=%0d, warp=%0d, data=%0h", - $time, CORE_ID, mem_wb_if.valid, mrq_read_addr, mem_wb_if.curr_PC, mem_wb_if.rd, mem_wb_if.warp_num, mem_wb_if.data); + $time, CORE_ID, mem_wb_unqual_if.valid, mrq_read_addr, mem_wb_unqual_if.curr_PC, mem_wb_unqual_if.rd, mem_wb_unqual_if.warp_num, mem_wb_unqual_if.data); end end `endif diff --git a/hw/rtl/VX_warp_sched.v b/hw/rtl/VX_warp_sched.v index 81825e54..9621d47b 100644 --- a/hw/rtl/VX_warp_sched.v +++ b/hw/rtl/VX_warp_sched.v @@ -1,14 +1,14 @@ `include "VX_define.vh" module VX_warp_sched ( - input wire clk, // Clock - input wire reset, - input wire stall, + input wire clk, + input wire reset, + input wire stall, // Wspawn - input wire wspawn, - input wire[31:0] wsapwn_pc, - input wire[`NUM_WARPS-1:0] wspawn_new_active, + input wire wspawn, + input wire[31:0] wsapwn_pc, + input wire[`NUM_WARPS-1:0] wspawn_new_active, // CTM input wire ctm, @@ -28,38 +28,38 @@ module VX_warp_sched ( // WSTALL input wire wstall, - input wire[`NW_BITS-1:0] wstall_warp_num, + input wire [`NW_BITS-1:0] wstall_warp_num, // Split input wire is_split, input wire dont_split, - input wire[`NUM_THREADS-1:0] split_new_mask, - input wire[`NUM_THREADS-1:0] split_later_mask, - input wire[31:0] split_save_pc, - input wire[`NW_BITS-1:0] split_warp_num, + input wire [`NUM_THREADS-1:0] split_new_mask, + input wire [`NUM_THREADS-1:0] split_later_mask, + input wire [31:0] split_save_pc, + input wire [`NW_BITS-1:0] split_warp_num, // Join input wire is_join, - input wire[`NW_BITS-1:0] join_warp_num, + input wire [`NW_BITS-1:0] join_warp_num, // JAL input wire jal, - input wire[31:0] dest, - input wire[`NW_BITS-1:0] jal_warp_num, + input wire [31:0] dest, + input wire [`NW_BITS-1:0] jal_warp_num, // Branch input wire branch_valid, input wire branch_dir, - input wire[31:0] branch_dest, - input wire[`NW_BITS-1:0] branch_warp_num, + input wire [31:0] branch_dest, + input wire [`NW_BITS-1:0] branch_warp_num, - output wire[`NUM_THREADS-1:0] thread_mask, - output wire[`NW_BITS-1:0] warp_num, - output wire[31:0] warp_pc, + output wire [`NUM_THREADS-1:0] thread_mask, + output wire [`NW_BITS-1:0] warp_num, + output wire [31:0] warp_pc, output wire busy, output wire scheduled_warp, - input wire[`NW_BITS-1:0] icache_stage_wid, + input wire [`NW_BITS-1:0] icache_stage_wid, input wire icache_stage_response ); wire update_use_wspawn; @@ -209,18 +209,18 @@ module VX_warp_sched ( // Branch if (branch_valid) begin - if (branch_dir) warp_pcs[branch_warp_num] <= branch_dest; + if (branch_dir) begin + warp_pcs[branch_warp_num] <= branch_dest; + end warp_stalled[branch_warp_num] <= 0; end // Lock/Release if (scheduled_warp && !stall) begin warp_lock[warp_num] <= 1'b1; - // warp_lock <= {`NUM_WARPS{1'b1}}; end if (icache_stage_response) begin warp_lock[icache_stage_wid] <= 1'b0; - // warp_lock <= {`NUM_WARPS{1'b0}}; end end diff --git a/hw/rtl/cache/VX_cache_core_rsp_merge.v b/hw/rtl/cache/VX_cache_core_rsp_merge.v index 2f835ce1..849d8907 100644 --- a/hw/rtl/cache/VX_cache_core_rsp_merge.v +++ b/hw/rtl/cache/VX_cache_core_rsp_merge.v @@ -29,12 +29,7 @@ module VX_cache_core_rsp_merge #( input wire core_rsp_ready ); - reg [NUM_BANKS-1:0] per_bank_core_rsp_pop_unqual; - - assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}}; - wire [`BANK_BITS-1:0] main_bank_index; - wire grant_valid; VX_fair_arbiter #( .N(NUM_BANKS) ) sel_bank ( @@ -42,10 +37,14 @@ module VX_cache_core_rsp_merge #( .reset (reset), .requests (per_bank_core_rsp_valid), .grant_index (main_bank_index), - .grant_valid (grant_valid), + `UNUSED_PIN (grant_valid), `UNUSED_PIN (grant_onehot) ); + reg [NUM_BANKS-1:0] per_bank_core_rsp_pop_unqual; + + assign per_bank_core_rsp_ready = per_bank_core_rsp_pop_unqual & {NUM_BANKS{core_rsp_ready}}; + integer i; if (CORE_TAG_ID_BITS != 0) begin @@ -54,7 +53,7 @@ module VX_cache_core_rsp_merge #( core_rsp_valid = 0; core_rsp_data = 0; for (i = 0; i < NUM_BANKS; i++) begin - if (grant_valid && per_bank_core_rsp_valid[i] + if (per_bank_core_rsp_valid[i] && (per_bank_core_rsp_tag[i][CORE_TAG_ID_BITS-1:0] == per_bank_core_rsp_tag[main_bank_index][CORE_TAG_ID_BITS-1:0])) begin core_rsp_valid[per_bank_core_rsp_tid[i]] = 1; core_rsp_data[per_bank_core_rsp_tid[i]] = per_bank_core_rsp_data[i]; @@ -70,7 +69,7 @@ module VX_cache_core_rsp_merge #( core_rsp_data = 0; core_rsp_tag = 0; for (i = 0; i < NUM_BANKS; i++) begin - if (grant_valid && per_bank_core_rsp_valid[i] + if (per_bank_core_rsp_valid[i] && !core_rsp_valid[per_bank_core_rsp_tid[i]] && ((main_bank_index == `BANK_BITS'(i)) || (per_bank_core_rsp_tid[i] != per_bank_core_rsp_tid[main_bank_index]))) begin From bdfacf709cc47440dc1348f3234a63fc6c4adede Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 10 Jul 2020 18:56:41 -0400 Subject: [PATCH 18/22] yosys synthesis refactoring --- driver/rtlsim/Makefile | 2 +- hw/modelsim/Makefile | 4 +- hw/opae/sources.txt | 7 +- hw/rtl/{pipe_regs => }/VX_d_e_reg.v | 0 hw/rtl/{pipe_regs => }/VX_f_d_reg.v | 0 hw/rtl/{pipe_regs => }/VX_i_d_reg.v | 0 hw/rtl/VX_lsu_unit.v | 4 +- hw/rtl/Vortex.v | 116 ++++++++++++++-------------- hw/rtl/cache/VX_cache_miss_resrv.v | 2 +- hw/rtl/cache/VX_snp_forwarder.v | 2 +- hw/rtl/libs/VX_divide.v | 10 +-- hw/rtl/libs/VX_encoder_onehot.v | 11 ++- hw/rtl/libs/VX_fair_arbiter.v | 2 +- hw/rtl/libs/VX_fixed_arbiter.v | 2 +- hw/rtl/libs/VX_generic_queue.v | 4 +- hw/rtl/libs/VX_generic_register.v | 2 +- hw/rtl/libs/VX_indexable_queue.v | 4 +- hw/rtl/libs/VX_matrix_arbiter.v | 10 +-- hw/rtl/libs/VX_mult.v | 11 ++- hw/rtl/libs/VX_priority_encoder.v | 2 +- hw/rtl/libs/VX_rr_arbiter.v | 6 +- hw/simulate/Makefile | 2 +- hw/syn/quartus/core/Makefile | 2 +- hw/syn/quartus/pipeline/Makefile | 2 +- hw/syn/quartus/top/Makefile | 2 +- hw/syn/quartus/vortex/Makefile | 2 +- hw/syn/yosys/synth.sh | 32 ++++++++ hw/syn/yosys/synthesis.ys | 27 ------- 28 files changed, 136 insertions(+), 134 deletions(-) rename hw/rtl/{pipe_regs => }/VX_d_e_reg.v (100%) rename hw/rtl/{pipe_regs => }/VX_f_d_reg.v (100%) rename hw/rtl/{pipe_regs => }/VX_i_d_reg.v (100%) create mode 100755 hw/syn/yosys/synth.sh delete mode 100644 hw/syn/yosys/synthesis.ys diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index 82ab979b..d0890c4c 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -34,7 +34,7 @@ TOP = Vortex SRCS = vortex.cpp ../common/vx_utils.cpp ../../hw/simulate/simulator.cpp -RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/pipe_regs -I../../hw/rtl/cache +RTL_INCLUDE = -I../../hw/rtl -I../../hw/rtl/libs -I../../hw/rtl/interfaces -I../../hw/rtl/cache VL_FLAGS += --language 1800-2009 --assert -Wall -Wpedantic $(CONFIGS) VL_FLAGS += -Wno-DECLFILENAME diff --git a/hw/modelsim/Makefile b/hw/modelsim/Makefile index 16cec83a..6a7b6244 100644 --- a/hw/modelsim/Makefile +++ b/hw/modelsim/Makefile @@ -69,8 +69,8 @@ SRC = \ ../rtl/cache/VX_generic_pe.v \ ../rtl/cache/cache_set.v \ ../rtl/cache/VX_cache_data_per_index.v \ -../rtl/pipe_regs/VX_d_e_reg.v \ -../rtl/pipe_regs/VX_f_d_reg.v \ +../rtl/VX_d_e_reg.v \ +../rtl/VX_f_d_reg.v \ ../models/memory/cln28hpm/rf2_128x128_wm1/rf2_128x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x128_wm1/rf2_256x128_wm1.v \ ../models/memory/cln28hpm/rf2_256x19_wm0/rf2_256x19_wm0.v \ diff --git a/hw/opae/sources.txt b/hw/opae/sources.txt index e8d0480c..0b448e88 100644 --- a/hw/opae/sources.txt +++ b/hw/opae/sources.txt @@ -103,10 +103,9 @@ QI:vortex_afu.qsf ../rtl/VX_inst_multiplex.v ../rtl/VX_dcache_arb.v ../rtl/VX_mem_arb.v - -../rtl/pipe_regs/VX_f_d_reg.v -../rtl/pipe_regs/VX_i_d_reg.v -../rtl/pipe_regs/VX_d_e_reg.v +../rtl/VX_f_d_reg.v +../rtl/VX_i_d_reg.v +../rtl/VX_d_e_reg.v ccip_interface_reg.sv ccip_std_afu.sv diff --git a/hw/rtl/pipe_regs/VX_d_e_reg.v b/hw/rtl/VX_d_e_reg.v similarity index 100% rename from hw/rtl/pipe_regs/VX_d_e_reg.v rename to hw/rtl/VX_d_e_reg.v diff --git a/hw/rtl/pipe_regs/VX_f_d_reg.v b/hw/rtl/VX_f_d_reg.v similarity index 100% rename from hw/rtl/pipe_regs/VX_f_d_reg.v rename to hw/rtl/VX_f_d_reg.v diff --git a/hw/rtl/pipe_regs/VX_i_d_reg.v b/hw/rtl/VX_i_d_reg.v similarity index 100% rename from hw/rtl/pipe_regs/VX_i_d_reg.v rename to hw/rtl/VX_i_d_reg.v diff --git a/hw/rtl/VX_lsu_unit.v b/hw/rtl/VX_lsu_unit.v index f2f8af73..d1296680 100644 --- a/hw/rtl/VX_lsu_unit.v +++ b/hw/rtl/VX_lsu_unit.v @@ -59,7 +59,7 @@ module VX_lsu_unit #( wire [`NUM_THREADS-1:0][3:0] mem_req_byteen; wire [`NUM_THREADS-1:0][31:0] mem_req_data; - for (i = 0; i < `NUM_THREADS; ++i) begin + for (i = 0; i < `NUM_THREADS; i++) begin assign mem_req_addr[i] = full_address[i][31:2]; assign mem_req_offset[i] = full_address[i][1:0]; assign mem_req_byteen[i] = wmask << full_address[i][1:0]; @@ -148,7 +148,7 @@ module VX_lsu_unit #( reg [`NUM_THREADS-1:0][31:0] core_rsp_data; wire [`NUM_THREADS-1:0][31:0] rsp_data_shifted; - for (i = 0; i < `NUM_THREADS; ++i) begin + for (i = 0; i < `NUM_THREADS; i++) begin assign rsp_data_shifted[i] = dcache_rsp_if.data[i] >> {mem_rsp_offset[i], 3'b0}; always @(*) begin case (core_rsp_mem_read) diff --git a/hw/rtl/Vortex.v b/hw/rtl/Vortex.v index a606c15f..dfbf0e4a 100644 --- a/hw/rtl/Vortex.v +++ b/hw/rtl/Vortex.v @@ -139,54 +139,54 @@ module Vortex ( end else begin - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_req_rw; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag; - wire l3_core_req_ready; + wire per_cluster_dram_req_valid [`NUM_CLUSTERS-1:0]; + wire per_cluster_dram_req_rw [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_BYTEEN_WIDTH-1:0] per_cluster_dram_req_byteen [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_dram_req_addr [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_req_data [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_req_tag [`NUM_CLUSTERS-1:0]; + wire l3_core_req_ready; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_dram_rsp_ready; + wire per_cluster_dram_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] per_cluster_dram_rsp_data [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] per_cluster_dram_rsp_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_dram_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_req_ready; + wire per_cluster_snp_req_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] per_cluster_snp_req_addr [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_req_invalidate [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_req_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_snp_rsp_ready; + wire per_cluster_snp_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] per_cluster_snp_rsp_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_snp_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_valid; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_rw; - wire [`NUM_CLUSTERS-1:0][3:0] per_cluster_io_req_byteen; - wire [`NUM_CLUSTERS-1:0][29:0] per_cluster_io_req_addr; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_req_data; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_req_ready; + wire per_cluster_io_req_valid [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_req_rw [`NUM_CLUSTERS-1:0]; + wire [3:0] per_cluster_io_req_byteen [`NUM_CLUSTERS-1:0]; + wire [29:0] per_cluster_io_req_addr [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_io_req_data [`NUM_CLUSTERS-1:0]; + wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_req_tag [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_valid; - wire [`NUM_CLUSTERS-1:0][`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_io_rsp_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_io_rsp_ready; + wire per_cluster_io_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [`L2CORE_TAG_WIDTH-1:0] per_cluster_io_rsp_tag [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_io_rsp_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_io_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_valid; - wire [`NUM_CLUSTERS-1:0][11:0] per_cluster_csr_io_req_addr; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_rw; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_req_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_req_ready; + wire per_cluster_csr_io_req_valid [`NUM_CLUSTERS-1:0]; + wire [11:0] per_cluster_csr_io_req_addr [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_req_rw [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_csr_io_req_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_req_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_valid; - wire [`NUM_CLUSTERS-1:0][31:0] per_cluster_csr_io_rsp_data; - wire [`NUM_CLUSTERS-1:0] per_cluster_csr_io_rsp_ready; + wire per_cluster_csr_io_rsp_valid [`NUM_CLUSTERS-1:0]; + wire [31:0] per_cluster_csr_io_rsp_data [`NUM_CLUSTERS-1:0]; + wire per_cluster_csr_io_rsp_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] per_cluster_busy; - wire [`NUM_CLUSTERS-1:0] per_cluster_ebreak; + wire per_cluster_busy [`NUM_CLUSTERS-1:0]; + wire per_cluster_ebreak [`NUM_CLUSTERS-1:0]; wire [`CLOG2(`NUM_CLUSTERS)-1:0] csr_io_request_id = `CLOG2(`NUM_CLUSTERS)'(csr_io_req_coreid >> `CLOG2(`NUM_CLUSTERS)); wire [`NC_BITS-1:0] per_cluster_csr_io_req_coreid = `NC_BITS'(csr_io_req_coreid); @@ -336,27 +336,27 @@ module Vortex ( // L3 Cache /////////////////////////////////////////////////////////// - wire [`L3NUM_REQUESTS-1:0] l3_core_req_valid; - wire [`L3NUM_REQUESTS-1:0] l3_core_req_rw; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag; + wire l3_core_req_valid [`L3NUM_REQUESTS-1:0]; + wire l3_core_req_rw [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_BYTEEN_WIDTH-1:0] l3_core_req_byteen [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] l3_core_req_addr [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_req_data [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_req_tag [`L3NUM_REQUESTS-1:0]; - wire [`L3NUM_REQUESTS-1:0] l3_core_rsp_valid; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data; - wire [`L3NUM_REQUESTS-1:0][`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag; - wire l3_core_rsp_ready; + wire l3_core_rsp_valid [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_LINE_WIDTH-1:0] l3_core_rsp_data [`L3NUM_REQUESTS-1:0]; + wire [`L2DRAM_TAG_WIDTH-1:0] l3_core_rsp_tag [`L3NUM_REQUESTS-1:0]; + wire l3_core_rsp_ready; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_valid; - wire [`NUM_CLUSTERS-1:0][`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_invalidate; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdout_ready; + wire l3_snp_fwdout_valid [`NUM_CLUSTERS-1:0]; + wire [`L2DRAM_ADDR_WIDTH-1:0] l3_snp_fwdout_addr [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdout_invalidate [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdout_tag [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdout_ready [`NUM_CLUSTERS-1:0]; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_valid; - wire [`NUM_CLUSTERS-1:0][`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag; - wire [`NUM_CLUSTERS-1:0] l3_snp_fwdin_ready; + wire l3_snp_fwdin_valid [`NUM_CLUSTERS-1:0]; + wire [`L2SNP_TAG_WIDTH-1:0] l3_snp_fwdin_tag [`NUM_CLUSTERS-1:0]; + wire l3_snp_fwdin_ready [`NUM_CLUSTERS-1:0]; for (i = 0; i < `L3NUM_REQUESTS; i++) begin // Core Request diff --git a/hw/rtl/cache/VX_cache_miss_resrv.v b/hw/rtl/cache/VX_cache_miss_resrv.v index d4e6d5ee..c851629c 100644 --- a/hw/rtl/cache/VX_cache_miss_resrv.v +++ b/hw/rtl/cache/VX_cache_miss_resrv.v @@ -66,7 +66,7 @@ module VX_cache_miss_resrv #( reg [`LOG2UP(MRVQ_SIZE+1)-1:0] size; - `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size"); + `STATIC_ASSERT(MRVQ_SIZE > 5, "invalid size") assign miss_resrv_full = (size == $bits(size)'(MRVQ_SIZE)); assign miss_resrv_stop = (size > $bits(size)'(MRVQ_SIZE-5)); // need to add 5 cycles to prevent pipeline lock diff --git a/hw/rtl/cache/VX_snp_forwarder.v b/hw/rtl/cache/VX_snp_forwarder.v index 0536d393..f54b6eba 100644 --- a/hw/rtl/cache/VX_snp_forwarder.v +++ b/hw/rtl/cache/VX_snp_forwarder.v @@ -37,7 +37,7 @@ module VX_snp_forwarder #( input wire [NUM_REQUESTS-1:0][`LOG2UP(SNRQ_SIZE)-1:0] snp_fwdin_tag, output wire [NUM_REQUESTS-1:0] snp_fwdin_ready ); - `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value"); + `STATIC_ASSERT(NUM_REQUESTS > 1, "invalid value") reg [`REQS_BITS:0] pending_cntrs [SNRQ_SIZE-1:0]; diff --git a/hw/rtl/libs/VX_divide.v b/hw/rtl/libs/VX_divide.v index f32aeb13..510abf26 100644 --- a/hw/rtl/libs/VX_divide.v +++ b/hw/rtl/libs/VX_divide.v @@ -10,11 +10,11 @@ module VX_divide #( input wire clk, input wire reset, - input [WIDTHN-1:0] numer, - input [WIDTHD-1:0] denom, + input wire [WIDTHN-1:0] numer, + input wire [WIDTHD-1:0] denom, - output reg [WIDTHN-1:0] quotient, - output reg [WIDTHD-1:0] remainder + output wire [WIDTHN-1:0] quotient, + output wire [WIDTHD-1:0] remainder ); `ifdef QUARTUS @@ -36,7 +36,7 @@ module VX_divide #( quartus_div.lpm_nrepresentation = NSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_drepresentation = DSIGNED ? "SIGNED" : "UNSIGNED", quartus_div.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=FALSE", - quartus_div.lpm_pipeline = PIPELINE; + quartus_div.lpm_pipeline = PIPELINE; `else diff --git a/hw/rtl/libs/VX_encoder_onehot.v b/hw/rtl/libs/VX_encoder_onehot.v index e5e06ff0..a4e0e72e 100644 --- a/hw/rtl/libs/VX_encoder_onehot.v +++ b/hw/rtl/libs/VX_encoder_onehot.v @@ -3,20 +3,19 @@ module VX_encoder_onehot #( parameter N = 6 ) ( - input wire [N-1:0] onehot, - output reg valid, - output reg [`LOG2UP(N)-1:0] value + input wire [N-1:0] onehot, + output reg [`LOG2UP(N)-1:0] binary, + output reg valid ); integer i; always @(*) begin valid = 1'b0; - value = {`LOG2UP(N){1'bx}}; + binary = `LOG2UP(N)'(0); for (i = 0; i < N; i++) begin if (onehot[i]) begin valid = 1'b1; - value = `LOG2UP(N)'(i); - break; + binary = `LOG2UP(N)'(i); end end end diff --git a/hw/rtl/libs/VX_fair_arbiter.v b/hw/rtl/libs/VX_fair_arbiter.v index 5ac5749e..9ffc1ecd 100644 --- a/hw/rtl/libs/VX_fair_arbiter.v +++ b/hw/rtl/libs/VX_fair_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_fair_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_fixed_arbiter.v b/hw/rtl/libs/VX_fixed_arbiter.v index 0ce69146..7f6fbfa3 100644 --- a/hw/rtl/libs/VX_fixed_arbiter.v +++ b/hw/rtl/libs/VX_fixed_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_fixed_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_generic_queue.v b/hw/rtl/libs/VX_generic_queue.v index 52e12831..a666948b 100644 --- a/hw/rtl/libs/VX_generic_queue.v +++ b/hw/rtl/libs/VX_generic_queue.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_generic_queue #( - parameter DATAW, + parameter DATAW = 1, parameter SIZE = 16, parameter BUFFERED_OUTPUT = 1 ) ( @@ -15,7 +15,7 @@ module VX_generic_queue #( output wire full, output wire [`LOG2UP(SIZE+1)-1:0] size ); - `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!"); + `STATIC_ASSERT(`ISPOW2(SIZE), "must be 0 or power of 2!") reg [`LOG2UP(SIZE+1)-1:0] size_r; wire reading; diff --git a/hw/rtl/libs/VX_generic_register.v b/hw/rtl/libs/VX_generic_register.v index 869efdd4..7234b0a2 100644 --- a/hw/rtl/libs/VX_generic_register.v +++ b/hw/rtl/libs/VX_generic_register.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_generic_register #( - parameter N, + parameter N = 1, parameter PASSTHRU = 0 ) ( input wire clk, diff --git a/hw/rtl/libs/VX_indexable_queue.v b/hw/rtl/libs/VX_indexable_queue.v index b6749e81..886b05f6 100644 --- a/hw/rtl/libs/VX_indexable_queue.v +++ b/hw/rtl/libs/VX_indexable_queue.v @@ -1,8 +1,8 @@ `include "VX_define.vh" module VX_indexable_queue #( - parameter DATAW, - parameter SIZE + parameter DATAW = 1, + parameter SIZE = 1 ) ( input wire clk, input wire reset, diff --git a/hw/rtl/libs/VX_matrix_arbiter.v b/hw/rtl/libs/VX_matrix_arbiter.v index 1d578166..8c467974 100644 --- a/hw/rtl/libs/VX_matrix_arbiter.v +++ b/hw/rtl/libs/VX_matrix_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_matrix_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, @@ -27,8 +27,8 @@ module VX_matrix_arbiter #( genvar i, j; - for (i = 0; i < N; ++i) begin - for (j = 0; j < N; ++j) begin + for (i = 0; i < N; i++) begin + for (j = 0; j < N; j++) begin if (j > i) begin assign pri[j][i] = requests[i] && state[i][j]; end @@ -43,8 +43,8 @@ module VX_matrix_arbiter #( assign grant_onehot[i] = requests[i] && !(| pri[i]); end - for (i = 0; i < N; ++i) begin - for (j = i + 1; j < N; ++j) begin + for (i = 0; i < N; i++) begin + for (j = i + 1; j < N; j++) begin always @(posedge clk) begin if (reset) begin state[i][j] <= 0; diff --git a/hw/rtl/libs/VX_mult.v b/hw/rtl/libs/VX_mult.v index 16d47d6d..1dd77aea 100644 --- a/hw/rtl/libs/VX_mult.v +++ b/hw/rtl/libs/VX_mult.v @@ -7,13 +7,12 @@ module VX_mult #( parameter SIGNED = 0, parameter PIPELINE = 0 ) ( - input clk, - input reset, + input wire clk, + input wire reset, - input [WIDTHA-1:0] dataa, - input [WIDTHB-1:0] datab, - - output reg [WIDTHP-1:0] result + input wire [WIDTHA-1:0] dataa, + input wire [WIDTHB-1:0] datab, + output wire [WIDTHP-1:0] result ); `ifdef QUARTUS diff --git a/hw/rtl/libs/VX_priority_encoder.v b/hw/rtl/libs/VX_priority_encoder.v index e98a17d6..24c91724 100644 --- a/hw/rtl/libs/VX_priority_encoder.v +++ b/hw/rtl/libs/VX_priority_encoder.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_priority_encoder #( - parameter N + parameter N = 1 ) ( input wire [N-1:0] data_in, output reg [`LOG2UP(N)-1:0] data_out, diff --git a/hw/rtl/libs/VX_rr_arbiter.v b/hw/rtl/libs/VX_rr_arbiter.v index d093cd60..fb19e108 100644 --- a/hw/rtl/libs/VX_rr_arbiter.v +++ b/hw/rtl/libs/VX_rr_arbiter.v @@ -1,7 +1,7 @@ `include "VX_define.vh" module VX_rr_arbiter #( - parameter N = 0 + parameter N = 1 ) ( input wire clk, input wire reset, @@ -29,9 +29,9 @@ module VX_rr_arbiter #( integer i, j; always @(*) begin - for (i = 0; i < N; ++i) begin + for (i = 0; i < N; i++) begin grant_table[i] = `CLOG2(N)'(i); - for (j = 0; j < N; ++j) begin + for (j = 0; j < N; j++) begin if (requests[(i+j) % N]) begin grant_table[i] = `CLOG2(N)'((i+j) % N); end diff --git a/hw/simulate/Makefile b/hw/simulate/Makefile index 21814760..7b665714 100644 --- a/hw/simulate/Makefile +++ b/hw/simulate/Makefile @@ -15,7 +15,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_OPAE #DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CORE_REQ_INFO -INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/pipe_regs -I../rtl/cache -I../rtl/simulate +INCLUDE = -I../rtl/ -I../rtl/libs -I../rtl/interfaces -I../rtl/cache -I../rtl/simulate SRCS = simulator.cpp testbench.cpp diff --git a/hw/syn/quartus/core/Makefile b/hw/syn/quartus/core/Makefile index 69ab23ab..0968b478 100644 --- a/hw/syn/quartus/core/Makefile +++ b/hw/syn/quartus/core/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/pipeline/Makefile b/hw/syn/quartus/pipeline/Makefile index b2ed2d5e..49232fe8 100644 --- a/hw/syn/quartus/pipeline/Makefile +++ b/hw/syn/quartus/pipeline/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/top/Makefile b/hw/syn/quartus/top/Makefile index dbb4844f..c6219230 100644 --- a/hw/syn/quartus/top/Makefile +++ b/hw/syn/quartus/top/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache;../../../opae;../../../opae/ccip" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -set "NOPAE" -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache;../../../opae;../../../opae/ccip" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/quartus/vortex/Makefile b/hw/syn/quartus/vortex/Makefile index 4e9badb1..f8db7cc8 100644 --- a/hw/syn/quartus/vortex/Makefile +++ b/hw/syn/quartus/vortex/Makefile @@ -49,7 +49,7 @@ smart.log: $(PROJECT_FILES) # Project initialization $(PROJECT_FILES): - quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/pipe_regs;../../../rtl/cache" + quartus_sh -t ../project.tcl -project $(PROJECT) -family $(FAMILY) -device $(DEVICE) -top $(TOP_LEVEL_ENTITY) -src $(SRC_FILE) -sdc ../project.sdc -inc "../../../rtl;../../../rtl/libs;../../../rtl/interfaces;../../../rtl/cache" syn.chg: $(STAMP) syn.chg diff --git a/hw/syn/yosys/synth.sh b/hw/syn/yosys/synth.sh new file mode 100755 index 00000000..621866f1 --- /dev/null +++ b/hw/syn/yosys/synth.sh @@ -0,0 +1,32 @@ +#!/bin/bash + +dir_list='../../rtl/libs ../../rtl/cache ../../rtl/interfaces ../../rtl' + +inc_list="" +for dir in $dir_list; do + inc_list="$inc_list -I$dir" +done + +echo "inc_list=$inc_list" + +{ + # read design sources + for dir in $dir_list; do + for file in $(find $dir -name '*.v' -o -name '*.sv' -type f) + do + echo "read_verilog -sv $inc_list $file" + done + done + + echo "hierarchy -check -top Vortex" + + # insertation of global reset + echo "add -global_input reset 1" + echo "proc -global_arst reset" + + echo "synth -run coarse; opt -fine" + echo "tee -o brams.log memory_bram -rules scripts/brams.txt;;" + echo "write_verilog -noexpr -noattr synth.v" +} > synth.ys + +yosys -l synth.log synth.ys \ No newline at end of file diff --git a/hw/syn/yosys/synthesis.ys b/hw/syn/yosys/synthesis.ys deleted file mode 100644 index fd208160..00000000 --- a/hw/syn/yosys/synthesis.ys +++ /dev/null @@ -1,27 +0,0 @@ -# load design -read_verilog -sv -I../../rtl -I../../rtl/libs -I../../rtl/interfaces -I../../rtl/pipe_regs -I../../rtl/cache ../../rtl/Vortex.v - -# high-level synthesis -proc; opt; fsm;; memory -nomap; opt - -# substitute block rams -techmap -map map_rams.v - -# map remaining memories -memory_map - -# low-level synthesis -techmap; opt; flatten;; abc -lut6 -techmap -map map_xl_cells.v - -# add clock buffers -select -set xl_clocks t:FDRE %x:+FDRE[C] t:FDRE %d -iopadmap -inpad BUFGP O:I @xl_clocks - -# add io buffers -select -set xl_nonclocks w:* t:BUFGP %x:+BUFGP[I] %d -iopadmap -outpad OBUF I:O -inpad IBUF O:I @xl_nonclocks - -# write synthesis results -write_edif synth.edif - From 9cf8bf6149efd55cfd7f420ede03d4eac13ce438 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Fri, 10 Jul 2020 19:31:40 -0400 Subject: [PATCH 19/22] pipereg refactoring --- hw/rtl/VX_d_e_reg.v | 30 -------------------------- hw/rtl/VX_f_d_reg.v | 27 ----------------------- hw/rtl/VX_front_end.v | 50 ++++++++++++++++++++++++------------------- hw/rtl/VX_i_d_reg.v | 27 ----------------------- 4 files changed, 28 insertions(+), 106 deletions(-) delete mode 100644 hw/rtl/VX_d_e_reg.v delete mode 100644 hw/rtl/VX_f_d_reg.v delete mode 100644 hw/rtl/VX_i_d_reg.v diff --git a/hw/rtl/VX_d_e_reg.v b/hw/rtl/VX_d_e_reg.v deleted file mode 100644 index 93ae5ac0..00000000 --- a/hw/rtl/VX_d_e_reg.v +++ /dev/null @@ -1,30 +0,0 @@ -`include "VX_define.vh" - -module VX_d_e_reg ( - input wire clk, - input wire reset, - input wire branch_stall, - input wire freeze, - VX_backend_req_if frE_to_bckE_req_if, - VX_backend_req_if bckE_req_if -); - - wire stall = freeze; - wire flush = (branch_stall != 0); - - VX_generic_register #( - .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) - ) d_e_reg ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (flush), - .in ({frE_to_bckE_req_if.csr_addr, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}), - .out ({bckE_req_if.csr_addr , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier }) - ); - -endmodule - - - - diff --git a/hw/rtl/VX_f_d_reg.v b/hw/rtl/VX_f_d_reg.v deleted file mode 100644 index 59cf4506..00000000 --- a/hw/rtl/VX_f_d_reg.v +++ /dev/null @@ -1,27 +0,0 @@ -`include "VX_define.vh" - -module VX_f_d_reg ( - input wire clk, - input wire reset, - input wire freeze, - - VX_inst_meta_if fe_inst_meta_fd, - VX_inst_meta_if fd_inst_meta_de - -); - - wire flush = 1'b0; - wire stall = freeze == 1'b1; - - VX_generic_register #( - .N(64+`NW_BITS-1+1+`NUM_THREADS) - ) f_d_reg ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) - ); - -endmodule \ No newline at end of file diff --git a/hw/rtl/VX_front_end.v b/hw/rtl/VX_front_end.v index 9d17227c..8ceba8df 100644 --- a/hw/rtl/VX_front_end.v +++ b/hw/rtl/VX_front_end.v @@ -54,12 +54,15 @@ module VX_front_end #( .fe_inst_meta_fi (fe_inst_meta_fi) ); - VX_f_d_reg f_i_reg ( - .clk (clk), - .reset (reset), - .freeze (icache_stage_delay), - .fe_inst_meta_fd (fe_inst_meta_fi), - .fd_inst_meta_de (fe_inst_meta_fi2) + VX_generic_register #( + .N(64+`NW_BITS-1+1+`NUM_THREADS) + ) f_d_reg ( + .clk (clk), + .reset (reset), + .stall (icache_stage_delay), + .flush (1'b0), + .in ({fe_inst_meta_fi.instruction, fe_inst_meta_fi.curr_PC, fe_inst_meta_fi.warp_num, fe_inst_meta_fi.valid}), + .out ({fe_inst_meta_fi2.instruction, fe_inst_meta_fi2.curr_PC, fe_inst_meta_fi2.warp_num, fe_inst_meta_fi2.valid}) ); VX_icache_stage #( @@ -79,12 +82,15 @@ module VX_front_end #( .icache_req_if (icache_req_if) ); - VX_i_d_reg i_d_reg ( - .clk (clk), - .reset (reset), - .freeze (total_freeze), - .fe_inst_meta_fd (fe_inst_meta_id), - .fd_inst_meta_de (fd_inst_meta_de) + VX_generic_register #( + .N(64 + `NW_BITS-1 + 1 + `NUM_THREADS) + ) i_d_reg ( + .clk (clk), + .reset (reset), + .stall (total_freeze), + .flush (1'b0), + .in ({fe_inst_meta_id.instruction, fe_inst_meta_id.curr_PC, fe_inst_meta_id.warp_num, fe_inst_meta_id.valid}), + .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) ); VX_decode decode ( @@ -94,16 +100,16 @@ module VX_front_end #( .join_if (join_if) ); - wire no_br_stall = 0; - - VX_d_e_reg d_e_reg ( - .clk (clk), - .reset (reset), - .branch_stall (no_br_stall), - .freeze (total_freeze), - .frE_to_bckE_req_if (frE_to_bckE_req_if), - .bckE_req_if (bckE_req_if) - ); + VX_generic_register #( + .N(233 + `NW_BITS-1 + 1 + `NUM_THREADS) + ) d_e_reg ( + .clk (clk), + .reset (reset), + .stall (total_freeze), + .flush (1'b0), + .in ({frE_to_bckE_req_if.csr_addr, frE_to_bckE_req_if.is_jal, frE_to_bckE_req_if.is_etype, frE_to_bckE_req_if.is_csr, frE_to_bckE_req_if.csr_immed, frE_to_bckE_req_if.csr_mask, frE_to_bckE_req_if.rd, frE_to_bckE_req_if.rs1, frE_to_bckE_req_if.rs2, frE_to_bckE_req_if.alu_op, frE_to_bckE_req_if.wb, frE_to_bckE_req_if.rs2_src, frE_to_bckE_req_if.itype_immed, frE_to_bckE_req_if.mem_read, frE_to_bckE_req_if.mem_write, frE_to_bckE_req_if.branch_type, frE_to_bckE_req_if.upper_immed, frE_to_bckE_req_if.curr_PC, frE_to_bckE_req_if.jal, frE_to_bckE_req_if.jal_offset, frE_to_bckE_req_if.next_PC, frE_to_bckE_req_if.valid, frE_to_bckE_req_if.warp_num, frE_to_bckE_req_if.is_wspawn, frE_to_bckE_req_if.is_tmc, frE_to_bckE_req_if.is_split, frE_to_bckE_req_if.is_barrier}), + .out ({bckE_req_if.csr_addr , bckE_req_if.is_jal , bckE_req_if.is_etype ,bckE_req_if.is_csr , bckE_req_if.csr_immed , bckE_req_if.csr_mask , bckE_req_if.rd , bckE_req_if.rs1 , bckE_req_if.rs2 , bckE_req_if.alu_op , bckE_req_if.wb , bckE_req_if.rs2_src , bckE_req_if.itype_immed , bckE_req_if.mem_read , bckE_req_if.mem_write , bckE_req_if.branch_type , bckE_req_if.upper_immed , bckE_req_if.curr_PC , bckE_req_if.jal , bckE_req_if.jal_offset , bckE_req_if.next_PC , bckE_req_if.valid , bckE_req_if.warp_num , bckE_req_if.is_wspawn , bckE_req_if.is_tmc , bckE_req_if.is_split , bckE_req_if.is_barrier }) + ); endmodule diff --git a/hw/rtl/VX_i_d_reg.v b/hw/rtl/VX_i_d_reg.v deleted file mode 100644 index 2df17107..00000000 --- a/hw/rtl/VX_i_d_reg.v +++ /dev/null @@ -1,27 +0,0 @@ -`include "VX_define.vh" - -module VX_i_d_reg ( - input wire clk, - input wire reset, - input wire freeze, - - VX_inst_meta_if fe_inst_meta_fd, - VX_inst_meta_if fd_inst_meta_de - -); - - wire flush = 1'b0; - wire stall = freeze == 1'b1; - - VX_generic_register #( - .N(64 + `NW_BITS-1 + 1 + `NUM_THREADS) - ) i_d_reg ( - .clk (clk), - .reset (reset), - .stall (stall), - .flush (flush), - .in ({fe_inst_meta_fd.instruction, fe_inst_meta_fd.curr_PC, fe_inst_meta_fd.warp_num, fe_inst_meta_fd.valid}), - .out ({fd_inst_meta_de.instruction, fd_inst_meta_de.curr_PC, fd_inst_meta_de.warp_num, fd_inst_meta_de.valid}) - ); - -endmodule \ No newline at end of file From 0e8b9ec1c2af3396f9a627f0f7eb637814723844 Mon Sep 17 00:00:00 2001 From: trmontgomery Date: Mon, 13 Jul 2020 23:48:51 -0400 Subject: [PATCH 20/22] read and write complete --- hw/unit_tests/cache/.Makefile.swp | Bin 0 -> 12288 bytes hw/unit_tests/cache/Makefile | 4 +- hw/unit_tests/cache/cache_sim.cpp | 75 - hw/unit_tests/cache/cache_sim.h | 0 hw/unit_tests/cache/cachesim.cpp | 270 + hw/unit_tests/cache/cachesim.h | 89 + hw/unit_tests/cache/obj_dir/VVX_cache | Bin 0 -> 1206512 bytes hw/unit_tests/cache/obj_dir/VVX_cache.cpp | 42473 +++------------- hw/unit_tests/cache/obj_dir/VVX_cache.h | 1192 +- hw/unit_tests/cache/obj_dir/VVX_cache.mk | 9 +- hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a | Bin 0 -> 1089634 bytes .../cache/obj_dir/VVX_cache__ALLcls.cpp | 3 + .../cache/obj_dir/VVX_cache__ALLcls.d | 4 + .../cache/obj_dir/VVX_cache__ALLcls.o | Bin 0 -> 367912 bytes .../cache/obj_dir/VVX_cache__ALLsup.cpp | 5 + .../cache/obj_dir/VVX_cache__ALLsup.d | 6 + .../cache/obj_dir/VVX_cache__ALLsup.o | Bin 0 -> 716104 bytes .../cache/obj_dir/VVX_cache__Syms.cpp | 42 - hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h | 42 - .../cache/obj_dir/VVX_cache__Trace.cpp | 10566 +--- .../cache/obj_dir/VVX_cache__Trace__Slow.cpp | 18863 ++----- hw/unit_tests/cache/obj_dir/VVX_cache__ver.d | 1 + .../cache/obj_dir/VVX_cache__verFiles.dat | 37 + hw/unit_tests/cache/obj_dir/cache_sim.d | 6 + hw/unit_tests/cache/obj_dir/cache_sim.o | Bin 0 -> 6200 bytes hw/unit_tests/cache/obj_dir/cachesim.d | 6 + hw/unit_tests/cache/obj_dir/cachesim.o | Bin 0 -> 93048 bytes hw/unit_tests/cache/obj_dir/testbench.d | 6 + hw/unit_tests/cache/obj_dir/testbench.o | Bin 0 -> 5720 bytes hw/unit_tests/cache/obj_dir/verilated.d | 8 + hw/unit_tests/cache/obj_dir/verilated.o | Bin 0 -> 579016 bytes hw/unit_tests/cache/obj_dir/verilated_vcd_c.d | 4 + hw/unit_tests/cache/obj_dir/verilated_vcd_c.o | Bin 0 -> 232320 bytes hw/unit_tests/cache/ram.h | 64 + hw/unit_tests/cache/simulator.cpp | 83 - hw/unit_tests/cache/simulator.h | 52 - hw/unit_tests/cache/testbase.cpp | 59 - hw/unit_tests/cache/testbench.cpp | 49 +- hw/unit_tests/cache/trace.vcd | 20707 ++++++++ hw/unit_tests/cache/trace2.vcd | 9265 ++++ 40 files changed, 45511 insertions(+), 58479 deletions(-) create mode 100644 hw/unit_tests/cache/.Makefile.swp delete mode 100644 hw/unit_tests/cache/cache_sim.cpp delete mode 100644 hw/unit_tests/cache/cache_sim.h create mode 100644 hw/unit_tests/cache/cachesim.cpp create mode 100644 hw/unit_tests/cache/cachesim.h create mode 100755 hw/unit_tests/cache/obj_dir/VVX_cache create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.cpp create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.d create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ALLcls.o create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.cpp create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.d create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ALLsup.o create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__ver.d create mode 100644 hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat create mode 100644 hw/unit_tests/cache/obj_dir/cache_sim.d create mode 100644 hw/unit_tests/cache/obj_dir/cache_sim.o create mode 100644 hw/unit_tests/cache/obj_dir/cachesim.d create mode 100644 hw/unit_tests/cache/obj_dir/cachesim.o create mode 100644 hw/unit_tests/cache/obj_dir/testbench.d create mode 100644 hw/unit_tests/cache/obj_dir/testbench.o create mode 100644 hw/unit_tests/cache/obj_dir/verilated.d create mode 100644 hw/unit_tests/cache/obj_dir/verilated.o create mode 100644 hw/unit_tests/cache/obj_dir/verilated_vcd_c.d create mode 100644 hw/unit_tests/cache/obj_dir/verilated_vcd_c.o create mode 100644 hw/unit_tests/cache/ram.h delete mode 100644 hw/unit_tests/cache/simulator.cpp delete mode 100644 hw/unit_tests/cache/simulator.h delete mode 100644 hw/unit_tests/cache/testbase.cpp create mode 100644 hw/unit_tests/cache/trace.vcd create mode 100644 hw/unit_tests/cache/trace2.vcd diff --git a/hw/unit_tests/cache/.Makefile.swp b/hw/unit_tests/cache/.Makefile.swp new file mode 100644 index 0000000000000000000000000000000000000000..fe645a32b872279be51fddca51993ea8e17ac230 GIT binary patch literal 12288 zcmeI2&u`;I6vtnIO9ji1-IS9&9TWWAX;&oduS4^d}O?A4pRmoF09 z>qP(D`S&yTc7wiohsblIL`CVq)0-QpnHvuOH}$J|!9s70y0gOB7lmo)Cr+Z`BrbTa zccuzW_gtO$fqME2WmF7^foC%?O-{7ETiy5Wm9jtejk|aF&D-5)t0CE9Kn#chF(3xS zfEW-1Vn7T$*9MZw8hwo&ys+5C?&7)j*mDueLkx%kF(3xSfEW-1Vn7Ut0Wly3#DExh z4h^_NqWzbN)?UHl@&Etj@BgFMh+4n`P4F%t@aR>dpTPIvOYkYE0TXP4E%4VZqCdeO z;1}>S_!0a7z60Na4tO8j1uuaY!S7hZZ{QL570kc|I0scw0T002;4Sb5NZ0*0)-O#A zhygJm2E>3E5CdXB42Xdn4Xj^p(TKI^gvW!2&d`s@3zQok5UuZc!(}ILZE?QP>wV;8 zw{&w9O~V5oO#J}A9v)8|;R-Kn4_Q0m%NhC6d5*ID13pzDt<(C2iu}M$#u0Ds^lCZQ z49hU9-9y$qkC$)CUtqLdu`5j^=(R@Wu*2J%JNjz=GGUuFP0bW0bZotoW5SED4>GEU zyjw>7o^Cj;?s2<&j2!ejZM$wA=ZJc>EMax>=1$$x8(qW9El0JP=Hs@q?*@!p%b!ox za-biMHN(^!wR*#}Dou0QuLW*+I(1JKm-dQ9?Ow6Cj}^LctfGXqz8eGxlgRZHZ)p9A z8oFWPdqnztHE}X5d%L@(5=4$->?~1X?2p5kwR%2Z$mfYr;_@q`d*(7{-zWA*d2ce| z^kVfuh2B{j!Ng)qNL!RBL`hJ%7G(3U^#uMPCfd04RbFxDWM2dZ(-Xx|e3|96+7gzJ^Obb!ADiX-#r+4U zoUY1g)GgD=dP`}a)onUyf2VvOQNLvy^T9OIZS&|VYTCU;lua~h?bWbj*{h-6udYlr Lu0^$@ - -#include -#include - -uint64_t timestamp = 0; - -double sc_time_stamp() { - return timestamp; -} - -void tick(VVX_cache* tb){ - tb->eval(); - tb->clk = 1; - - tb->eval(); - tb->clk = 0; - tb->eval(); -} - -int main(int argc, char **argv){ - Verilated::commandArgs(argc, argv); //passes the command args to the object - - VVX_cache *tb = new VVX_cachee; - - //reset the cache - tb->reset = 1; - tb->eval(); - tb->reset = 0; - - //declare variables for output - data members in cache class - unsigned int clk; - bool full; - bool empty; - int size; - int data_out; - - //assign inputs - tb->core_req_valid = 1; - tb->core_req_rw = 1; - - char byte_en[] = {}; //word size 4 bytes - tb->core_req_byteen[0] = 1; - tb->core_req_byteen[1] = 1; - tb->core_req_byteen[2] = 1; - tb->core_req_byteen[3] = 1; - - char addr[4] = {0x1a, 0x2b, 0x3c, 0x4d}; //word addr width - - tb->core_req_addr[0] = arr[0]; - tb->core_req_addr[0] = arr[1]; - tb->core_req_addr[0] = arr[2]; - tb->core_req_addr[0] = arr[3]; - - //char req_data[] = {}; //word width - //tb->core_req_data - - //char req_tag[] = {}; //core_req_tag_count by core req_tag_width - //tb->core_req_tag = - - - for (int i = 0; i < 5; ++i){ - //toggle the clock - tick(tb); - } - - delete tb; - - exit(0); -} - diff --git a/hw/unit_tests/cache/cache_sim.h b/hw/unit_tests/cache/cache_sim.h deleted file mode 100644 index e69de29b..00000000 diff --git a/hw/unit_tests/cache/cachesim.cpp b/hw/unit_tests/cache/cachesim.cpp new file mode 100644 index 00000000..26d67b76 --- /dev/null +++ b/hw/unit_tests/cache/cachesim.cpp @@ -0,0 +1,270 @@ +#include "cachesim.h" +#include +#include +#include +#include + +uint64_t timestamp = 0; + +double sc_time_stamp() { + return timestamp; +} + +CacheSim::CacheSim() { + // force random values for uninitialized signals + Verilated::randReset(2); + + ram_ = nullptr; + cache_ = new VVX_cache(); + + dram_rsp_active_ = false; + snp_req_active_ = false; + +//#ifdef VCD_OUTPUT + Verilated::traceEverOn(true); + trace_ = new VerilatedVcdC; + cache_->trace(trace_, 99); + trace_->open("trace.vcd"); +//#endif +} + +CacheSim::~CacheSim() { +//#ifdef VCD_OUTPUT + trace_->close(); +//#endif + delete cache_; +} + +void CacheSim::attach_ram(RAM* ram) { + ram_ = ram; + dram_rsp_vec_.clear(); +} + +void CacheSim::reset() { +#ifndef NDEBUG + std::cout << timestamp << ": [sim] reset()" << std::endl; +#endif + + cache_->reset = 1; + this->step(); + cache_->reset = 0; + this->step(); + dram_rsp_vec_.clear(); + +} + +void CacheSim::step() { + cache_->clk = 0; + this->eval(); + + cache_->clk = 1; + this->eval(); + + //this->eval_reqs(); + //this->eval_rsps(); + this->eval_dram_bus(); +} + +void CacheSim::eval() { + cache_->eval(); +//#ifdef VCD_OUTPUT + trace_->dump(timestamp); +//#endif + ++timestamp; +} + +void CacheSim::run(){ +#ifndef NDEBUG + std::cout << timestamp << ": [sim] run()" << std::endl; +#endif + // reset the device + this->reset(); + this->step(); + + // execute program + while (!core_reqq_.empty()) { + + for(int i = 0; i < 10; ++i){ + if(i == 1){ + this->clear_req(); //invalidate reqs + } + this->step(); + } + + } +} + +void CacheSim::clear_req(){ + cache_->core_req_valid = 0; +} + +/* +void CacheSim::send_req(core_req_t *req){ + core_reqq_.push(req); +} + +bool CacheSim::get_core_req_ready(){ + return cache_->core_req_ready; +} + +bool CacheSim::get_core_rsp_ready(){ + return cache_->core_rsp_ready; +} +*/ + +void CacheSim::set_core_req(){ + cache_->core_req_valid = 0xf; + cache_->core_req_rw = 0xf; + cache_->core_req_byteen = 0xffff; + cache_->core_req_addr[0] = 0x00; + cache_->core_req_addr[1] = 0xab; + cache_->core_req_addr[2] = 0xcd; + cache_->core_req_addr[3] = 0xe1; + cache_->core_req_data[0] = 0xffffffff; + cache_->core_req_data[1] = 0x11111111; + cache_->core_req_data[2] = 0x22222222; + cache_->core_req_data[3] = 0x33333333; + cache_->core_req_tag = 0xff; +} + +void CacheSim::set_core_req2(){ + cache_->core_req_valid = 0xf; //b1000 + cache_->core_req_rw = 0x0; //b0000 + cache_->core_req_byteen = 0xffff; + cache_->core_req_addr[0] = 0x00; + cache_->core_req_addr[1] = 0xab; + cache_->core_req_addr[2] = 0xcd; + cache_->core_req_addr[3] = 0xe1; + cache_->core_req_data[0] = 0x1111111; + cache_->core_req_data[1] = 0x4444444; + cache_->core_req_data[2] = 0x5555555; + cache_->core_req_data[3] = 0x6666666; + cache_->core_req_tag = 0xff; +} + + +void CacheSim::get_core_rsp(){ + std::cout << std::hex << "core_rsp_valid: " << cache_->core_rsp_valid << std::endl; + std::cout << std::hex << "core_rsp_data: " << cache_->core_rsp_data << std::endl; + std::cout << std::hex << "core_rsp_tag: " << cache_->core_rsp_tag << std::endl; + + char check = cache_->core_req_valid; + std::cout << "core_req_valid: " << check << std::endl; + std::cout << std::hex << "core_req_data: " << cache_->core_req_data << std::endl; + std::cout << std::hex << "core_req_tag: " << cache_->core_req_tag << std::endl; +} + +void CacheSim::get_dram_req(){ + std::cout << std::hex << "dram_req_valid: " << cache_->dram_req_valid << std::endl; + std::cout << std::hex << "dram_req_rw: " << cache_->dram_req_rw << std::endl; + std::cout << std::hex << "dram_req_byteen: " << cache_->dram_req_byteen << std::endl; + std::cout << std::hex << "dram_req_addr: " << cache_->dram_req_addr << std::endl; + std::cout << std::hex << "dram_req_data: " << cache_->dram_req_data << std::endl; + std::cout << std::hex << "dram_req_tag: " << cache_->dram_req_tag << std::endl; +} + +void CacheSim::get_dram_rsp(){ + std::cout << std::hex << "dram_rsp_valid: " << cache_->dram_rsp_valid << std::endl; + std::cout << std::hex << "dram_rsp_data: " << cache_->dram_rsp_data << std::endl; + std::cout << std::hex << "dram_rsp_tag: " << cache_->dram_rsp_tag << std::endl; + std::cout << std::hex << "dram_rsp_ready: " << cache_->dram_rsp_ready << std::endl; +} + + + +void CacheSim::eval_reqs(){ + //check to see if cache is accepting reqs + /*if(!core_reqq_.empty() && cache_->core_req_ready){ + core_req_t *req = core_reqq_.front(); + cache_->core_req_valid = req->valid; + cache_->core_req_rw = req->rw; + cache_->core_req_byteen = req->byteen; + cache_->core_req_addr = req->addr; + cache_->core_req_data = req->data; + cache_->core_req_tag = req->tag; + }*/ +} + +void CacheSim::eval_rsps(){ + //check to see if a request has been responded to + //if core_rsp tag equal to the front queue tag pop it from the queue + //while the req tag == rsp tag +} + +void CacheSim::eval_dram_bus() { + if (ram_ == nullptr) { + cache_->dram_req_ready = 0; + return; + } + + // schedule DRAM responses + int dequeue_index = -1; + for (int i = 0; i < dram_rsp_vec_.size(); i++) { + if (dram_rsp_vec_[i].cycles_left > 0) { + dram_rsp_vec_[i].cycles_left -= 1; + } + if ((dequeue_index == -1) + && (dram_rsp_vec_[i].cycles_left == 0)) { + dequeue_index = i; + } + } + + // send DRAM response + if (dram_rsp_active_ + && cache_->dram_rsp_valid + && cache_->dram_rsp_ready) { + dram_rsp_active_ = false; + } + if (!dram_rsp_active_) { + if (dequeue_index != -1) { //time to respond to the request + cache_->dram_rsp_valid = 1; + + //copy data from the rsp queue to the cache module + memcpy((uint8_t*)cache_->dram_rsp_data, dram_rsp_vec_[dequeue_index].data, GLOBAL_BLOCK_SIZE); + + cache_->dram_rsp_tag = dram_rsp_vec_[dequeue_index].tag; + free(dram_rsp_vec_[dequeue_index].data); //take data out of the queue + dram_rsp_vec_.erase(dram_rsp_vec_.begin() + dequeue_index); + dram_rsp_active_ = true; + } else { + cache_->dram_rsp_valid = 0; + } + } + + // handle DRAM stalls + bool dram_stalled = false; +#ifdef ENABLE_DRAM_STALLS + if (0 == ((timestamp/2) % DRAM_STALLS_MODULO)) { + dram_stalled = true; + } else + if (dram_rsp_vec_.size() >= DRAM_RQ_SIZE) { + dram_stalled = true; + } +#endif + + // process DRAM requests + if (!dram_stalled) { + if (cache_->dram_req_valid) { + if (cache_->dram_req_rw) { //write = 1 + uint64_t byteen = cache_->dram_req_byteen; + unsigned base_addr = (cache_->dram_req_addr * GLOBAL_BLOCK_SIZE); + uint8_t* data = (uint8_t*)(cache_->dram_req_data); + for (int i = 0; i < GLOBAL_BLOCK_SIZE; i++) { + if ((byteen >> i) & 0x1) { + (*ram_)[base_addr + i] = data[i]; + } + } + } else { + dram_req_t dram_req; + dram_req.cycles_left = DRAM_LATENCY; + dram_req.data = (uint8_t*)malloc(GLOBAL_BLOCK_SIZE); + dram_req.tag = cache_->dram_req_tag; + ram_->read(cache_->dram_req_addr * GLOBAL_BLOCK_SIZE, GLOBAL_BLOCK_SIZE, dram_req.data); + dram_rsp_vec_.push_back(dram_req); + } + } + } + + cache_->dram_req_ready = ~dram_stalled; +} + diff --git a/hw/unit_tests/cache/cachesim.h b/hw/unit_tests/cache/cachesim.h new file mode 100644 index 00000000..97e1b896 --- /dev/null +++ b/hw/unit_tests/cache/cachesim.h @@ -0,0 +1,89 @@ +#pragma once + +#include "VVX_cache.h" +#include "VVX_cache__Syms.h" +#include "verilated.h" + +//#ifdef VCD_OUTPUT +#include +//#endif + +//#include +#include "ram.h" +#include +#include +#include + +#define ENABLE_DRAM_STALLS +#define DRAM_LATENCY 100 +#define DRAM_RQ_SIZE 16 +#define DRAM_STALLS_MODULO 16 +#define GLOBAL_BLOCK_SIZE 16 + +typedef struct { + int cycles_left; + uint8_t *data; + unsigned tag; +} dram_req_t; + +typedef struct { + bool valid = 1; + unsigned rw; + unsigned byteen; + unsigned int *addr[4]; + unsigned int *data[4]; + unsigned tag; + bool responded; +} core_req_t; + +class CacheSim { +public: + + CacheSim(); + virtual ~CacheSim(); + + bool busy(); + + void reset(); + void step(); + void wait(uint32_t cycles); + void attach_ram(RAM* ram); + + void run(); //run until all reqs are empty + void clear_req(); + void send_req(core_req_t *req); + + void set_core_req(); + void set_core_req2(); + + //display funcs + + void get_dram_req(); + void get_core_rsp(); + bool get_core_req_ready(); + bool get_core_rsp_ready(); + void get_dram_rsp(); + + +private: + + void eval(); + + void eval_reqs(); + void eval_rsps(); + void eval_dram_bus(); + + std::queue core_reqq_; + std::vector dram_rsp_vec_; + int dram_rsp_active_; + + uint32_t snp_req_active_; + uint32_t snp_req_size_; + uint32_t pending_snp_reqs_; + + VVX_cache *cache_; + RAM *ram_; +//#ifdef VCD_OUTPUT + VerilatedVcdC *trace_; +//#endif +}; diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache b/hw/unit_tests/cache/obj_dir/VVX_cache new file mode 100755 index 0000000000000000000000000000000000000000..0ef08584770a376b3bfed873fb3aa8fcdc193835 GIT binary patch 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HcmV?d00001 diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache.cpp index 179bbdb8..14c427b6 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache.cpp +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.cpp @@ -6,18 +6,18 @@ #include "VVX_cache__Syms.h" //========== -CData/*2:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[256]; -CData/*0:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[256]; -IData/*31:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; -CData/*2:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[256]; -CData/*0:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[256]; -IData/*31:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; -CData/*2:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[256]; -CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[256]; -IData/*31:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; -CData/*2:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[256]; -CData/*0:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[256]; -IData/*31:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; +CData/*1:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16]; +CData/*0:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16]; +IData/*31:0*/ VVX_cache::__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16]; +CData/*0:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16]; +IData/*31:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16]; +CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16]; +IData/*31:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; +CData/*1:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16]; +CData/*0:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16]; +IData/*31:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; CData/*1:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; CData/*0:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; IData/*31:0*/ VVX_cache::__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; @@ -30,18 +30,6 @@ IData/*31:0*/ VVX_cache::__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__b CData/*1:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; CData/*0:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; IData/*31:0*/ VVX_cache::__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; -CData/*1:0*/ VVX_cache::__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; -CData/*0:0*/ VVX_cache::__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; -IData/*31:0*/ VVX_cache::__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; -CData/*1:0*/ VVX_cache::__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; -CData/*0:0*/ VVX_cache::__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; -IData/*31:0*/ VVX_cache::__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; -CData/*1:0*/ VVX_cache::__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; -CData/*0:0*/ VVX_cache::__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; -IData/*31:0*/ VVX_cache::__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; -CData/*1:0*/ VVX_cache::__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; -CData/*0:0*/ VVX_cache::__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; -IData/*31:0*/ VVX_cache::__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; VL_CTOR_IMP(VVX_cache) { VVX_cache__Syms* __restrict vlSymsp = __VlSymsp = new VVX_cache__Syms(this, name()); @@ -140,72 +128,72 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__2(VVX_cache__Syms* __restrict vlSymsp // Body vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1cU & vlTOPp->core_req_addr[0U]))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + = (((~ ((IData)(1U) << (0xcU & vlTOPp->core_req_addr[0U]))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) | ((1U & (IData)(vlTOPp->core_req_valid)) - << (0x1cU & vlTOPp->core_req_addr[0U]))); + << (0xcU & vlTOPp->core_req_addr[0U]))); vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1fU & ((IData)(1U) - + (0x1cU & - (vlTOPp->core_req_addr[1U] - << 2U)))))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & ( + vlTOPp->core_req_addr[1U] + << 2U)))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) | ((1U & ((IData)(vlTOPp->core_req_valid) - >> 1U)) << (0x1fU & ((IData)(1U) - + (0x1cU - & (vlTOPp->core_req_addr[1U] - << 2U)))))); + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + (vlTOPp->core_req_addr[1U] + << 2U)))))); vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1fU & ((IData)(2U) - + (0x1cU & + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & ( + (vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & ((vlTOPp->core_req_addr[2U] << 4U) | (0xcU & (vlTOPp->core_req_addr[1U] - >> 0x1cU)))))))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) - | ((1U & ((IData)(vlTOPp->core_req_valid) - >> 2U)) << (0x1fU & ((IData)(2U) - + (0x1cU - & ((vlTOPp->core_req_addr[2U] - << 4U) - | (0xcU - & (vlTOPp->core_req_addr[1U] - >> 0x1cU)))))))); + >> 0x1cU)))))))); vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1fU & ((IData)(3U) - + (0x1cU & + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & ( + (vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & ((vlTOPp->core_req_addr[3U] << 6U) | (0x3cU & (vlTOPp->core_req_addr[2U] - >> 0x1aU)))))))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) - | ((1U & ((IData)(vlTOPp->core_req_valid) - >> 3U)) << (0x1fU & ((IData)(3U) - + (0x1cU - & ((vlTOPp->core_req_addr[3U] - << 6U) - | (0x3cU - & (vlTOPp->core_req_addr[2U] - >> 0x1aU)))))))); - vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xffU; + >> 0x1aU)))))))); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xfU; vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[1U] + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[1U] << 0x1eU) | ( vlTOPp->core_req_addr[0U] >> 2U))))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & vlTOPp->core_req_addr[1U]))) + = ((~ ((IData)(1U) << (3U & vlTOPp->core_req_addr[1U]))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[2U] + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[2U] << 2U) | (vlTOPp->core_req_addr[1U] >> 0x1eU))))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[3U] + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[3U] << 4U) | (vlTOPp->core_req_addr[2U] >> 0x1cU))))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); @@ -215,123 +203,99 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_settle__TOP__3\n"); ); VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Variables - WData/*191:0*/ __Vtemp268[6]; - WData/*255:0*/ __Vtemp269[8]; - WData/*191:0*/ __Vtemp281[6]; - WData/*255:0*/ __Vtemp282[8]; - WData/*191:0*/ __Vtemp294[6]; - WData/*255:0*/ __Vtemp295[8]; - WData/*191:0*/ __Vtemp307[6]; - WData/*255:0*/ __Vtemp308[8]; - WData/*191:0*/ __Vtemp320[6]; - WData/*255:0*/ __Vtemp321[8]; - WData/*191:0*/ __Vtemp333[6]; - WData/*255:0*/ __Vtemp334[8]; - WData/*191:0*/ __Vtemp346[6]; - WData/*255:0*/ __Vtemp347[8]; - WData/*191:0*/ __Vtemp359[6]; - WData/*255:0*/ __Vtemp360[8]; - WData/*127:0*/ __Vtemp361[4]; - WData/*287:0*/ __Vtemp368[9]; - WData/*287:0*/ __Vtemp369[9]; - WData/*319:0*/ __Vtemp370[10]; - WData/*127:0*/ __Vtemp373[4]; - WData/*287:0*/ __Vtemp380[9]; - WData/*287:0*/ __Vtemp381[9]; - WData/*319:0*/ __Vtemp382[10]; - WData/*127:0*/ __Vtemp385[4]; - WData/*287:0*/ __Vtemp392[9]; - WData/*287:0*/ __Vtemp393[9]; - WData/*319:0*/ __Vtemp394[10]; - WData/*127:0*/ __Vtemp397[4]; - WData/*287:0*/ __Vtemp404[9]; - WData/*287:0*/ __Vtemp405[9]; - WData/*319:0*/ __Vtemp406[10]; - WData/*127:0*/ __Vtemp409[4]; - WData/*287:0*/ __Vtemp416[9]; - WData/*287:0*/ __Vtemp417[9]; - WData/*319:0*/ __Vtemp418[10]; - WData/*127:0*/ __Vtemp421[4]; - WData/*287:0*/ __Vtemp428[9]; - WData/*287:0*/ __Vtemp429[9]; - WData/*319:0*/ __Vtemp430[10]; - WData/*127:0*/ __Vtemp433[4]; - WData/*287:0*/ __Vtemp440[9]; - WData/*287:0*/ __Vtemp441[9]; - WData/*319:0*/ __Vtemp442[10]; - WData/*127:0*/ __Vtemp445[4]; - WData/*287:0*/ __Vtemp452[9]; - WData/*287:0*/ __Vtemp453[9]; - WData/*319:0*/ __Vtemp454[10]; + WData/*191:0*/ __Vtemp146[6]; + WData/*255:0*/ __Vtemp147[8]; + WData/*191:0*/ __Vtemp160[6]; + WData/*255:0*/ __Vtemp161[8]; + WData/*191:0*/ __Vtemp174[6]; + WData/*255:0*/ __Vtemp175[8]; + WData/*191:0*/ __Vtemp188[6]; + WData/*255:0*/ __Vtemp189[8]; + WData/*127:0*/ __Vtemp191[4]; + WData/*287:0*/ __Vtemp198[9]; + WData/*287:0*/ __Vtemp199[9]; + WData/*319:0*/ __Vtemp201[10]; + WData/*127:0*/ __Vtemp204[4]; + WData/*287:0*/ __Vtemp211[9]; + WData/*287:0*/ __Vtemp212[9]; + WData/*319:0*/ __Vtemp214[10]; + WData/*127:0*/ __Vtemp217[4]; + WData/*287:0*/ __Vtemp224[9]; + WData/*287:0*/ __Vtemp225[9]; + WData/*319:0*/ __Vtemp227[10]; + WData/*127:0*/ __Vtemp230[4]; + WData/*287:0*/ __Vtemp237[9]; + WData/*287:0*/ __Vtemp238[9]; + WData/*319:0*/ __Vtemp240[10]; // Body vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1cU & vlTOPp->core_req_addr[0U]))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + = (((~ ((IData)(1U) << (0xcU & vlTOPp->core_req_addr[0U]))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) | ((1U & (IData)(vlTOPp->core_req_valid)) - << (0x1cU & vlTOPp->core_req_addr[0U]))); + << (0xcU & vlTOPp->core_req_addr[0U]))); vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1fU & ((IData)(1U) - + (0x1cU & - (vlTOPp->core_req_addr[1U] - << 2U)))))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) + = (((~ ((IData)(1U) << (0xfU & ((IData)(1U) + + (0xcU & ( + vlTOPp->core_req_addr[1U] + << 2U)))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) | ((1U & ((IData)(vlTOPp->core_req_valid) - >> 1U)) << (0x1fU & ((IData)(1U) - + (0x1cU - & (vlTOPp->core_req_addr[1U] - << 2U)))))); + >> 1U)) << (0xfU & ((IData)(1U) + + (0xcU & + (vlTOPp->core_req_addr[1U] + << 2U)))))); vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1fU & ((IData)(2U) - + (0x1cU & + = (((~ ((IData)(1U) << (0xfU & ((IData)(2U) + + (0xcU & ( + (vlTOPp->core_req_addr[2U] + << 4U) + | (0xcU + & (vlTOPp->core_req_addr[1U] + >> 0x1cU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 2U)) << (0xfU & ((IData)(2U) + + (0xcU & ((vlTOPp->core_req_addr[2U] << 4U) | (0xcU & (vlTOPp->core_req_addr[1U] - >> 0x1cU)))))))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) - | ((1U & ((IData)(vlTOPp->core_req_valid) - >> 2U)) << (0x1fU & ((IData)(2U) - + (0x1cU - & ((vlTOPp->core_req_addr[2U] - << 4U) - | (0xcU - & (vlTOPp->core_req_addr[1U] - >> 0x1cU)))))))); + >> 0x1cU)))))))); vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - = (((~ ((IData)(1U) << (0x1fU & ((IData)(3U) - + (0x1cU & + = (((~ ((IData)(1U) << (0xfU & ((IData)(3U) + + (0xcU & ( + (vlTOPp->core_req_addr[3U] + << 6U) + | (0x3cU + & (vlTOPp->core_req_addr[2U] + >> 0x1aU)))))))) + & (IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid)) + | ((1U & ((IData)(vlTOPp->core_req_valid) + >> 3U)) << (0xfU & ((IData)(3U) + + (0xcU & ((vlTOPp->core_req_addr[3U] << 6U) | (0x3cU & (vlTOPp->core_req_addr[2U] - >> 0x1aU)))))))) - & vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) - | ((1U & ((IData)(vlTOPp->core_req_valid) - >> 3U)) << (0x1fU & ((IData)(3U) - + (0x1cU - & ((vlTOPp->core_req_addr[3U] - << 6U) - | (0x3cU - & (vlTOPp->core_req_addr[2U] - >> 0x1aU)))))))); - vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xffU; + >> 0x1aU)))))))); + vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = 0xfU; vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[1U] + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[1U] << 0x1eU) | ( vlTOPp->core_req_addr[0U] >> 2U))))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & vlTOPp->core_req_addr[1U]))) + = ((~ ((IData)(1U) << (3U & vlTOPp->core_req_addr[1U]))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[2U] + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[2U] << 2U) | (vlTOPp->core_req_addr[1U] >> 0x1eU))))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel - = ((~ ((IData)(1U) << (7U & ((vlTOPp->core_req_addr[3U] + = ((~ ((IData)(1U) << (3U & ((vlTOPp->core_req_addr[3U] << 4U) | (vlTOPp->core_req_addr[2U] >> 0x1cU))))) & (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel)); @@ -344,7 +308,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] = vlTOPp->dram_rsp_data[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] @@ -354,7 +318,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] = vlTOPp->dram_rsp_data[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] @@ -364,7 +328,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] = vlTOPp->dram_rsp_data[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] @@ -374,253 +338,113 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (0U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (0U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (1U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (1U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (2U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (2U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (3U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (3U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (4U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (4U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (5U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (5U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (6U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (6U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (7U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (7U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use + = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) + | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) + - (IData)(1U)))) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 1U))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 2U))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 3U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 5U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 7U))); vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 1U))); vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 2U))); vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 3U))); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 5U))); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 7U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] @@ -637,22 +461,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r @@ -669,22 +477,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -845,166 +637,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] @@ -1037,38 +669,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] @@ -1085,22 +685,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -1181,86 +765,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0U] = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] @@ -1277,22 +781,21 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_req_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0U] = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) @@ -1333,77 +836,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 1U))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 3U))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 5U))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 7U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -1452,54 +884,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index @@ -1540,46 +924,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i [vlTOPp->__Vtableidx8]; - vlTOPp->__Vtableidx9 = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx9]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx9]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx9]; - vlTOPp->__Vtableidx10 = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx10]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx10]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx10]; - vlTOPp->__Vtableidx11 = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx11]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx11]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx11]; - vlTOPp->__Vtableidx12 = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx12]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx12]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx12]; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -1596,46 +940,18 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) @@ -1652,70 +968,30 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] @@ -1724,38 +1000,18 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -1868,187 +1124,43 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) << 1U))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) << 2U))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) << 3U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 5U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 7U))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill = (0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -2074,8 +1186,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -2101,8 +1213,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -2128,8 +1240,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -2153,126 +1265,14 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U)))) >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use - = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) - | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) - - (IData)(1U)))) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) - | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 9U) | (0x1f8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (0x1fcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] >> 0x17U))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) - | (0xf0000000U & (0x10000000U | (0x80000000U + | (0xf0000000U & (0x10000000U | (0xc0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] << 5U))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] @@ -2283,7 +1283,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x1bU))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) - | (0xff000000U & (0x2000000U | (0xf8000000U + | (0xff000000U & (0x2000000U | (0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] << 1U))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] @@ -2294,60 +1294,15 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x1fU))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) - | (0xfff00000U & (0x300000U | (0xff800000U + | (0xfff00000U & (0x300000U | (0xffc00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] << 0x1dU) - | (0x1f800000U + | (0x1fc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] >> 3U))))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) - | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 3U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) - | (0xffff0000U & (0x40000U | (0xfff80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0x19U) - | (0x1f80000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 7U))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] - = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) - | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 7U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] - = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) - | (0xfffff000U & (0x5000U | (0xffff8000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0x15U) - | (0x1f8000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0xbU))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) - | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0xbU))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) - | (0xffffff00U & (0x600U | (0xfffff800U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0x11U) - | (0x1f800U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0xfU))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] - = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) - | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0xfU))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] - = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) - | (0xfffffff0U & (0x70U | (0xffffff80U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xdU) | - (0x1f80U & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x13U))))))); + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 3U)); vlTOPp->__Vtableidx3 = vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index @@ -2390,38 +1345,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x14U))) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -2470,54 +1393,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 1U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -2538,29 +1413,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)); vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) - >> (7U & vlTOPp->snp_req_addr))); + >> (3U & vlTOPp->snp_req_addr))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))))) @@ -2577,28 +1435,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))))) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->core_req_ready = (0xffU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) - | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); + vlTOPp->core_req_ready = (0xfU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) + | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xfffcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + ((0xfcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] @@ -2618,7 +1460,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xfff3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + ((0xf3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 8U))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] @@ -2650,7 +1492,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xffcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + ((0xcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 6U))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] @@ -2682,7 +1524,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xff3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + ((0x3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 4U))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] @@ -2710,144 +1552,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x20U)) << 0x1eU))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) - | (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) >> 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xfcffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0x300U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) - | (0xffffff00U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 8U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - = ((0xfffc0000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) - | ((0xffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0x18U)) | (0xffffff00U & - ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 8U)))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xf3ffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0xc00U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - = ((0x3ffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) - | (0xfffc0000U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 0x12U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) - | ((0x3ffffU & ((IData)((VL_ULL(0x3ffffffffff) + = (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 0x12U)))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xcfffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0x3000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - << 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) - | (0xf0000000U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 0x1cU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - = ((0xfffffffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 4U)) | (0xf0000000U & - ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 0x1cU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - = ((0xffffffc0U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) - | (0xfffffffU & ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) >> 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0x3fffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0xc000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - = ((0x3fU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) - | (0xffffffc0U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - = ((0x3fU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0x1aU)) | (0xffffffc0U & ((IData)( - ((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 6U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) @@ -2956,114 +1666,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (0x1fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] @@ -3077,28 +1679,17 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[5U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[6U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]); + = (0xffffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U])); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid - = (0xffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) - & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) - : (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] - & VL_NEGATE_I((IData)((1U & - (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); + = (0xfU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) + & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + : ((vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); @@ -3111,18 +1702,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U]) { @@ -3143,34 +1722,15 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff0000) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | (IData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -3189,19 +1749,19 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) - | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 7U) | (0x78U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x19U))))); + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 6U) | (0x3cU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1aU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -3210,12 +1770,13 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 4U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffff0000ffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x10U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -3234,25 +1795,25 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) - | (0xf0000000U & (0x10000000U | (0x80000000U + | (0xf0000000U & (0x10000000U | (0xc0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 3U))))); + << 2U))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) - | (0xffffffU & ((0xffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 3U)) | - (7U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1dU))))); + | (0xffffffU & ((0xffffffcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 2U)) | + (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1eU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -3261,11 +1822,13 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 8U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffff0000ffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x20U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -3284,40 +1847,40 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) - | (0xff000000U & (0x2000000U | (0xf8000000U + | (0xff000000U & (0x2000000U | (0xfc000000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x1fU) - | (0x78000000U + << 0x1eU) + | (0x3c000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 1U))))))); + >> 2U))))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 1U))); + >> 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] << 0x14U))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) - | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0xcU))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0xcU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x30U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -3336,1666 +1899,709 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) - | (0xfff00000U & (0x300000U | (0xff800000U + | (0xfff00000U & (0x300000U | (0xffc00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x1bU) - | (0x7800000U + << 0x1aU) + | (0x3c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 5U))))))); + >> 6U))))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) - | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))); + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) - | (0xffff0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 0x10U))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] - = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) - | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x10U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x10U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x11U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x12U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x13U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) - | (0xffff0000U & (0x40000U | (0xfff80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x17U) - | (0x780000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 9U))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] - = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) - | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 9U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] - = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) - | (0xfffff000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 0xcU))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) - | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x14U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x15U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x16U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x17U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] - = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) - | (0xfffff000U & (0x5000U | (0xffff8000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x13U) - | (0x78000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0xdU))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) - | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0xdU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) - | (0xffffff00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 8U))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] - = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) - | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x18U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x19U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1aU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1bU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) - | (0xffffff00U & (0x600U | (0xfffff800U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0xfU) - | (0x7800U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x11U))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] - = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) - | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x11U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] - = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) - | (0xfffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1cU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1dU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1eU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1fU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] - = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) - | (0xfffffff0U & (0x70U | (0xffffff80U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0xbU) | - (0x780U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x15U))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) @@ -5012,450 +2618,246 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); 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- vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -5472,22 +2874,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); @@ -5500,44 +2886,20 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid - = (0xfU & (vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x10U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x14U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x18U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x1cU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->core_rsp_tag = ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + vlTOPp->core_rsp_tag = ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (VL_ULL(0x3ffffffffff) & (((0U == (0x1fU & ((IData)(0x2aU) @@ -5547,7 +2909,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(2U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -5559,7 +2921,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -5573,7 +2935,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | ((QData)((IData)( vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))])) @@ -5585,24 +2947,23 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) - + (0xfU & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] << ((IData)(0x20U) - (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] >> + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)))) { @@ -5615,8 +2976,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] >> 0xaU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -5624,7 +2985,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -5635,10 +2996,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -5653,8 +3014,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] >> 0x14U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -5662,7 +3023,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -5673,10 +3034,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -5691,8 +3052,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] >> 0x1eU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -5700,7 +3061,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -5711,10 +3072,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -5724,158 +3085,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 6U)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - >> 8U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 8U)))); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - >> 0x12U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 0xaU)))); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - >> 0x1cU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 0xcU)))); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - >> 6U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 0xeU)))); - } vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; @@ -5883,24 +3092,23 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) - + (0xfU & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] << ((IData)(0x20U) - (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] >> + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)))) { @@ -5913,8 +3121,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] >> 0xaU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -5922,7 +3130,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -5933,10 +3141,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -5950,8 +3158,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] >> 0x14U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -5959,7 +3167,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -5970,10 +3178,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -5987,8 +3195,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] >> 0x1eU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -5996,7 +3204,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -6007,10 +3215,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -6019,167 +3227,19 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - >> 8U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U]); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - >> 0x12U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U]); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - >> 0x1cU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 7U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U]); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - >> 6U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 9U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U]); - } vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) - + (0xfU + + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -6188,23 +3248,23 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) << 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] >> 0xaU))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (( (0U == @@ -6216,7 +3276,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -6227,7 +3287,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))] @@ -6237,16 +3297,16 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)) << 1U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) << 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] >> 0x14U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (( (0U == @@ -6258,7 +3318,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -6269,7 +3329,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))] @@ -6279,16 +3339,16 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)) << 2U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) << 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] >> 0x1eU))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (( (0U == @@ -6300,7 +3360,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -6311,7 +3371,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))] @@ -6320,174 +3380,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)) << 3U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffff0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 4U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - >> 8U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 4U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xffffffe0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 5U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - << 0xeU) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - >> 0x12U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 5U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xffffffc0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 6U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - << 4U) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - >> 0x1cU))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 6U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xffffff80U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 7U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - << 0x1aU) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - >> 6U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 7U)))); vlTOPp->__Vtableidx1 = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index @@ -6530,100 +3422,36 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) << 1U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) << 1U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) << 2U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) << 2U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) << 3U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) << 3U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) - << 7U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) - << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 @@ -6690,8 +3518,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -6702,12 +3530,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 @@ -6774,8 +3602,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -6786,12 +3614,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 @@ -6858,8 +3686,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -6870,12 +3698,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 @@ -6942,8 +3770,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -6954,348 +3782,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) @@ -7314,35 +3806,23 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall @@ -7359,19 +3839,19 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall @@ -7388,19 +3868,19 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall @@ -7417,19 +3897,19 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall @@ -7442,122 +3922,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); @@ -7570,18 +3934,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) @@ -7782,206 +4134,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (0x3ffU & (vlTOPp->core_req_addr[3U] >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U]; vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U]; vlTOPp->core_rsp_data[2U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U]; @@ -8028,38 +4180,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); vlTOPp->__Vtableidx4 = vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid; vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank = vlTOPp->__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank @@ -8086,8 +4206,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 @@ -8095,8 +4215,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 @@ -8104,8 +4224,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 @@ -8113,44 +4233,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) @@ -8174,7 +4258,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -8193,11 +4277,11 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) @@ -8226,7 +4310,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -8249,11 +4333,11 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) @@ -8282,7 +4366,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -8305,11 +4389,11 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) @@ -8338,7 +4422,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -8361,241 +4445,17 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - << 4U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 4U) | (0x3f0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 4U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall))) - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - << 5U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 5U) | (0x7e0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 5U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall))) - << 5U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - << 6U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 6U) | (0xfc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 6U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall))) - << 6U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - << 7U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 7U) | (0x1f80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 7U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall))) - << 7U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) @@ -8612,28 +4472,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 4U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 5U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 6U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 7U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); vlTOPp->snp_rsp_valid = vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = 0U; vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))); - vlTOPp->snp_rsp_tag = ((0xdfU >= (0xffU & ((IData)(0x1cU) + vlTOPp->snp_rsp_tag = ((0x6fU >= (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) ? (0xfffffffU & (((0U == (0x1fU @@ -8643,7 +4487,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) >> 5U)))] @@ -8654,7 +4498,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) >> 5U))] @@ -8664,36 +4508,20 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) : 0U); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) << 1U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) << 2U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) << 3U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (4U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (5U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (6U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (7U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 7U)); vlTOPp->dram_req_rw = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; vlTOPp->dram_req_valid = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); @@ -8706,33 +4534,12 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))); vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) - ? (0xffffU & (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 4U))) - ? 0U - : ( - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ - ((IData)(1U) - + - (3U - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - >> 1U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 4U))))) - | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ - (3U - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - >> 1U))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 4U))))) + ? (0xffffU & (IData)( + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + >> + (0x3fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) : 0xffffU); vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) ? (((0U == (0x1fU @@ -8740,7 +4547,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(1U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -8749,8 +4556,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ - (0x1cU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 2U))] + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 7U)))) @@ -8761,7 +4568,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(2U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -8771,7 +4578,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(1U) - + (0x1cU & + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] >> (0x1fU & @@ -8784,7 +4591,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(3U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -8794,7 +4601,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(2U) - + (0x1cU & + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] >> (0x1fU & @@ -8807,7 +4614,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(4U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -8817,7 +4624,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(3U) - + (0x1cU & + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] >> (0x1fU & @@ -8825,9 +4632,9 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U)))) : 0U); vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) - ? ((0xdfU + ? ((0x6fU >= - (0xffU + (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) ? ( @@ -8841,7 +4648,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) >> 5U)))] @@ -8852,7 +4659,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) >> 5U))] @@ -8863,9 +4670,9 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U) : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req) ? ( - (0xdfU + (0x6fU >= - (0xffU + (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) ? @@ -8879,7 +4686,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U)))] @@ -8890,7 +4697,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U))] @@ -8901,44 +4708,24 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U) : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | ((IData)(vlTOPp->dram_req_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | (((IData)(vlTOPp->dram_req_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) << 1U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | (((IData)(vlTOPp->dram_req_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) << 2U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | (((IData)(vlTOPp->dram_req_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) << 3U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (4U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (5U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (6U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (7U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 @@ -9007,74 +4794,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -9162,6 +4881,19 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] + = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] + = ((0xffff0000U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid) + << 0x10U)) | vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing + = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -9191,142 +4923,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing - = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)); @@ -9342,30 +4938,15 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 7U)); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) - & (~ ((~ (IData)((0U != (0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + & (~ ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->dram_req_tag = vlTOPp->dram_req_addr; @@ -9384,22 +4965,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 @@ -9480,86 +5045,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); @@ -9576,7 +5061,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp268[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp146[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -9634,7 +5119,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp268[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp146[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -9749,72 +5234,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp269[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp147[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -9822,41 +5305,41 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -9871,7 +5354,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -9912,73 +5395,71 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp268[5U]); - __Vtemp269[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp146[5U]); + __Vtemp147[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -9986,42 +5467,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -10035,7 +5516,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -10078,9 +5559,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -10091,8 +5570,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -10106,7 +5585,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -10118,31 +5597,31 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -10150,35 +5629,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -10199,7 +5678,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -10241,72 +5720,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp269[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp147[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -10314,42 +5791,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -10363,7 +5840,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -10422,13 +5899,14 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp268[4U]; + = __Vtemp146[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp269[5U]; + = __Vtemp147[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp269[6U]; + = __Vtemp147[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp269[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp147[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -10453,7 +5931,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp281[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp160[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -10511,7 +5989,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp281[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp160[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -10626,72 +6104,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp282[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp161[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -10699,41 +6175,41 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -10748,7 +6224,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -10789,73 +6265,71 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp281[5U]); - __Vtemp282[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp160[5U]); + __Vtemp161[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -10863,42 +6337,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -10912,7 +6386,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -10955,9 +6429,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -10968,8 +6440,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -10983,7 +6455,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -10995,31 +6467,31 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -11027,35 +6499,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -11076,7 +6548,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -11118,72 +6590,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp282[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp161[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -11191,42 +6661,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -11240,7 +6710,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -11299,13 +6769,14 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp281[4U]; + = __Vtemp160[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp282[5U]; + = __Vtemp161[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp282[6U]; + = __Vtemp161[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp282[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp161[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -11330,7 +6801,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp294[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp174[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -11388,7 +6859,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp294[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp174[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -11503,72 +6974,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp295[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp175[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -11576,41 +7045,41 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -11625,7 +7094,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -11666,73 +7135,71 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp294[5U]); - __Vtemp295[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp174[5U]); + __Vtemp175[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -11740,42 +7207,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -11789,7 +7256,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -11832,9 +7299,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -11845,8 +7310,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -11860,7 +7325,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -11872,31 +7337,31 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -11904,35 +7369,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -11953,7 +7418,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -11995,72 +7460,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp295[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp175[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -12068,42 +7531,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -12117,7 +7580,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -12176,13 +7639,14 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp294[4U]; + = __Vtemp174[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp295[5U]; + = __Vtemp175[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp295[6U]; + = __Vtemp175[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp295[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp175[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -12207,7 +7671,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp307[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp188[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -12265,7 +7729,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp307[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp188[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -12380,72 +7844,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp308[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp189[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -12453,41 +7915,41 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -12502,7 +7964,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -12543,73 +8005,71 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp307[5U]); - __Vtemp308[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp188[5U]); + __Vtemp189[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -12617,42 +8077,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -12666,7 +8126,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -12709,9 +8169,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -12722,8 +8180,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -12737,7 +8195,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -12749,31 +8207,31 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -12781,35 +8239,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -12830,7 +8288,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -12872,72 +8330,70 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp308[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp189[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -12945,42 +8401,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -12994,7 +8450,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -13053,13 +8509,14 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp307[4U]; + = __Vtemp188[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp308[5U]; + = __Vtemp189[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp308[6U]; + = __Vtemp189[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp308[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp189[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -13068,3613 +8525,61 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head - = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp320[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ( - (VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp320[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - >> 0x1fU)) | (0xfffffffeU - & ((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0)))) - >> 0x20U)) - << 1U))); - __Vtemp321[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - << 0x12U)) | - __Vtemp320[5U]); - __Vtemp321[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp321[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 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((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 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- (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp334[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 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((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 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- ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp347[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 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((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - >> 0x1fU)) | (0xfffffffeU - & ((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - 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[vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0)))) - >> 0x20U)) - << 1U))); - __Vtemp360[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - 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| (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - 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>> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - << 0x12U)) | - __Vtemp359[5U]); - __Vtemp360[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - 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& (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - 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<< 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp360[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp359[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp360[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp360[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp360[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) - | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - __Vtemp361[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp191[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp361[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp191[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp361[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp191[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp361[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp191[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp368[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp198[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -16687,7 +8592,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp361[ + (__Vtemp191[ ((IData)(1U) + (3U @@ -16700,7 +8605,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp361[ + | (__Vtemp191[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -16709,8 +8614,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp368[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp198[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -16723,7 +8628,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp361[ + (__Vtemp191[ ((IData)(1U) + (3U @@ -16736,7 +8641,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp361[ + | (__Vtemp191[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -16745,7 +8650,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 @@ -16760,7 +8665,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp361[ + (__Vtemp191[ ((IData)(1U) + (3U @@ -16773,7 +8678,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp361[ + | (__Vtemp191[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -16783,10 +8688,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp369[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp199[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -16799,7 +8704,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp361[ + (__Vtemp191[ ((IData)(1U) + (3U @@ -16812,7 +8717,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp361[ + | (__Vtemp191[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -16822,39 +8727,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp370[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp201[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -16863,7 +8764,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -16874,8 +8775,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -16890,42 +8791,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp368[6U]; + = __Vtemp198[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp368[7U]; + = __Vtemp198[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp369[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp199[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp370[9U])); + [0U] << 0x1aU)) | __Vtemp201[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 @@ -16933,17 +8834,17 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp373[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp204[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp373[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp204[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp373[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp204[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp373[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp204[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp380[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp211[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -16956,7 +8857,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp373[ + (__Vtemp204[ ((IData)(1U) + (3U @@ -16969,7 +8870,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp373[ + | (__Vtemp204[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -16978,8 +8879,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp380[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp211[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -16992,7 +8893,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp373[ + (__Vtemp204[ ((IData)(1U) + (3U @@ -17005,7 +8906,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp373[ + | (__Vtemp204[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17014,7 +8915,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 @@ -17029,7 +8930,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp373[ + (__Vtemp204[ ((IData)(1U) + (3U @@ -17042,7 +8943,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp373[ + | (__Vtemp204[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17052,10 +8953,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp381[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp212[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -17068,7 +8969,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp373[ + (__Vtemp204[ ((IData)(1U) + (3U @@ -17081,7 +8982,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp373[ + | (__Vtemp204[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17091,39 +8992,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp382[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp214[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -17132,7 +9029,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -17143,8 +9040,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -17159,42 +9056,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp380[6U]; + = __Vtemp211[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp380[7U]; + = __Vtemp211[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp381[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp212[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp382[9U])); + [0U] << 0x1aU)) | __Vtemp214[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 @@ -17202,17 +9099,17 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp385[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp217[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp385[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp217[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp385[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp217[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp385[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp217[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp392[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp224[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -17225,7 +9122,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp385[ + (__Vtemp217[ ((IData)(1U) + (3U @@ -17238,7 +9135,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp385[ + | (__Vtemp217[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17247,8 +9144,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp392[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp224[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -17261,7 +9158,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp385[ + (__Vtemp217[ ((IData)(1U) + (3U @@ -17274,7 +9171,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp385[ + | (__Vtemp217[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17283,7 +9180,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 @@ -17298,7 +9195,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp385[ + (__Vtemp217[ ((IData)(1U) + (3U @@ -17311,7 +9208,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp385[ + | (__Vtemp217[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17321,10 +9218,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp393[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp225[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -17337,7 +9234,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp385[ + (__Vtemp217[ ((IData)(1U) + (3U @@ -17350,7 +9247,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp385[ + | (__Vtemp217[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17360,39 +9257,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp394[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp227[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -17401,7 +9294,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -17412,8 +9305,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -17428,42 +9321,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp392[6U]; + = __Vtemp224[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp392[7U]; + = __Vtemp224[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp393[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp225[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp394[9U])); + [0U] << 0x1aU)) | __Vtemp227[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 @@ -17471,17 +9364,17 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp397[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp230[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp397[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp230[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp397[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp230[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp397[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp230[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp404[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp237[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -17494,7 +9387,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp397[ + (__Vtemp230[ ((IData)(1U) + (3U @@ -17507,7 +9400,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp397[ + | (__Vtemp230[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17516,8 +9409,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp404[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp237[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -17530,7 +9423,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp397[ + (__Vtemp230[ ((IData)(1U) + (3U @@ -17543,7 +9436,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp397[ + | (__Vtemp230[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17552,7 +9445,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 @@ -17567,7 +9460,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp397[ + (__Vtemp230[ ((IData)(1U) + (3U @@ -17580,7 +9473,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp397[ + | (__Vtemp230[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17590,10 +9483,10 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp405[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp238[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -17606,7 +9499,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U))) ? 0U : - (__Vtemp397[ + (__Vtemp230[ ((IData)(1U) + (3U @@ -17619,7 +9512,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp397[ + | (__Vtemp230[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -17629,39 +9522,35 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp406[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp240[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -17670,7 +9559,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -17681,8 +9570,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -17697,42 +9586,42 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp404[6U]; + = __Vtemp237[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp404[7U]; + = __Vtemp237[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp405[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp238[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp406[9U])); + [0U] << 0x1aU)) | __Vtemp240[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 @@ -17740,1082 +9629,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp409[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp409[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp409[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp409[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - __Vtemp416[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp409[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp409[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U)))))))) - << 0x18U))); - __Vtemp416[7U] = ((0xffffffU & ((IData)((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp409[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp409[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U)))))))) - >> 8U)) | (0xff000000U - & ((IData)( - ((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp409[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp409[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - << 0x18U))); - __Vtemp417[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp409[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp409[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - >> 8U))); - __Vtemp418[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - << 0x18U)) - | ((0x3800000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U] - << 0x17U)) - | ((0x3c00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U] - << 0x16U)) - | ((0x3e00000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)) - << 0x15U)) - | ((0x3f00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] - << 0x14U)) - | ((0x3f80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - << 0x13U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U] - >> 6U))))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] - = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] - = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] << 0x11U)) | (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U] - << 3U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e) - << 2U)) - | ((0xfffffffeU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e) - << 1U)) - | (0x1ffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] - >> 0xfU)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - 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[0U])) - << 0x19U)) - | ((0x3000000U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - << 0x18U)) - | ((0x3800000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U] - << 0x17U)) - | ((0x3c00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U] - << 0x16U)) - | ((0x3e00000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)) - << 0x15U)) - | ((0x3f00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] - << 0x14U)) - | ((0x3f80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - << 0x13U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - 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<< 2U)) - | ((0xfffffffeU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e) - << 1U)) - | (0x1ffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] - >> 0xfU)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] - 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[0U] - << 5U))))) - | (__Vtemp433[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - << 0x18U))); - __Vtemp441[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp433[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp433[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - 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[0U] - << 0x16U)) - | ((0x3e00000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)) - << 0x15U)) - | ((0x3f00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] - << 0x14U)) - | ((0x3f80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - << 0x13U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U] - >> 6U))))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] - = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] - = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - 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[0U])) << 0x1bU)) | - ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp442[9U])); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write - = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e))) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp445[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp445[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - 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& vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U)))))))) - << 0x18U))); - __Vtemp452[7U] = ((0xffffffU & ((IData)((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp445[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp445[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U)))))))) - >> 8U)) | (0xff000000U - & ((IData)( - ((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp445[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp445[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - << 0x18U))); - __Vtemp453[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp445[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp445[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - >> 8U))); - __Vtemp454[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - << 0x18U)) - | ((0x3800000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U] - << 0x17U)) - | ((0x3c00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U] - << 0x16U)) - | ((0x3e00000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)) - << 0x15U)) - | ((0x3f00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] - << 0x14U)) - | ((0x3f80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - << 0x13U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U] - >> 6U))))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] - = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] - = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] << 0x11U)) | (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U] - << 3U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e) - << 2U)) - | ((0xfffffffeU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e) - << 1U)) - | (0x1ffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] - >> 0xfU)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp452[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp452[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp453[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] - = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) << 0x1bU)) | - ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp454[9U])); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write - = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e))) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) @@ -18956,146 +9769,6 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { [0U] >> 2U))) : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) @@ -19112,41 +9785,18 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we))); } VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSymsp) { VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_sequent__TOP__4\n"); ); VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Variables - CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; - CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - CData/*0:0*/ __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0; - CData/*0:0*/ __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0; - CData/*3:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; - CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - CData/*2:0*/ __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0; + CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0; CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; CData/*4:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; @@ -19163,96 +9813,96 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0; - CData/*3:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*2:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - CData/*2:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0; + CData/*1:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0; - CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + SData/*15:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1; + CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0; - CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1; - CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2; - CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3; - CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; CData/*0:0*/ __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4; - CData/*3:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; + CData/*5:0*/ __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; CData/*6:0*/ __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; CData/*7:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5; 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WData/*313:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[10]; - IData/*20:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + IData/*19:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; WData/*84:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[3]; WData/*75:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[3]; - WData/*198:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[7]; - WData/*152:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[5]; + WData/*199:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[7]; 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+ QData/*54:0*/ __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; // Body - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr @@ -20191,49 +10320,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; - __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r @@ -20266,62 +10352,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r @@ -20354,22 +10388,18 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r @@ -20378,110 +10408,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r @@ -20514,22 +10440,46 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r @@ -20538,30 +10488,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r @@ -20570,6 +10496,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r @@ -20581,14 +10515,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr @@ -20597,14 +10523,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table @@ -20613,38 +10531,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel @@ -20653,38 +10539,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r @@ -20717,22 +10571,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r @@ -20741,22 +10583,22 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; @@ -20765,70 +10607,54 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0U; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0U; + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x40U; + } else { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; + } + } __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0U; @@ -20893,134 +10719,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0U; __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0U; - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 0x10U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = 4U; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = 4U; - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } - } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = 0U; } else { @@ -21060,152 +10758,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid = 0U; } } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - = (VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U])))); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen - = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - = (VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U])))); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen - = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - = (VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U])))); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen - = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - = (VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U])))); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[3U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen - = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U)); + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = 0U; + } else { + if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = 1U; + } else { + if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = 0U; + } } } if ((1U & (~ (IData)(vlTOPp->reset)))) { @@ -21356,112 +10919,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 2U)); } } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw - = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] - = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw - = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] - = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw - = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] - = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw - = (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U)); - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[1U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[2U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[3U] - = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr + = (0xfffffffU & ((IData)(0x10U) + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r)); } } if ((1U & (~ (IData)(vlTOPp->reset)))) { @@ -21577,9 +11040,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[1U] = 0U; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] = 0U; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] = 0U; } else { if (((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))) { @@ -21591,270 +11051,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[2U]; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[5U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[6U]; } } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; 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- vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; 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- vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_ULL(0); - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.snp_req_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; - } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_ULL(0); @@ -22111,668 +11309,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))]; } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) { - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr - = (0xfffffffU & ((IData)(0x10U) + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; 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- __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; 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- __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.core_req_arb.reqq_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; - } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; @@ -22827,14 +11363,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; } __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); } __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; @@ -22874,11 +11410,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); } __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) @@ -22990,14 +11526,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; } __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); } __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; @@ -23037,11 +11573,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); } __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) @@ -23153,14 +11689,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; } __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); } __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; @@ -23200,11 +11736,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); } __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) @@ -23316,14 +11852,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)))) { __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))) { vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; } __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r))); } __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U]; @@ -23363,11 +11899,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) - - (IData)(1U))); + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r) + - (IData)(1U))); } __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); } vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing) @@ -23425,6 +11961,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][9U]; } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = 0U; + } else { + if ((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use))) { + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original + = vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid; + } + } if (vlTOPp->reset) { vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = 0U; } else { @@ -23436,72 +11980,348 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } } if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; } if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; } if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; } if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty))))))); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)); + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); + } + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; } if (vlTOPp->reset) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = 0U; @@ -23571,566 +12391,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } } } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; - } else { - if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) - - (IData)(1U))); - } - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((0xfU == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.dfp_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (0xfU & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; @@ -24564,772 +12824,68 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; } if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[3].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[2].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[1].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[0].bank.cwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = 0U; - } else { - if ((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use))) { - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original - = vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid; } } if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { - if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) - - (IData)(1U))); - } + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); } - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); } } if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { - if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) - - (IData)(1U))); - } + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); + } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); } - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); } } if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = 0U; } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { - if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) - - (IData)(1U))); - } + if ((1U & (~ ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head))))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); } - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)))) { - if (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr) - - (IData)(1U))); - } + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size) + - (IData)(1U))); } } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - } } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = 0U; @@ -25404,100 +12960,101 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } } if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) { + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; + __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; + __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; + if ((3U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))); + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); } - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = (0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))); - } - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))) - & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) { + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)))) { + if ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { + if (Verilated::assertOn()) { + if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { + VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2: 'assert' failed.\n", + 64,VL_TIME_Q(), + vlSymsp->name()); + VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); + } + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; + } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r + = (7U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r) + - (IData)(1U))); + } + __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) + | ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r)) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] + = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data + [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) + ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) + : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = 0U; @@ -25595,239 +13152,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(__Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)); } } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U]; - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[7U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U]; - __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((7U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U]; - if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) { - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r - = (0xfU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (7U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U] - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][7U]; - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; - } - } if (vlTOPp->reset) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[0U] = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value[1U] = 0U; @@ -25920,632 +13244,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U]; } } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vtemp514[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 0x1dU) - | (0x1fe00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 3U)))) - | (IData)(((((QData)((IData)( - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) - << 0x33U) - | ((VL_ULL(0x7fffffffffe00) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x22U) - | (VL_ULL(0xfffffffffffffe00) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - << 2U)))) - | (QData)((IData)( - ((0x100U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xf0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xcU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xaU) - | (0x3fcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x16U)))) - | (3U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U))))))))) - >> 0x20U))); - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] - = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) - << 0x33U) | ((VL_ULL(0x7fffffffffe00) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x22U) - | (VL_ULL(0xfffffffffffffe00) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - << 2U)))) - | (QData)((IData)( - ((0x100U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xf0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xcU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xaU) - | (0x3fcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x16U)))) - | (3U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U)))))))))); - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] - = __Vtemp514[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] - = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 3U)); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vtemp515[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 0x1dU) - | (0x1fe00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 3U)))) - | (IData)(((((QData)((IData)( - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) - << 0x33U) - | ((VL_ULL(0x7fffffffffe00) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x22U) - | (VL_ULL(0xfffffffffffffe00) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - << 2U)))) - | (QData)((IData)( - ((0x100U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xf0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xcU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xaU) - | (0x3fcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x16U)))) - | (3U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U))))))))) - >> 0x20U))); - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] - = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) - << 0x33U) | ((VL_ULL(0x7fffffffffe00) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x22U) - | (VL_ULL(0xfffffffffffffe00) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - << 2U)))) - | (QData)((IData)( - ((0x100U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xf0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xcU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xaU) - | (0x3fcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x16U)))) - | (3U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U)))))))))); - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] - = __Vtemp515[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] - = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 3U)); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - __Vtemp516[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 0x1dU) - | (0x1fe00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 3U)))) - | (IData)(((((QData)((IData)( - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) - << 0x33U) - | ((VL_ULL(0x7fffffffffe00) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x22U) - | (VL_ULL(0xfffffffffffffe00) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - << 2U)))) - | (QData)((IData)( - ((0x100U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xf0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xcU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xaU) - | (0x3fcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x16U)))) - | (3U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U))))))))) - >> 0x20U))); - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] - = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) - << 0x33U) | ((VL_ULL(0x7fffffffffe00) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x22U) - | (VL_ULL(0xfffffffffffffe00) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - << 2U)))) - | (QData)((IData)( - ((0x100U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xf0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xcU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xaU) - | (0x3fcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x16U)))) - | (3U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U)))))))))); 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- __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] - = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) - << 0x33U) | ((VL_ULL(0x7fffffffffe00) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x22U) - | (VL_ULL(0xfffffffffffffe00) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - << 2U)))) - | (QData)((IData)( - ((0x100U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xf0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 2U)) - | ((0xcU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xaU) - | (0x3fcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x16U)))) - | (3U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U)))))))))); - __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] - = __Vtemp521[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] - = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 3U)); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; - } else { - if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; - } else { - if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; - } else { - if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); - } - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; - } else { - if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); - } - } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; } else { if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)))) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); @@ -26555,8 +13259,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; } else { if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)))) { __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); @@ -26566,8 +13270,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; } else { if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)))) { __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); @@ -26577,1613 +13281,13 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = 0U; } else { if ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)))) { __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))); } } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); - } - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); - } - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table - = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); 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- vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[7].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[6].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[5].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - } - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if ((3U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (3U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U]; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) { - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing)))) { - if ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r))) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.genblk5[4].bank.dwb_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = (7U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r) - - (IData)(1U))); - } - __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (3U & ((IData)(2U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))); - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((1U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data - [((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; - } if (vlTOPp->reset) { __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U] = 0U; @@ -28705,66 +13809,1602 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))][6U]; } if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp276[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp276[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp277[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp277[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp278[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp278[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + __Vtemp279[1U] = ((0xffe00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 0x1eU) + | (0x3fe00000U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 2U)))) + | (IData)(((((QData)((IData)( + (3U + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) + | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U))))))))) + >> 0x20U))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U] + = (IData)((((QData)((IData)((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))) + << 0x33U) | ((VL_ULL(0x7fffffffffe00) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) + << 0x22U) + | (VL_ULL(0xfffffffffffffe00) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) + << 2U)))) + | (QData)((IData)( + ((0x100U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xf0U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + << 2U)) + | ((0xcU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 0xbU) + | (0x7fcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x15U)))) + | (3U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x16U)))))))))); + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U] + = __Vtemp279[1U]; + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U] + = (0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 2U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0 + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)); + __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = (0xfU & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr))); + } + } + } + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = 0U; + __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = 0U; + } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))); 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+ } else { + if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + = ((~ (VL_ULL(1) << (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty); + } } } } if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]); } } } if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]); } } } if ((1U & (~ (IData)(vlTOPp->reset)))) { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]); + } + } + } + if ((1U & (~ (IData)(vlTOPp->reset)))) { + if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)))) { + if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { + __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)); + __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 = 1U; + __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]); } } } if ((1U & (~ (IData)(vlTOPp->reset)))) { if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); } } @@ -28772,12 +15412,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym if ((1U & (~ (IData)(vlTOPp->reset)))) { if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); } } @@ -28785,12 +15425,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym if ((1U & (~ (IData)(vlTOPp->reset)))) { if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); } } @@ -28798,132 +15438,16 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym if ((1U & (~ (IData)(vlTOPp->reset)))) { if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) { vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))); - if ((0x18fU >= (0x1ffU & ((IData)(0x19U) + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))); + if ((0x19fU >= (0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))))) { - VL_ASSIGNSEL_WIII(25,(0x1ffU & ((IData)(0x19U) + VL_ASSIGNSEL_WIII(26,(0x1ffU & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr))), vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table, vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1); } } } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; - } - } if (vlTOPp->reset) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U] = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U] = 0U; @@ -29040,111 +15564,23 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U]; } } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e) { - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - } - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e) { - __Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - } - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e) { - __Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - } - } - } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { - if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]); - } else { - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e) { - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - } - } - } if ((1U & (~ (IData)(vlTOPp->reset)))) { if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { if ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } else { if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e) { __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } } @@ -29156,17 +15592,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } else { if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e) { __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } } @@ -29178,17 +15614,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } else { if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e) { __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } } @@ -29200,698 +15636,22 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])] | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))); __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } else { if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e) { __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 = 1U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } } } } - if ((1U & (~ (IData)(vlTOPp->reset)))) { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { - if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 - = (0xffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U]); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; - __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 - = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - >> 8U))); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; - __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 - = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - >> 0x10U))); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; - __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 - = (0xffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - >> 0x18U))); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; - __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]); 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- } - if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 - = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - >> 8U)); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; - __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 - = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - >> 0x10U)); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; - __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { - __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 - = (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - >> 0x18U)); - __Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; - __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; - __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]); - } - } - } if ((1U & (~ (IData)(vlTOPp->reset)))) { if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)))) { if ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29900,7 +15660,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29911,7 +15671,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29922,7 +15682,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29933,7 +15693,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29942,7 +15702,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29953,7 +15713,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29964,7 +15724,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29975,7 +15735,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29984,7 +15744,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -29995,7 +15755,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30006,7 +15766,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30017,7 +15777,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30026,7 +15786,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30036,7 +15796,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30046,7 +15806,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30056,7 +15816,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]); } } @@ -30069,7 +15829,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30080,7 +15840,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30091,7 +15851,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30102,7 +15862,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30111,7 +15871,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30122,7 +15882,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30133,7 +15893,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30144,7 +15904,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30153,7 +15913,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30164,7 +15924,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30175,7 +15935,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30186,7 +15946,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30195,7 +15955,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30205,7 +15965,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30215,7 +15975,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30225,7 +15985,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]); } } @@ -30238,7 +15998,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30249,7 +16009,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30260,7 +16020,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30271,7 +16031,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30280,7 +16040,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30291,7 +16051,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30302,7 +16062,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30313,7 +16073,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30322,7 +16082,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30333,7 +16093,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30344,7 +16104,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30355,7 +16115,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30364,7 +16124,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30374,7 +16134,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30384,7 +16144,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30394,7 +16154,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]); } } @@ -30407,7 +16167,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 = 0U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30418,7 +16178,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 = 8U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30429,7 +16189,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 = 0x10U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30440,7 +16200,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 = 0x18U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30449,7 +16209,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 = 0x20U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30460,7 +16220,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 = 0x28U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30471,7 +16231,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 = 0x30U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30482,7 +16242,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 = 0x38U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30491,7 +16251,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 = 0x40U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30502,7 +16262,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 = 0x48U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30513,7 +16273,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 = 0x50U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30524,7 +16284,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 = 0x58U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30533,7 +16293,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 = 0x60U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30543,7 +16303,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 = 0x68U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30553,7 +16313,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 = 0x70U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } if ((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable))) { @@ -30563,67 +16323,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym __Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 1U; __Vdlyvlsb__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 = 0x78U; __Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15 - = (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]); } } } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data__v0; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r @@ -30680,134 +16384,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][7U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][8U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0][9U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data__v0[9U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r @@ -30936,110 +16512,78 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data__v0[4U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r @@ -31128,182 +16672,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r @@ -31321,89 +16697,25 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[2U]; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][3U] = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[6U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0][7U] - = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data__v0[7U]; } vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel @@ -31412,158 +16724,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][0U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][1U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][2U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][3U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][4U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][5U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0][6U] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data__v0[6U]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r @@ -31668,14 +16828,62 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym } vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr - = __Vdly__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][0U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[0U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][1U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[1U]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0][2U] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table__v0[2U]; + } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr + = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr; + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } + if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0) { + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0] + = __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag__v0; + } vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = __Vdly__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr @@ -31684,34 +16892,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = __Vdly__VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = __Vdly__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] - = __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; - } if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0] = __Vdlyvval__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v0; @@ -31740,326 +16920,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1) { vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb__v1] = 0U; } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1), - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v1); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2), - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v2); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3), - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v3); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5); 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- } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v4); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v5); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v6); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v7); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v8); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v9); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v10); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v11); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v12); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v13); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v14); - } - if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15) { - VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15), - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15); - } if (__Vdlyvset__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0) { VL_ASSIGNSEL_WIII(8,(IData)(__Vdlyvlsb__VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v0), vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data @@ -32380,40 +17240,20 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data [__Vdlyvdim0__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15], __Vdlyvval__VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data__v15); } + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use + = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) + | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) + - (IData)(1U)))) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + if (vlTOPp->reset) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r = 0U; + } else { + if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) { + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r + = vlTOPp->dram_req_addr; + } + } vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 7U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 6U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 5U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 3U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out @@ -32421,7 +17261,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out @@ -32429,7 +17269,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 1U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out @@ -32437,252 +17277,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); vlTOPp->VX_cache__DOT__per_bank_snp_req_ready = - ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready)) | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - if (vlTOPp->reset) { - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = 0U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = 1U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - } else { - if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) { - __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 - = vlTOPp->dram_req_addr; - __Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 = 1U; - __Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0 - = (1U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)))) { - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 0U; - if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) { - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 1U; - } - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r - = (1U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))); - } - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = (1U & ((IData)(1U) + (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r))); - } - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - = vlTOPp->dram_req_addr; - if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading) { - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = (1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r))); - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)))) { - if (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) { - if (Verilated::assertOn()) { - if (VL_UNLIKELY(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)))) { - VL_WRITEF("[%0t] %%Error: VX_generic_queue.v:144: Assertion failed in %NVX_cache.cache_dram_req_arb.prfqq.pfq_queue.genblk3.genblk2: 'assert' failed.\n", - 64,VL_TIME_Q(), - vlSymsp->name()); - VL_STOP_MT("../../rtl/libs/VX_generic_queue.v", 144, ""); - } - } - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = 1U; - } - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = 0U; - __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r - = (1U & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) - - (IData)(1U))); - } - } - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing) - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r) - | ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)))); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r - = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data - [(1U & ((IData)(1U) + ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading) - ? (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r) - : (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r))))]; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 7U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 6U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 5U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[8U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); - vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 4U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -32724,7 +17324,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 3U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] @@ -32768,7 +17368,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] @@ -32812,7 +17412,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) << 1U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U] @@ -32856,327 +17456,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[9U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[9U]); vlTOPp->VX_cache__DOT__per_bank_core_req_ready - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready)) | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); - vlTOPp->__Vtableidx12 = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx12]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx12]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx12]; - vlTOPp->__Vtableidx11 = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx11]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx11]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx11]; - vlTOPp->__Vtableidx10 = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx10]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx10]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx10]; - vlTOPp->__Vtableidx9 = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx9]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx9]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx9]; - vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx8]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx8]; - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx8]; - vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx7]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx7]; - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx7]; - vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx6]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx6]; - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx6]; - vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index - [vlTOPp->__Vtableidx5]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request - [vlTOPp->__Vtableidx5]; - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i - [vlTOPp->__Vtableidx5]; - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 7U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 6U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 5U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) - << 1U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) - | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use + = ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill) + ? (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + : (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -33225,10 +17510,141 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use - = ((IData)(vlTOPp->reset) ? 0U : ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill) - ? (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - : (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value))); + vlTOPp->__Vtableidx8 = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx8]; + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx8]; + vlTOPp->__Vtableidx7 = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx7]; + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable7_VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx7]; + vlTOPp->__Vtableidx6 = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx6]; + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable6_VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx6]; + vlTOPp->__Vtableidx5 = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + = vlTOPp->__Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i + [vlTOPp->__Vtableidx5]; + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 3U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 2U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)) + << 1U))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); + vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U] + = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] + : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -33245,198 +17661,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[7U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[7U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible - = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[1U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[1U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[2U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[2U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[3U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[3U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[4U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[5U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[5U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] - : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[0U] @@ -33549,146 +17773,38 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r[6U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r[6U]); - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; - } - } - if (vlTOPp->reset) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] = 0U; - } else { - if ((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; - } - } + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0 + = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 8U)); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible + = (1U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table)) + >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr))); if (vlTOPp->reset) { vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] = 0U; @@ -33829,197 +17945,9 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U]; } } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U] - >> 0x12U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0U] - = (3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x12U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0U] - = (VL_ULL(0x1ffffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U])) - << 0x3fU) | - (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[5U])) - << 0x1fU) | - ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U])) - >> 1U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0U] - = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] - >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0U][1U] @@ -34048,25 +17976,25 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 1U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0U] = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0U][1U] @@ -34095,25 +18023,25 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 1U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0U] = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0U][1U] @@ -34142,25 +18070,25 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 1U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0U] = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xeU)); + >> 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0U][1U] @@ -34189,52 +18117,25 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 1U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xfU)); + >> 0x10U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x10U)); + >> 0x11U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0x11U)); + >> 0x12U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0U] = (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] - >> 0xdU)); + >> 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0U] - = (0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] + = (0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[7U] << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value[6U] >> 0x14U))); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r - = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r - = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r - = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r - = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - if (__Vdlyvset__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0) { - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[__Vdlyvdim0__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0] - = __Vdlyvval__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data__v0; - } - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r - = __Vdly__VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty - = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))))) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading + = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) + & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))))) @@ -34251,114 +18152,142 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = (1U & ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))))) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) - | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0 - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw) - >> (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - = ((0x77U >= (0x7fU & ((IData)(0x1eU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? (0x3fffffffU & (((0U == (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - ((IData)(1U) - + (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr[ - (3U & (((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)) - >> 5U))] >> - (0x1fU & ((IData)(0x1eU) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : 0U); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 1U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 2U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + << 3U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0x3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 4U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 2U)) | (0xc0000000U & + ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x1eU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] + = (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) >> 2U)); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 6U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0x14U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) + | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0xcU)) | (0xfff00000U + & ((IData)( + ((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0x14U)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xf3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 8U))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + << 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) + | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) + >> 0x16U)) | (0xfffffc00U + & ((IData)(( + (VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U)) + << 0xaU)))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] + = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = + ((0xfcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) + | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0xaU))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] + = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))); + vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) + | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) + << 0x20U) + | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) + >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) @@ -34468,290 +18397,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) : 0U); vlTOPp->dram_rsp_ready = (0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready)); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0x3fffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0xc000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - = ((0x3fU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) - | (0xffffffc0U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - = ((0x3fU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0x1aU)) | (0xffffffc0U & ((IData)( - ((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xcfffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0x3000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - << 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) - | (0xf0000000U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 0x1cU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - = ((0xfffffffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 4U)) | (0xf0000000U & - ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 0x1cU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - = ((0xffffffc0U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U]) - | (0xfffffffU & ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) >> 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xf3ffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0xc00U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - = ((0x3ffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) - | (0xfffc0000U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 0x12U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U]) - | ((0x3ffffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 0x12U)))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xfcffU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0x300U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) - | (0xffffff00U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 8U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - = ((0xfffc0000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U]) - | ((0xffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0x18U)) | (0xffffff00U & - ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 8U)))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xff3fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0xc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - = ((0x3fffffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) - | (0xc0000000U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 0x1eU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] - = ((0x3fffffffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 2U)) | (0xc0000000U & - ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 0x1eU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U]) - | (0x3fffffffU & ((IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) >> 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xffcfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0x30U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 6U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) - | (0xfff00000U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 0x14U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - = ((0xc0000000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U]) - | ((0xfffffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0xcU)) | (0xfff00000U - & ((IData)( - ((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 0x14U)))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xfff3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (0xcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 8U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] - = ((0x3ffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) - | (0xfffffc00U & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - << 0xaU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U]) - | ((0x3ffU & ((IData)((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))) - >> 0x16U)) | (0xfffffc00U - & ((IData)(( - (VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U)) - << 0xaU)))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]; - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid = - ((0xfffcU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)) - | (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] - = ((0xfffffc00U & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U]) - | (IData)(((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) - | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U])))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (2U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 1U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (4U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 2U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (8U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 3U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x10U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x20U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 5U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x40U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 6U))); - vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - | (0x80U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - << 7U))); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[0U] = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[0U] @@ -34765,263 +18410,31 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[2U] : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[3U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[4U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[4U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[5U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[5U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[6U] - = ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[6U] - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]); + = (0xffffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr[3U] + : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U])); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid - = (0xffU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) - ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) - & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) - : (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U] - & VL_NEGATE_I((IData)((1U & - (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] - = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) - | (0xfffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 4U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1cU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1dU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1eU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1fU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] - = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) - | (0xfffffff0U & (0x70U | (0xffffff80U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0xbU) | - (0x780U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x15U))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) - | (0xffffff00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 8U))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U] - = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[6U]) - | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[3U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x18U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x19U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1aU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x1bU] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) - | (0xffffff00U & (0x600U | (0xfffff800U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0xfU) - | (0x7800U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x11U))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U] - = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[6U]) - | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x11U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] - = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) - | (0xfffff000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 0xcU))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[5U]) - | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x14U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x14U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x15U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x16U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x17U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] - = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) - | (0xfffff000U & (0x5000U | (0xffff8000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x13U) - | (0x78000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0xdU))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[5U]) - | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0xdU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) - | (0xffff0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - << 0x10U))); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U] - = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[4U]) - | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x10U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[2U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x10U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x11U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x12U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0x13U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) - | (0xffff0000U & (0x40000U | (0xfff80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x17U) - | (0x780000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 9U))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U] - = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[4U]) - | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 9U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + = (0xfU & ((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid)) + ? ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid) + & VL_NEGATE_I((IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + : ((vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U) & VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U] = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) | (0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] << 0x14U))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[3U]) - | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0xcU))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0xcU)); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x30U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0xcU] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -35040,26 +18453,25 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) - | (0xfff00000U & (0x300000U | (0xff800000U + | (0xfff00000U & (0x300000U | (0xffc00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x1bU) - | (0x7800000U + << 0x1aU) + | (0x3c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 5U))))))); + >> 6U))))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[3U]) - | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))); + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U] = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) | (0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -35068,11 +18480,13 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[2U]) | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 8U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[1U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffff0000ffffffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x20U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[8U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -35091,26 +18505,26 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) - | (0xff000000U & (0x2000000U | (0xf8000000U + | (0xff000000U & (0x2000000U | (0xfc000000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 0x1fU) - | (0x78000000U + << 0x1eU) + | (0x3c000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 1U))))))); + >> 2U))))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U] = ((0xfff00000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[2U]) | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 1U))); + >> 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -35119,12 +18533,13 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[1U]) | (0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 4U))); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) - | (0xffff0000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0x1bU) | (0x7ff0000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 5U))))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffff0000ffff) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | ((QData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U))))) + << 0x10U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[4U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -35143,33 +18558,34 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) - | (0xf0000000U & (0x10000000U | (0x80000000U + | (0xf0000000U & (0x10000000U | (0xc0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 3U))))); + << 2U))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U] = ((0xff000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[1U]) - | (0xffffffU & ((0xffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 3U)) | - (7U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1dU))))); + | (0xffffffU & ((0xffffffcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 2U)) | + (3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1eU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U] = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[0U]) | (0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[0U]) - | (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))); + vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + = ((VL_ULL(0xffffffffffff0000) & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen) + | (IData)((IData)((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] @@ -35188,759 +18604,31 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x1cU)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U] = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[0U]) - | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 7U) | (0x78U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x19U))))); + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + << 6U) | (0x3cU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + >> 0x1aU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); + >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; - if (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U]) { - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = 1U; - } - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 1U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 2U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 7U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 9U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xaU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xbU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xdU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) : 0U) << 0xfU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); + >> 7U)) & ((~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) | (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel))))); + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual + = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; if (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U]) { @@ -35949,183 +18637,174 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; if (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U]) { @@ -36134,183 +18813,174 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; if (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U]) { @@ -36319,183 +18989,174 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe = 0U; if (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U]) { @@ -36504,199 +19165,174 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((1U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) + ? (1U & ((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U]) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((2U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - << 7U) | ( + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] + << 6U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0U] - >> 0x19U))) + >> 0x1aU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 1U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((4U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - << 0xeU) | + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[1U] - >> 0x12U))) + >> 0x14U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((8U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - << 0x15U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] + << 0x12U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[2U] - >> 0xbU))) + >> 0xeU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x10U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 0x1cU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + << 0x18U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 4U))) + >> 8U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x20U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - << 3U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[3U] - >> 0x1dU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 2U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x40U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - << 0xaU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] - >> 0x16U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + << 4U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[4U] + >> 0x1cU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 6U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x80U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - << 0x11U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] - >> 0xfU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] + << 0xaU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[5U] + >> 0x16U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x100U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - << 0x18U) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] + << 0x10U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[6U] - >> 8U))) + >> 0x10U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 8U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x200U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 0x1fU) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 1U))) + >> 0xaU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 9U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x400U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[7U] - >> 0x1aU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 0x1cU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 4U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xaU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x800U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - << 0xdU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] - >> 0x13U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + << 2U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[8U] + >> 0x1eU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xbU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x1000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - << 0x14U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] - >> 0xcU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + << 8U) | ( + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[9U] + >> 0x18U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x2000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 0x1bU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 5U))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + << 0xeU) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] + >> 0x12U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xdU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x4000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - << 2U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xaU] - >> 0x1eU))) + ? (1U & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + << 0x14U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] + >> 0xcU))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xeU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | (((0x8000U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table)) - ? (1U & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] - << 9U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xbU] - >> 0x17U))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + ? (1U & ((0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[0xcU] + >> 6U)) == + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) : 0U) << 0xfU)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])] << 0x15U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + = ((0xfff00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] << 0x14U)) | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - = ((0x40U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])) << 6U)) | ((0x20U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])) - << 5U)) - | (0x1fffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [ - (0xfU - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])] - >> 0xbU)))); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use - = (((0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid)) - | (0U == ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid) - - (IData)(1U)))) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual - = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); + = ((0x20U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 5U)) | + ((0x10U & ((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]))) << 4U)) + | (0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])] >> 0xcU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = (1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)) & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids)))))); @@ -36732,323 +19368,39 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->__Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i [vlTOPp->__Vtableidx1]; vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) - << 7U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) - << 7U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) << 3U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) << 3U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid) << 2U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid) << 2U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid) << 1U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid) << 1U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid = - ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] - = ((0xfU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) - | (0xfffffff0U & (0x70U | (0xffffff80U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0xdU) | - (0x1f80U & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x13U))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] - = ((0xffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) - | (0xffffff00U & (0x600U | (0xfffff800U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0x11U) - | (0x1f800U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0xfU))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U] - = ((0xfffffff0U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]) - | (0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0xfU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] - = ((0xfffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) - | (0xfffff000U & (0x5000U | (0xffff8000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0x15U) - | (0x1f8000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0xbU))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U] - = ((0xffffff00U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]) - | (0xffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0xbU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] - = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[2U] - = ((0xc00U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - << 0xaU)) | (IData)(((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U)))) - >> 0x20U))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] - = ((0xffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) - | (0xffff0000U & (0x40000U | (0xfff80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 0x19U) - | (0x1f80000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 7U))))))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U] - = ((0xfffff000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]) - | (0xfffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 7U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))) & (~ ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in - = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -37074,16 +19426,15 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x20U))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] = ((0xfffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]) - | (0xfff00000U & (0x300000U | (0xff800000U + | (0xfff00000U & (0x300000U | (0xffc00000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] << 0x1dU) - | (0x1f800000U + | (0x1fc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] >> 3U))))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U] - = ((0xffff0000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]) - | (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 3U))); + = (0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] @@ -37111,8 +19462,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -37138,7 +19489,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x20U))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] = ((0xffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U]) - | (0xff000000U & (0x2000000U | (0xf8000000U + | (0xff000000U & (0x2000000U | (0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] << 1U))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U] @@ -37174,8 +19525,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -37201,7 +19552,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x20U))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] = ((0xfffffffU & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) - | (0xf0000000U & (0x10000000U | (0x80000000U + | (0xf0000000U & (0x10000000U | (0xc0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] << 5U))))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[1U] @@ -37237,8 +19588,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 2U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U)); + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[1U] = (IData)((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) @@ -37264,8 +19615,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x20U))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U] = ((0xf0000000U & vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[0U]) - | (0xffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 9U) | (0x1f8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + | (0xffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (0x1fcU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] >> 0x17U))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual = (1U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -37292,374 +19643,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0x13U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U))) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffeU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffdU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffeU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 1U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfffbU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffffcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 2U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfff7U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 3U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffefU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffff0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 4U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffdfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffe0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 5U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xffbfU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffffc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 6U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xff7fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 7U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfeffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffff00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 8U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfdffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffe00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 9U) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xfbffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffffc00U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xaU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xf7ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff800U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xbU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xefffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xfffff000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xcU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xdfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffe000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xdU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0xbfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffffc000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xeU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready - = ((0x7fffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)) - | (0xffff8000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] - = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][2U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][3U] - = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] - = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) @@ -37734,8 +19717,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -37746,12 +19729,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) @@ -37826,8 +19809,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -37838,12 +19821,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) @@ -37918,8 +19901,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -37930,12 +19913,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) @@ -38010,8 +19993,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 0xfU) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0U] = (0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] - >> 0x15U))); + << 0xcU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U] + >> 0x14U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0U][1U] @@ -38022,27 +20005,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 5U)); + >> 4U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0U] = (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[5U] - >> 6U)); + >> 5U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0U] - = (0x1fffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); + = (0xfffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[4U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); @@ -38055,8 +20023,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->core_rsp_tag = ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + vlTOPp->core_rsp_tag = ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (VL_ULL(0x3ffffffffff) & (((0U == (0x1fU & ((IData)(0x2aU) @@ -38066,7 +20034,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(2U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -38078,7 +20046,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -38092,7 +20060,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | ((QData)((IData)( vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))])) @@ -38104,24 +20072,23 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) - + (0xfU & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] << ((IData)(0x20U) - (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] >> + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)))) { @@ -38134,8 +20101,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] >> 0xaU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -38143,7 +20110,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38154,10 +20121,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -38172,8 +20139,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] >> 0x14U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -38181,7 +20148,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38192,10 +20159,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -38210,8 +20177,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] >> 0x1eU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -38219,7 +20186,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38230,10 +20197,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -38243,158 +20210,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 6U)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - >> 8U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 8U)))); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - >> 0x12U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 0xaU)))); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - >> 0x1cU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 0xcU)))); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - >> 6U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) - | ((IData)(1U) << - (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 0xeU)))); - } vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; @@ -38402,24 +20217,23 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) - + (0xfU & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] + + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] << ((IData)(0x20U) - (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] >> + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)))) { @@ -38432,8 +20246,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] >> 0xaU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -38441,7 +20255,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38452,10 +20266,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -38469,8 +20283,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] >> 0x14U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -38478,7 +20292,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38489,10 +20303,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -38506,8 +20320,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] >> 0x1eU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -38515,7 +20329,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38526,10 +20340,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & ( + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) @@ -38538,171 +20352,23 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 4U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - << 0x18U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - >> 8U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[4U]); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 5U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - << 0xeU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - >> 0x12U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[5U]); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 6U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - << 4U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - >> 0x1cU))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 7U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[6U]); - } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 7U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - << 0x1aU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - >> 6U))) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & - (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { - VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) - >> 9U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, - vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[7U]); - } vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) - == ((0x14fU >= (0x1ffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (((0U == (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) - + (0xfU + + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38711,23 +20377,23 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] >> (0x1fU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) << 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] >> 0xaU))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (( (0U == @@ -38739,7 +20405,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38750,7 +20416,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))] @@ -38760,16 +20426,16 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)) << 1U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) << 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] >> 0x14U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (( (0U == @@ -38781,7 +20447,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38792,7 +20458,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))] @@ -38802,16 +20468,16 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)) << 2U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) | (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) << 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] >> 0x1eU))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + == ((0xa7U >= (0xffU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (0xffU & (( (0U == @@ -38823,7 +20489,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))] @@ -38834,7 +20500,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))] @@ -38843,174 +20509,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) : 0U)) << 3U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffff0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 4U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - << 0x18U) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[5U] - >> 8U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 4U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xffffffe0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 5U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - << 0xeU) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[6U] - >> 0x12U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 5U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xffffffc0U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 6U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[8U] - << 4U) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[7U] - >> 0x1cU))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 6U)))); - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xffffff80U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 7U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0xaU] - << 0x1aU) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[9U] - >> 6U))) - == ((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (( - (0U - == - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)) << 7U)))); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = 0U; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r) @@ -39038,304 +20536,66 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i = vlTOPp->__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i [vlTOPp->__Vtableidx2]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))); 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- vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] - = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual - = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); @@ -39348,55 +20608,61 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); @@ -39409,55 +20675,61 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); @@ -39470,55 +20742,61 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[0U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) | (0xfffffffU & + << 5U)) | (0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[1U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[2U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[3U] - = ((0xfffffffU & ((0xffffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U)) | + = ((0xfffffffU & ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x1cU))) | (0xf0000000U + >> 0x1bU))) | (0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 4U))); + << 5U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[4U] = ((0xf0000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 2U)) | (0xfffffffU & - ((0xffffff0U + << 3U)) | (0xfffffffU & + ((0xfffffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x1cU)))); + >> 0x1bU)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[5U] - = ((0xffe00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 4U)) | (0x1fffffU & ( - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U))); + = ((0xffc00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + << 5U)) | (0xfffffffU & + ((0x3ffffcU & + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 1U)) | + (3U & ((0xffffff8U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 3U)) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x1dU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[6U] - = ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) - << 6U)) | ((0xffffffe0U + = ((0xffffff80U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) + << 7U)) | ((0xffffffc0U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in) - << 5U)) | - (0x1fU & ((0x1ffff0U + << 6U)) | + (0x3fU & ((0x3fffe0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 4U)) + << 5U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x1cU))))); + >> 0x1bU))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); @@ -39526,74 +20804,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = (1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual - = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual))) @@ -39608,8 +20818,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) @@ -39625,8 +20835,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) @@ -39642,8 +20852,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual = (((((((0xbU >= (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)) @@ -39659,8 +20869,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match - = ((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + = ((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U)) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U]); vlTOPp->core_rsp_data[0U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[0U]; vlTOPp->core_rsp_data[1U] = vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U]; @@ -39677,7 +20887,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = ((IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r) | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))); - vlTOPp->snp_rsp_tag = ((0xdfU >= (0xffU & ((IData)(0x1cU) + vlTOPp->snp_rsp_tag = ((0x6fU >= (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))) ? (0xfffffffU & (((0U == (0x1fU @@ -39687,7 +20897,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) >> 5U)))] @@ -39698,7 +20908,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))))) | (vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)) >> 5U))] @@ -39715,33 +20925,12 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r) | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))); vlTOPp->dram_req_byteen = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) - ? (0xffffU & (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 4U))) - ? 0U - : ( - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ - ((IData)(1U) - + - (3U - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - >> 1U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 4U))))) - | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen[ - (3U - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - >> 1U))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 4U))))) + ? (0xffffU & (IData)( + (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen + >> + (0x3fU + & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 4U))))) : 0xffffU); vlTOPp->dram_req_data[0U] = ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) ? (((0U == (0x1fU @@ -39749,7 +20938,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(1U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -39758,8 +20947,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ - (0x1cU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) - << 2U))] + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) + << 2U))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 7U)))) @@ -39770,7 +20959,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(2U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -39780,7 +20969,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(1U) - + (0x1cU & + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] >> (0x1fU & @@ -39793,7 +20982,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(3U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -39803,7 +20992,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(2U) - + (0x1cU & + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] >> (0x1fU & @@ -39816,7 +21005,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U))) ? 0U : (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(4U) - + (0x1cU + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] << ((IData)(0x20U) @@ -39826,7 +21015,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data[ ((IData)(3U) - + (0x1cU & + + (0xcU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank) << 2U)))] >> (0x1fU & @@ -39834,9 +21023,9 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U)))) : 0U); vlTOPp->dram_req_addr = (0xfffffffU & ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid) - ? ((0xdfU + ? ((0x6fU >= - (0xffU + (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))) ? ( @@ -39850,7 +21039,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) >> 5U)))] @@ -39861,7 +21050,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))))) | (vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)) >> 5U))] @@ -39872,9 +21061,9 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U) : ((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req) ? ( - (0xdfU + (0x6fU >= - (0xffU + (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) ? @@ -39888,7 +21077,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U)))] @@ -39899,7 +21088,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U))] @@ -39909,134 +21098,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))) : 0U) : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2 - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); @@ -40044,19 +21105,19 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall @@ -40076,19 +21137,19 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall @@ -40108,19 +21169,19 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall @@ -40140,19 +21201,19 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( + & ((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])))) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall @@ -40165,74 +21226,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss - = ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) | - ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 @@ -40303,233 +21296,9 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)))); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing = ((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))); vlTOPp->dram_req_tag = vlTOPp->dram_req_addr; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - << 7U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 7U) | (0x1f80U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 7U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall))) - << 7U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - << 6U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 6U) | (0xfc0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 6U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall))) - << 6U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - << 5U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 5U) | (0x7e0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 5U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall))) - << 5U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing - = (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - << 4U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << 4U) | (0x3f0U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U) - & ((~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)) - << 4U))))) - & ((~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall))) - << 4U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe - = ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e - = (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) @@ -40552,7 +21321,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) << 3U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << 3U) | (0x1f8U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -40575,11 +21344,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) @@ -40608,7 +21377,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) << 2U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << 2U) | (0xfcU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -40631,11 +21400,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) @@ -40664,7 +21433,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) << 1U) & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << 1U) | (0x7eU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -40687,11 +21456,11 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) @@ -40720,7 +21489,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -40739,97 +21508,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U])) & ((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | ( + << 7U) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][0U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][1U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][2U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 @@ -40910,122 +21599,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][3U] : vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq - = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending - = (((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq = (1U & (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] @@ -41120,15 +21693,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[2U] = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[2U]; vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[3U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[4U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[5U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[5U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[6U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[6U]; - vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[7U] - = vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid; + = ((0xffff0000U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid) + << 0x10U)) | vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr[3U]); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing = (((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) @@ -41162,3514 +21728,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U] | vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head - = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) - & (0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp749[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ( - (VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp749[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - >> 0x1fU)) | (0xfffffffeU - & ((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0)))) - >> 0x20U)) - << 1U))); - __Vtemp750[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? 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- ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - << 0x12U)) | - __Vtemp749[5U]); - __Vtemp750[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? 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- (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp750[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 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( - (VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp762[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - >> 0x1fU)) | (0xfffffffeU - & ((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0)))) - >> 0x20U)) - << 1U))); - __Vtemp763[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? 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- ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - << 0x12U)) | - __Vtemp762[5U]); - __Vtemp763[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? 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- (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp763[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 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((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - >> 0x1fU)) | (0xfffffffeU - & ((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? 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- (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp776[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 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((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))) - >> 0x1fU)) | (0xfffffffeU - & ((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0)))) - >> 0x20U)) - << 1U))); - __Vtemp789[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? 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- ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - << 0x12U)) | - __Vtemp788[5U]); - __Vtemp789[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? 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- (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U)))))) - >> 0xeU)) | (0xfffc0000U - & ((IData)( - ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - << 0x12U))); - __Vtemp789[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) - << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U))))))))))) - << 0x20U) - | (QData)((IData)( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (((0U - == - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))))) - >> 0x20U)) - >> 0xeU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[0U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[1U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[2U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[3U] - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp788[4U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp789[5U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp789[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp789[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e - = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) - | (((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); @@ -44686,7 +21744,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp801[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp401[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -44744,7 +21802,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp801[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp401[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -44859,72 +21917,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp802[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp402[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -44932,41 +21988,41 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -44981,7 +22037,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -45022,73 +22078,71 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp801[5U]); - __Vtemp802[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp401[5U]); + __Vtemp402[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -45096,42 +22150,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -45145,7 +22199,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -45188,9 +22242,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -45201,8 +22253,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -45216,7 +22268,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -45228,31 +22280,31 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -45260,35 +22312,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -45309,7 +22361,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -45351,72 +22403,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp802[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp402[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -45424,42 +22474,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -45473,7 +22523,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -45532,13 +22582,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp801[4U]; + = __Vtemp401[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp802[5U]; + = __Vtemp402[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp802[6U]; + = __Vtemp402[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp802[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp402[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -45563,7 +22614,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp814[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp415[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -45621,7 +22672,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp814[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp415[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -45736,72 +22787,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp815[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp416[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -45809,41 +22858,41 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -45858,7 +22907,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -45899,73 +22948,71 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp814[5U]); - __Vtemp815[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp415[5U]); + __Vtemp416[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -45973,42 +23020,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -46022,7 +23069,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -46065,9 +23112,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -46078,8 +23123,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -46093,7 +23138,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -46105,31 +23150,31 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -46137,35 +23182,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -46186,7 +23231,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -46228,72 +23273,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp815[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp416[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -46301,42 +23344,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -46350,7 +23393,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -46409,13 +23452,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp814[4U]; + = __Vtemp415[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp815[5U]; + = __Vtemp416[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp815[6U]; + = __Vtemp416[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp815[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp416[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -46440,7 +23484,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp827[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp429[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -46498,7 +23542,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp827[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp429[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -46613,72 +23657,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp828[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp430[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -46686,41 +23728,41 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -46735,7 +23777,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -46776,73 +23818,71 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp827[5U]); - __Vtemp828[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp429[5U]); + __Vtemp430[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -46850,42 +23890,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -46899,7 +23939,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -46942,9 +23982,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -46955,8 +23993,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -46970,7 +24008,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -46982,31 +24020,31 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -47014,35 +24052,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -47063,7 +24101,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -47105,72 +24143,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp828[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp430[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -47178,42 +24214,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -47227,7 +24263,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -47286,13 +24322,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp827[4U]; + = __Vtemp429[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp828[5U]; + = __Vtemp430[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp828[6U]; + = __Vtemp430[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp828[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp430[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -47317,7 +24354,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - __Vtemp840[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp443[4U] = ((0xfffffffeU & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ( (VL_ULL(0x1ffffffffff80) & (((QData)((IData)( @@ -47375,7 +24412,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 7U) : VL_ULL(0))))) << 1U)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); - __Vtemp840[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp443[5U] = ((1U & ((IData)(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -47490,72 +24527,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : VL_ULL(0)))) >> 0x20U)) << 1U))); - __Vtemp841[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp444[5U] = ((0xfffc0000U & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -47563,41 +24598,41 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) << 2U)) - | (3U + | (3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U @@ -47612,7 +24647,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -47653,73 +24688,71 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U)))) : 0U)))))) << 0x12U)) | - __Vtemp840[5U]); - __Vtemp841[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp443[5U]); + __Vtemp444[6U] = ((0x3ffffU & ((IData)((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -47727,42 +24760,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -47776,7 +24809,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -47819,9 +24852,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym >> 0xeU)) | (0xfffc0000U & ((IData)( ((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) - | ((0x40000000U + ((0x80000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -47832,8 +24863,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U)) - << 0x1eU)) - | ((0x20000000U + << 0x1fU)) + | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U @@ -47847,7 +24878,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U)) - << 0x1dU)) + << 0x1eU)) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : @@ -47859,31 +24890,31 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))) - << 0x1cU) + << 0x1dU) | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU + << 0x1cU) + | ((0xffffffcU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -47891,35 +24922,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) @@ -47940,7 +24971,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -47982,72 +25013,70 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U))))) >> 0x20U)) << 0x12U))); - __Vtemp841[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - << 0x1fU) + __Vtemp444[7U] = (0x3ffffU & ((IData)(((((QData)((IData)( + ((0x80000000U + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + (1U + & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U + : 0U)) + << 0x1fU)) | ((0x40000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U - : 0U)) - << 0x1eU)) - | ((0x20000000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - (1U - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (1U - & (IData)( + ? + (1U + & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) - : 0U)) - << 0x1dU)) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U - : - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))) + : 0U)) + << 0x1eU)) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U + : + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))) + << 0x1dU) + | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) << 0x1cU) - | ((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)) - << 0x1bU) - | ((0x7fffffcU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? - (0x1ffffffU + | ((0xffffffcU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? + (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -48055,42 +25084,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) : 0U)))) - << 2U)) - | (3U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + << 2U)) + | (3U + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) @@ -48104,7 +25133,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) - : 0U))))))))))) + : 0U)))))))))) << 0x20U) | (QData)((IData)( ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) @@ -48163,13 +25192,14 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] : 0U); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[4U] - = __Vtemp840[4U]; + = __Vtemp443[4U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[5U] - = __Vtemp841[5U]; + = __Vtemp444[5U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[6U] - = __Vtemp841[6U]; + = __Vtemp444[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[7U] - = __Vtemp841[7U]; + = ((0xfffc0000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + << 0x12U)) | __Vtemp444[7U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e = (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)) @@ -48178,1093 +25208,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)))); - __Vtemp842[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp446[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp842[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp446[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp842[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp446[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp842[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp446[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp849[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp842[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp842[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U)))))))) - << 0x18U))); - __Vtemp849[7U] = ((0xffffffU & ((IData)((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp842[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp842[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U)))))))) - >> 8U)) | (0xff000000U - & ((IData)( - ((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp842[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp842[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - << 0x18U))); - __Vtemp850[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp842[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp842[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - >> 8U))); - __Vtemp851[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - << 0x18U)) - | ((0x3800000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U] - << 0x17U)) - | ((0x3c00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U] - << 0x16U)) - | ((0x3e00000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)) - << 0x15U)) - | ((0x3f00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] - << 0x14U)) - | ((0x3f80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - << 0x13U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U] - >> 6U))))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] - = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] - = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] << 0x11U)) | (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U] - << 3U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e) - << 2U)) - | ((0xfffffffeU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e) - << 1U)) - | (0x1ffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] - >> 0xfU)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] - << 0x18U))); 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- __Vtemp885[7U] = ((0xffffffU & ((IData)((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp878[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp878[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U)))))))) - >> 8U)) | (0xff000000U - & ((IData)( - ((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp878[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp878[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - << 0x18U))); - __Vtemp886[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U])) - << 0x20U) - | (QData)((IData)( - (((0U - == - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U - : - (__Vtemp878[ - ((IData)(1U) - + - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << - ((IData)(0x20U) - - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp878[ - (3U - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))))) - >> 0x20U)) - >> 8U))); - __Vtemp887[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - << 0x18U)) - | ((0x3800000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U] - << 0x17U)) - | ((0x3c00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U] - << 0x16U)) - | ((0x3e00000U - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)) - << 0x15U)) - | ((0x3f00000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] - << 0x14U)) - | ((0x3f80000U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - << 0x13U)) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U] - >> 6U))))))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] - = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[1U] - = ((0xfffe0000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] << 0x11U)) | (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U] - << 3U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e) - << 2U)) - | ((0xfffffffeU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e) - << 1U)) - | (0x1ffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U] - >> 0xfU)))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] - << 0x18U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp885[6U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp885[7U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp886[8U]); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] - = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])) << 0x1bU)) | - ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp887[9U])); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write - = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U]) & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e))) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp890[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp890[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp890[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp890[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - __Vtemp897[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp453[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49277,7 +25231,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp890[ + (__Vtemp446[ ((IData)(1U) + (3U @@ -49290,7 +25244,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp890[ + | (__Vtemp446[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49299,8 +25253,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp897[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp453[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49313,7 +25267,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp890[ + (__Vtemp446[ ((IData)(1U) + (3U @@ -49326,7 +25280,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp890[ + | (__Vtemp446[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49335,7 +25289,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 @@ -49350,7 +25304,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp890[ + (__Vtemp446[ ((IData)(1U) + (3U @@ -49363,7 +25317,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp890[ + | (__Vtemp446[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49373,10 +25327,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp898[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp454[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49389,7 +25343,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp890[ + (__Vtemp446[ ((IData)(1U) + (3U @@ -49402,7 +25356,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp890[ + | (__Vtemp446[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49412,39 +25366,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp899[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp456[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -49453,7 +25403,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -49464,8 +25414,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -49480,42 +25430,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp897[6U]; + = __Vtemp453[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp897[7U]; + = __Vtemp453[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp898[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp454[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp899[9U])); + [0U] << 0x1aU)) | __Vtemp456[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 @@ -49523,17 +25473,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp902[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp459[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp902[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp459[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp902[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp459[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp902[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp459[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp909[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp466[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49546,7 +25496,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp902[ + (__Vtemp459[ ((IData)(1U) + (3U @@ -49559,7 +25509,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp902[ + | (__Vtemp459[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49568,8 +25518,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp909[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp466[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49582,7 +25532,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp902[ + (__Vtemp459[ ((IData)(1U) + (3U @@ -49595,7 +25545,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp902[ + | (__Vtemp459[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49604,7 +25554,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 @@ -49619,7 +25569,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp902[ + (__Vtemp459[ ((IData)(1U) + (3U @@ -49632,7 +25582,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp902[ + | (__Vtemp459[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49642,10 +25592,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp910[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp467[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49658,7 +25608,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp902[ + (__Vtemp459[ ((IData)(1U) + (3U @@ -49671,7 +25621,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp902[ + | (__Vtemp459[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49681,39 +25631,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp911[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp469[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -49722,7 +25668,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -49733,8 +25679,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -49749,42 +25695,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp909[6U]; + = __Vtemp466[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp909[7U]; + = __Vtemp466[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp910[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp467[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp911[9U])); + [0U] << 0x1aU)) | __Vtemp469[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 @@ -49792,17 +25738,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp914[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp472[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp914[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp472[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp914[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp472[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp914[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp472[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp921[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp479[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49815,7 +25761,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp914[ + (__Vtemp472[ ((IData)(1U) + (3U @@ -49828,7 +25774,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp914[ + | (__Vtemp472[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49837,8 +25783,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp921[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp479[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49851,7 +25797,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp914[ + (__Vtemp472[ ((IData)(1U) + (3U @@ -49864,7 +25810,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp914[ + | (__Vtemp472[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49873,7 +25819,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 @@ -49888,7 +25834,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp914[ + (__Vtemp472[ ((IData)(1U) + (3U @@ -49901,7 +25847,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp914[ + | (__Vtemp472[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49911,10 +25857,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp922[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp480[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -49927,7 +25873,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp914[ + (__Vtemp472[ ((IData)(1U) + (3U @@ -49940,7 +25886,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp914[ + | (__Vtemp472[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -49950,39 +25896,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp923[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp482[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -49991,7 +25933,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -50002,8 +25944,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -50018,42 +25960,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp921[6U]; + = __Vtemp479[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp921[7U]; + = __Vtemp479[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp922[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp480[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp923[9U])); + [0U] << 0x1aU)) | __Vtemp482[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 @@ -50061,17 +26003,17 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - __Vtemp926[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp485[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp926[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp485[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp926[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp485[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp926[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp485[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - __Vtemp933[6U] = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U] >> 8U)) - | (0xff000000U & ((IData)((((QData)((IData)( + __Vtemp492[6U] = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U] >> 9U)) + | (0xff800000U & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -50084,7 +26026,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp926[ + (__Vtemp485[ ((IData)(1U) + (3U @@ -50097,7 +26039,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp926[ + | (__Vtemp485[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -50106,8 +26048,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - << 0x18U))); - __Vtemp933[7U] = ((0xffffffU & ((IData)((((QData)((IData)( + << 0x17U))); + __Vtemp492[7U] = ((0x7fffffU & ((IData)((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -50120,7 +26062,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp926[ + (__Vtemp485[ ((IData)(1U) + (3U @@ -50133,7 +26075,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp926[ + | (__Vtemp485[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -50142,7 +26084,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U)))))))) - >> 8U)) | (0xff000000U + >> 9U)) | (0xff800000U & ((IData)( ((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 @@ -50157,7 +26099,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp926[ + (__Vtemp485[ ((IData)(1U) + (3U @@ -50170,7 +26112,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp926[ + | (__Vtemp485[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -50180,10 +26122,10 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - << 0x18U))); - __Vtemp934[8U] = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 - [0U] << 0x18U)) - | (0xffffffU & ((IData)(((((QData)((IData)( + << 0x17U))); + __Vtemp493[8U] = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U] << 0x17U)) + | (0x7fffffU & ((IData)(((((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U])) << 0x20U) @@ -50196,7 +26138,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U))) ? 0U : - (__Vtemp926[ + (__Vtemp485[ ((IData)(1U) + (3U @@ -50209,7 +26151,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp926[ + | (__Vtemp485[ (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U])] @@ -50219,39 +26161,35 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] << 5U))))))) >> 0x20U)) - >> 8U))); - __Vtemp935[9U] = (0x3ffffffU & ((0x2000000U & ( - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 - [0U])) - & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 - [0U])) - << 0x19U)) - | ((0x3000000U + >> 9U))); + __Vtemp495[9U] = ((0xfe000000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + [0U])) << 0x19U)) + | (0x1ffffffU & ((0x1000000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) << 0x18U)) - | ((0x3800000U + | ((0x1800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U] << 0x17U)) - | ((0x3c00000U + | ((0x1c00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 [0U] << 0x16U)) - | ((0x3e00000U + | ((0x1e00000U & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)) << 0x15U)) - | ((0x3f00000U + | ((0x1f00000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U] << 0x14U)) - | ((0x3f80000U + | ((0x1f80000U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ @@ -50260,7 +26198,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 0x13U)) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U] - >> 6U))))))))); + >> 7U))))))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[0U] = (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U]); @@ -50271,8 +26209,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0x20U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[2U] - = ((0xff000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] << 0x18U)) | ((0xfffffff8U + = ((0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] << 0x17U)) | ((0xfffffff8U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c [0U] << 3U)) @@ -50287,42 +26225,42 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 0xfU)))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[3U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[4U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[5U] - = ((0xffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U] >> 8U)) | (0xff000000U + = ((0x7fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U] >> 9U)) | (0xff800000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U] - << 0x18U))); + << 0x17U))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[6U] - = __Vtemp933[6U]; + = __Vtemp492[6U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[7U] - = __Vtemp933[7U]; + = __Vtemp492[7U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[8U] - = ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U] << 0x1aU)) | __Vtemp934[8U]); + = ((0xfe000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] << 0x19U)) | __Vtemp493[8U]); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[9U] = ((0xf8000000U & ((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])) << 0x1bU)) | ((0xfc000000U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 - [0U] << 0x1aU)) | __Vtemp935[9U])); + [0U] << 0x1aU)) | __Vtemp495[9U])); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = ((((((IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U)) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 @@ -50330,146 +26268,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e))) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 2U))) - : 0U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xff0fU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xf0ffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 8U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we - = ((0xfffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we)) - | (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - ? 0xfU : (((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)) - ? (0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U))) - : 0U)) << 0xcU)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we = ((0xfff0U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we)) | ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) @@ -50610,22 +26408,6 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym [0U] >> 2U))) : 0U)) << 0xcU)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable - = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) - ? 0U : (0xffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U] & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill))) @@ -50648,94 +26430,30 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp VL_DEBUG_IF(VL_DBG_MSGF("+ VVX_cache::_combo__TOP__5\n"); ); VVX_cache* __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp; // Body - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) - << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) - << 0x1cU) - | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in - = (((QData)((IData)((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U)))) + = (((QData)((IData)((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U)))) << 0x1dU) | (QData)((IData)((((IData)(vlTOPp->snp_req_invalidate) << 0x1cU) | vlTOPp->snp_req_tag)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] - = vlTOPp->dram_rsp_data[0U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] - = vlTOPp->dram_rsp_data[1U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[2U] - = vlTOPp->dram_rsp_data[2U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] - = vlTOPp->dram_rsp_data[3U]; - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] = vlTOPp->dram_rsp_data[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] @@ -50745,7 +26463,7 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] = vlTOPp->dram_rsp_data[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] @@ -50755,7 +26473,7 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] = vlTOPp->dram_rsp_data[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] @@ -50765,7 +26483,7 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[0U] = vlTOPp->dram_rsp_data[0U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[1U] @@ -50775,184 +26493,100 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[3U] = vlTOPp->dram_rsp_data[3U]; vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[4U] - = (0x1ffffffU & (vlTOPp->dram_rsp_tag >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (7U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (6U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (5U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing - = (((IData)(vlTOPp->snp_req_valid) & (4U == - (7U & vlTOPp->snp_req_addr))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); + = (0x3ffffffU & (vlTOPp->dram_rsp_tag >> 2U)); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (3U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (2U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (1U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = (((IData)(vlTOPp->snp_req_valid) & (0U == - (7U & vlTOPp->snp_req_addr))) + (3U & vlTOPp->snp_req_addr))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (7U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (6U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (5U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing - = (((IData)(vlTOPp->dram_rsp_valid) & (4U == - (7U - & vlTOPp->dram_rsp_tag))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (3U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (2U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (1U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing = (((IData)(vlTOPp->dram_rsp_valid) & (0U == - (7U + (3U & vlTOPp->dram_rsp_tag))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); vlTOPp->snp_req_ready = (1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) - >> (7U & vlTOPp->snp_req_addr))); - vlTOPp->core_req_ready = (0xffU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) - | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); + >> (3U & vlTOPp->snp_req_addr))); + vlTOPp->core_req_ready = (0xfU == ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_req_ready) + | (IData)(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel))); vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready = ((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_rsp_ready)))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | ((IData)(vlTOPp->snp_rsp_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank)))); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | (((IData)(vlTOPp->snp_rsp_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) << 1U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | (((IData)(vlTOPp->snp_rsp_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) << 2U)); vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) + ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) | (((IData)(vlTOPp->snp_rsp_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) << 3U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (4U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (5U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (6U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready = - ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)) - | (((IData)(vlTOPp->snp_rsp_ready) & (7U == (IData)(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank))) - << 7U)); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop = (((~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)) & (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)) & (IData)(vlTOPp->dram_req_ready)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xfeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | ((IData)(vlTOPp->dram_req_ready) & (0U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank)))); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xfdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | (((IData)(vlTOPp->dram_req_ready) & (1U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) << 1U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xfbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | (((IData)(vlTOPp->dram_req_ready) & (2U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) << 2U)); vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xf7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) + = ((7U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) | (((IData)(vlTOPp->dram_req_ready) & (3U == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) << 3U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xefU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (4U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 4U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xdfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (5U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 5U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0xbfU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (6U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 6U)); - vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready - = ((0x7fU & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)) - | (((IData)(vlTOPp->dram_req_ready) & (7U - == (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank))) - << 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid - = (0xfU & (vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & ((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) >> 4U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) >> 8U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid + = (0xfU & (((IData)(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid) >> 0xcU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x10U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x14U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x18U) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid - = (0xfU & ((vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid - >> 0x1cU) & VL_NEGATE_I((IData)((IData)(vlTOPp->core_req_ready))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)) @@ -50969,22 +26603,6 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 3U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 4U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 5U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 6U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading - = (1U & (((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 7U)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid) & (IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready)); @@ -51000,26 +26618,11 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 7U)); vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading = ((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) - & (~ ((~ (IData)((0U != (0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + & (~ ((~ (IData)((0U != (0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire @@ -51037,22 +26640,6 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) >> 3U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 4U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 5U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 6U)); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire - = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 7U)); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) @@ -51253,294 +26840,50 @@ VL_INLINE_OPT void VVX_cache::_combo__TOP__5(VVX_cache__Syms* __restrict vlSymsp | (0x3ffU & (vlTOPp->core_req_addr[3U] >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing - = ((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[0U] - = (IData)(vlTOPp->core_req_tag); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[1U] - = ((0xfffffc00U & (vlTOPp->core_req_data[0U] - << 0xaU)) | (IData)((vlTOPp->core_req_tag - >> 0x20U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[2U] - = ((0x3ffU & (vlTOPp->core_req_data[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[3U] - = ((0x3ffU & (vlTOPp->core_req_data[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[4U] - = ((0x3ffU & (vlTOPp->core_req_data[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_data[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[5U] - = ((0xfffffc00U & (vlTOPp->core_req_addr[0U] - << 0xaU)) | (0x3ffU & (vlTOPp->core_req_data[3U] - >> 0x16U))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[6U] - = ((0x3ffU & (vlTOPp->core_req_addr[0U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[1U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[7U] - = ((0x3ffU & (vlTOPp->core_req_addr[1U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[2U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[8U] - = ((0x3ffU & (vlTOPp->core_req_addr[2U] >> 0x16U)) - | (0xfffffc00U & (vlTOPp->core_req_addr[3U] - << 0xaU))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[9U] - = ((0xffc00000U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid) - << 0x16U)) | ((0xfffc0000U - & ((IData)(vlTOPp->core_req_rw) - << 0x12U)) - | ((0xfffffffcU - & ((IData)(vlTOPp->core_req_byteen) - << 2U)) - | (0x3ffU - & (vlTOPp->core_req_addr[3U] - >> 0x16U))))); vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading - = ((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))); } void VVX_cache::_eval(VVX_cache__Syms* __restrict vlSymsp) { @@ -51670,25 +27013,25 @@ void VVX_cache::_ctor_var_reset() { snp_fwdin_valid = VL_RAND_RESET_I(2); snp_fwdin_tag = VL_RAND_RESET_I(2); snp_fwdin_ready = VL_RAND_RESET_I(2); - VX_cache__DOT__per_bank_core_req_ready = VL_RAND_RESET_I(8); - VX_cache__DOT__per_bank_core_rsp_valid = VL_RAND_RESET_I(8); - VX_cache__DOT__per_bank_core_rsp_tid = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(256, VX_cache__DOT__per_bank_core_rsp_data); - VL_RAND_RESET_W(336, VX_cache__DOT__per_bank_core_rsp_tag); - VX_cache__DOT__per_bank_core_rsp_ready = VL_RAND_RESET_I(8); - VX_cache__DOT__per_bank_dram_fill_req_valid = VL_RAND_RESET_I(8); - VL_RAND_RESET_W(224, VX_cache__DOT__per_bank_dram_fill_req_addr); - VX_cache__DOT__per_bank_dram_fill_rsp_ready = VL_RAND_RESET_I(8); - VX_cache__DOT__per_bank_dram_wb_req_ready = VL_RAND_RESET_I(8); - VX_cache__DOT__per_bank_dram_wb_req_valid = VL_RAND_RESET_I(8); - VL_RAND_RESET_W(128, VX_cache__DOT__per_bank_dram_wb_req_byteen); - VL_RAND_RESET_W(224, VX_cache__DOT__per_bank_dram_wb_req_addr); - VL_RAND_RESET_W(1024, VX_cache__DOT__per_bank_dram_wb_req_data); - VX_cache__DOT__per_bank_snp_req_ready = VL_RAND_RESET_I(8); - VX_cache__DOT__per_bank_snp_rsp_valid = VL_RAND_RESET_I(8); - VL_RAND_RESET_W(224, VX_cache__DOT__per_bank_snp_rsp_tag); - VX_cache__DOT__per_bank_snp_rsp_ready = VL_RAND_RESET_I(8); - VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = VL_RAND_RESET_I(32); + VX_cache__DOT__per_bank_core_req_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_core_rsp_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_core_rsp_tid = VL_RAND_RESET_I(8); + VL_RAND_RESET_W(128, VX_cache__DOT__per_bank_core_rsp_data); + VL_RAND_RESET_W(168, VX_cache__DOT__per_bank_core_rsp_tag); + VX_cache__DOT__per_bank_core_rsp_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_fill_req_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_dram_fill_req_addr); + VX_cache__DOT__per_bank_dram_fill_rsp_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_wb_req_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_wb_req_valid = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_dram_wb_req_byteen = VL_RAND_RESET_Q(64); + VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_dram_wb_req_addr); + VL_RAND_RESET_W(512, VX_cache__DOT__per_bank_dram_wb_req_data); + VX_cache__DOT__per_bank_snp_req_ready = VL_RAND_RESET_I(4); + VX_cache__DOT__per_bank_snp_rsp_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__per_bank_snp_rsp_tag); + VX_cache__DOT__per_bank_snp_rsp_ready = VL_RAND_RESET_I(4); + VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid = VL_RAND_RESET_I(16); VL_RAND_RESET_W(128, VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data); VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); @@ -51702,85 +27045,63 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel = VL_RAND_RESET_I(4); VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank = VL_RAND_RESET_I(2); VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid = VL_RAND_RESET_I(2); VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr = VL_RAND_RESET_I(28); VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<2; ++__Vi0) { - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_I(28); - }} - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_I(28); - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_I(28); - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = VL_RAND_RESET_I(8); - VL_RAND_RESET_W(224, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid = VL_RAND_RESET_I(8); - VL_RAND_RESET_W(224, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr); - VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out); - VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r = VL_RAND_RESET_I(28); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid = VL_RAND_RESET_I(4); + VL_RAND_RESET_W(112, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr); + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out); + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vi0]); + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(232, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(116, VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(8); - VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = VL_RAND_RESET_I(3); + VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = VL_RAND_RESET_I(2); VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use = VL_RAND_RESET_I(8); - VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = VL_RAND_RESET_I(4); VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill = VL_RAND_RESET_I(1); - VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = VL_RAND_RESET_I(8); - VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank = VL_RAND_RESET_I(3); + VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank = VL_RAND_RESET_I(2); VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid = VL_RAND_RESET_I(1); - VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(8); + VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); @@ -51807,7 +27128,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); @@ -51830,7 +27151,7 @@ void VVX_cache::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); @@ -51846,8 +27167,8 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); @@ -51855,10 +27176,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); }} - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -51869,10 +27190,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -51891,23 +27212,23 @@ void VVX_cache::_ctor_var_reset() { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value); { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); }} @@ -51918,7 +27239,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); @@ -51926,31 +27247,31 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); }} - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); @@ -51963,18 +27284,18 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); @@ -51982,10 +27303,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); @@ -51993,11 +27314,11 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); @@ -52024,7 +27345,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); @@ -52047,7 +27368,7 @@ void VVX_cache::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); @@ -52063,8 +27384,8 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); @@ -52072,10 +27393,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); }} - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -52086,10 +27407,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -52108,23 +27429,23 @@ void VVX_cache::_ctor_var_reset() { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value); { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); }} @@ -52135,7 +27456,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); @@ -52143,31 +27464,31 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); }} - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); @@ -52180,18 +27501,18 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); @@ -52199,10 +27520,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); @@ -52210,11 +27531,11 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); @@ -52241,7 +27562,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); @@ -52264,7 +27585,7 @@ void VVX_cache::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); @@ -52280,8 +27601,8 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); @@ -52289,10 +27610,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); }} - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -52303,10 +27624,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -52325,23 +27646,23 @@ void VVX_cache::_ctor_var_reset() { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value); { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); }} @@ -52352,7 +27673,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); @@ -52360,31 +27681,31 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); }} - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); @@ -52397,18 +27718,18 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); @@ -52416,10 +27737,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); @@ -52427,11 +27748,11 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); @@ -52458,7 +27779,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(26); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); @@ -52481,7 +27802,7 @@ void VVX_cache::_ctor_var_reset() { { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); @@ -52497,8 +27818,8 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); @@ -52506,10 +27827,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(55); }} - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(55); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(55); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -52520,10 +27841,10 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(154, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); @@ -52542,23 +27863,23 @@ void VVX_cache::_ctor_var_reset() { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(243, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value); { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); }} @@ -52569,7 +27890,7 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(20); }} { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); @@ -52577,31 +27898,31 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(20); }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<64; ++__Vi0) { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); }} - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_Q(64); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_Q(64); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); + VL_RAND_RESET_W(166, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value); { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); + VL_RAND_RESET_W(416, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); @@ -52614,18 +27935,18 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(26); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(3); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { + { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); + VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); @@ -52633,884 +27954,16 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); + VL_RAND_RESET_W(200, VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); - }} - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__s0_1_c0__DOT__value); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); - }} - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); - }} - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); - }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); - }} - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); - }} - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); - }} - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); - }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); - }} - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); - }} - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); - }} - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); - }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 = VL_RAND_RESET_I(30); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2 = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[__Vi0] = VL_RAND_RESET_I(25); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[__Vi0] = VL_RAND_RESET_I(2); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[__Vi0] = VL_RAND_RESET_I(32); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[__Vi0] = VL_RAND_RESET_Q(49); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[__Vi0] = VL_RAND_RESET_I(1); - }} - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2 = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[__Vi0] = VL_RAND_RESET_Q(54); - }} - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r = VL_RAND_RESET_Q(54); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__size_r = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(153, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(120, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag = VL_RAND_RESET_Q(42); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(314, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(242, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value); - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[__Vi0] = VL_RAND_RESET_I(1); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[__Vi0] = VL_RAND_RESET_I(16); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<1; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[__Vi0]); - }} - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill = VL_RAND_RESET_I(1); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we = VL_RAND_RESET_I(16); - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(128, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[__Vi0]); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[__Vi0] = VL_RAND_RESET_I(21); - }} - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[__Vi0] = VL_RAND_RESET_I(16); - }} - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j = VL_RAND_RESET_I(32); - VL_RAND_RESET_W(167, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value); - VL_RAND_RESET_W(316, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value); - { int __Vi0=0; for (; __Vi0<16; ++__Vi0) { - VL_RAND_RESET_W(85, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[__Vi0]); - }} - VL_RAND_RESET_W(400, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size = VL_RAND_RESET_I(5); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match = VL_RAND_RESET_I(16); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1 = VL_RAND_RESET_I(25); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r = VL_RAND_RESET_I(4); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<8; ++__Vi0) { - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(76, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r = VL_RAND_RESET_I(3); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing = VL_RAND_RESET_I(1); - { int __Vi0=0; for (; __Vi0<4; ++__Vi0) { - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[__Vi0]); - }} - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r); - VL_RAND_RESET_W(199, VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r = VL_RAND_RESET_I(2); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r = VL_RAND_RESET_I(1); - VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r = VL_RAND_RESET_I(1); __Vtableidx1 = 0; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[0] = 0U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[1] = 0U; @@ -53528,246 +27981,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[13] = 0U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[14] = 1U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[15] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[17] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[18] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[19] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[20] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[21] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[22] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[23] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[24] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[25] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[26] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[27] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[28] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[29] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[30] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[31] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[32] = 5U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[33] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[34] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[35] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[36] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[37] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[38] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[39] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[40] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[41] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[42] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[43] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[44] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[45] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[46] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[47] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[48] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[49] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[50] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[51] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[52] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[53] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[54] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[55] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[56] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[57] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[58] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[59] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[60] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[61] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[62] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[63] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[64] = 6U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[65] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[66] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[67] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[68] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[69] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[70] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[71] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[72] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[73] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[74] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[75] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[76] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[77] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[78] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[79] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[80] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[81] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[82] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[83] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[84] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[85] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[86] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[87] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[88] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[89] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[90] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[91] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[92] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[93] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[94] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[95] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[96] = 5U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[97] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[98] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[99] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[100] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[101] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[102] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[103] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[104] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[105] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[106] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[107] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[108] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[109] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[110] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[111] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[112] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[113] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[114] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[115] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[116] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[117] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[118] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[119] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[120] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[121] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[122] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[123] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[124] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[125] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[126] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[127] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[128] = 7U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[129] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[130] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[131] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[132] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[133] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[134] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[135] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[136] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[137] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[138] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[139] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[140] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[141] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[142] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[143] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[144] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[145] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[146] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[147] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[148] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[149] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[150] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[151] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[152] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[153] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[154] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[155] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[156] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[157] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[158] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[159] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[160] = 5U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[161] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[162] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[163] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[164] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[165] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[166] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[167] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[168] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[169] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[170] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[171] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[172] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[173] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[174] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[175] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[176] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[177] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[178] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[179] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[180] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[181] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[182] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[183] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[184] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[185] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[186] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[187] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[188] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[189] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[190] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[191] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[192] = 6U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[193] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[194] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[195] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[196] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[197] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[198] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[199] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[200] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[201] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[202] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[203] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[204] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[205] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[206] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[207] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[208] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[209] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[210] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[211] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[212] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[213] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[214] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[215] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[216] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[217] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[218] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[219] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[220] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[221] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[222] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[223] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[224] = 5U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[225] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[226] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[227] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[228] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[229] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[230] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[231] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[232] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[233] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[234] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[235] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[236] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[237] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[238] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[239] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[240] = 4U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[241] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[242] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[243] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[244] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[245] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[246] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[247] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[248] = 3U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[249] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[250] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[251] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[252] = 2U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[253] = 0U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[254] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[255] = 0U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[0] = 0U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[1] = 1U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[2] = 1U; @@ -53784,246 +27997,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[13] = 1U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[14] = 1U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[15] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[17] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[18] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[19] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[20] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[21] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[22] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[23] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[24] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[25] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[26] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[27] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[28] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[29] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[30] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[31] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[32] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[33] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[34] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[35] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[36] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[37] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[38] = 1U; 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- __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[205] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[206] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[207] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[208] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[209] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[210] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[211] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[212] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[213] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[214] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[215] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[216] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[217] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[218] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[219] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[220] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[221] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[222] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[223] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[224] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[225] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[226] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[227] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[228] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[229] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[230] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[231] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[232] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[233] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[234] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[235] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[236] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[237] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[238] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[239] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[240] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[241] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[242] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[243] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[244] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[245] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[246] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[247] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[248] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[249] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[250] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[251] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[252] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[253] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[254] = 1U; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[255] = 1U; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; @@ -54040,246 +28013,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; - __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; __Vtableidx2 = 0; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[0] = 0U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[1] = 0U; @@ -54297,246 +28030,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[13] = 0U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[14] = 1U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[15] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[17] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[18] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[19] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[20] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[21] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[22] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[23] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[24] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[25] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[26] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[27] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[28] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[29] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[30] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[31] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[32] = 5U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[33] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[34] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[35] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[36] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[37] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[38] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[39] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[40] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[41] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[42] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[43] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[44] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[45] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[46] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[47] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[48] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[49] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[50] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[51] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[52] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[53] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[54] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[55] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[56] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[57] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[58] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[59] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[60] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[61] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[62] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[63] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[64] = 6U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[65] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[66] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[67] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[68] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[69] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[70] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[71] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[72] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[73] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[74] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[75] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[76] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[77] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[78] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[79] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[80] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[81] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[82] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[83] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[84] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[85] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[86] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[87] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[88] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[89] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[90] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[91] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[92] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[93] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[94] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[95] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[96] = 5U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[97] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[98] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[99] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[100] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[101] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[102] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[103] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[104] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[105] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[106] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[107] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[108] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[109] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[110] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[111] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[112] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[113] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[114] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[115] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[116] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[117] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[118] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[119] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[120] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[121] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[122] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[123] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[124] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[125] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[126] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[127] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[128] = 7U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[129] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[130] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[131] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[132] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[133] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[134] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[135] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[136] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[137] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[138] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[139] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[140] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[141] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[142] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[143] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[144] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[145] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[146] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[147] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[148] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[149] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[150] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[151] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[152] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[153] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[154] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[155] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[156] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[157] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[158] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[159] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[160] = 5U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[161] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[162] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[163] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[164] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[165] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[166] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[167] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[168] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[169] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[170] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[171] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[172] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[173] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[174] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[175] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[176] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[177] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[178] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[179] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[180] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[181] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[182] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[183] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[184] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[185] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[186] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[187] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[188] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[189] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[190] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[191] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[192] = 6U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[193] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[194] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[195] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[196] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[197] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[198] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[199] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[200] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[201] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[202] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[203] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[204] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[205] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[206] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[207] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[208] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[209] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[210] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[211] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[212] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[213] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[214] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[215] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[216] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[217] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[218] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[219] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[220] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[221] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[222] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[223] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[224] = 5U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[225] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[226] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[227] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[228] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[229] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[230] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[231] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[232] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[233] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[234] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[235] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[236] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[237] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[238] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[239] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[240] = 4U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[241] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[242] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[243] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[244] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[245] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[246] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[247] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[248] = 3U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[249] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[250] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[251] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[252] = 2U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[253] = 0U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[254] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[255] = 0U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[0] = 0U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[1] = 1U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[2] = 1U; @@ -54553,246 +28046,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[13] = 1U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[14] = 1U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[15] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[17] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[18] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[19] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[20] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[21] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[22] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[23] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[24] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[25] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[26] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[27] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[28] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[29] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[30] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[31] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[32] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[33] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[34] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[35] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[36] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[37] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[38] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[39] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[40] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[41] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[42] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[43] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[44] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[45] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[46] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[47] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[48] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[49] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[50] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[51] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[52] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[53] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[54] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[55] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[56] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[57] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[58] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[59] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[60] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[61] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[62] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[63] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[64] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[65] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[66] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[67] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[68] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[69] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[70] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[71] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[72] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[73] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[74] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[75] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[76] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[77] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[78] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[79] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[80] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[81] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[82] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[83] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[84] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[85] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[86] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[87] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[88] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[89] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[90] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[91] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[92] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[93] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[94] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[95] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[96] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[97] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[98] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[99] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[100] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[101] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[102] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[103] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[104] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[105] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[106] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[107] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[108] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[109] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[110] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[111] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[112] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[113] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[114] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[115] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[116] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[117] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[118] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[119] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[120] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[121] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[122] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[123] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[124] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[125] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[126] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[127] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[128] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[129] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[130] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[131] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[132] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[133] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[134] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[135] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[136] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[137] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[138] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[139] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[140] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[141] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[142] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[143] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[144] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[145] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[146] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[147] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[148] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[149] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[150] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[151] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[152] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[153] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[154] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[155] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[156] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[157] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[158] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[159] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[160] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[161] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[162] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[163] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[164] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[165] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[166] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[167] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[168] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[169] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[170] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[171] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[172] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[173] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[174] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[175] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[176] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[177] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[178] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[179] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[180] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[181] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[182] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[183] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[184] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[185] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[186] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[187] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[188] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[189] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[190] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[191] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[192] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[193] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[194] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[195] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[196] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[197] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[198] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[199] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[200] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[201] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[202] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[203] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[204] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[205] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[206] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[207] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[208] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[209] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[210] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[211] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[212] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[213] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[214] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[215] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[216] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[217] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[218] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[219] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[220] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[221] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[222] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[223] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[224] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[225] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[226] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[227] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[228] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[229] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[230] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[231] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[232] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[233] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[234] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[235] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[236] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[237] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[238] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[239] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[240] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[241] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[242] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[243] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[244] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[245] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[246] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[247] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[248] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[249] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[250] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[251] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[252] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[253] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[254] = 1U; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[255] = 1U; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; @@ -54809,246 +28062,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; - __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; __Vtableidx3 = 0; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[0] = 0U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[1] = 0U; @@ -55066,246 +28079,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[13] = 0U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[14] = 1U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[15] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[17] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[18] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[19] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[20] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[21] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[22] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[23] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[24] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[25] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[26] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[27] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[28] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[29] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[30] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[31] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[32] = 5U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[33] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[34] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[35] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[36] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[37] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[38] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[39] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[40] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[41] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[42] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[43] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[44] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[45] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[46] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[47] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[48] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[49] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[50] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[51] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[52] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[53] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[54] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[55] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[56] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[57] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[58] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[59] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[60] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[61] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[62] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[63] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[64] = 6U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[65] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[66] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[67] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[68] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[69] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[70] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[71] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[72] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[73] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[74] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[75] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[76] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[77] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[78] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[79] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[80] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[81] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[82] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[83] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[84] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[85] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[86] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[87] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[88] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[89] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[90] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[91] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[92] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[93] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[94] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[95] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[96] = 5U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[97] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[98] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[99] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[100] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[101] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[102] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[103] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[104] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[105] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[106] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[107] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[108] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[109] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[110] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[111] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[112] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[113] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[114] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[115] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[116] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[117] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[118] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[119] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[120] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[121] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[122] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[123] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[124] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[125] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[126] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[127] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[128] = 7U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[129] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[130] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[131] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[132] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[133] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[134] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[135] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[136] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[137] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[138] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[139] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[140] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[141] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[142] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[143] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[144] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[145] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[146] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[147] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[148] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[149] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[150] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[151] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[152] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[153] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[154] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[155] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[156] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[157] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[158] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[159] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[160] = 5U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[161] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[162] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[163] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[164] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[165] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[166] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[167] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[168] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[169] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[170] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[171] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[172] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[173] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[174] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[175] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[176] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[177] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[178] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[179] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[180] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[181] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[182] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[183] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[184] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[185] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[186] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[187] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[188] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[189] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[190] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[191] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[192] = 6U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[193] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[194] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[195] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[196] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[197] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[198] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[199] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[200] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[201] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[202] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[203] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[204] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[205] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[206] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[207] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[208] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[209] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[210] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[211] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[212] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[213] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[214] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[215] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[216] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[217] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[218] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[219] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[220] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[221] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[222] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[223] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[224] = 5U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[225] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[226] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[227] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[228] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[229] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[230] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[231] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[232] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[233] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[234] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[235] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[236] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[237] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[238] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[239] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[240] = 4U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[241] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[242] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[243] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[244] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[245] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[246] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[247] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[248] = 3U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[249] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[250] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[251] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[252] = 2U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[253] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[254] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[255] = 0U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[0] = 0U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[1] = 1U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[2] = 1U; @@ -55322,246 +28095,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[13] = 1U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[14] = 1U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[15] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[17] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[18] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[19] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[20] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[21] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[22] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[23] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[24] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[25] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[26] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[27] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[28] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[29] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[30] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[31] = 1U; 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- __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[219] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[220] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[221] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[222] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[223] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[224] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[225] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[226] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[227] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[228] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[229] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[230] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[231] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[232] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[233] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[234] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[235] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[236] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[237] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[238] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[239] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[240] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[241] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[242] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[243] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[244] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[245] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[246] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[247] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[248] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[249] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[250] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[251] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[252] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[253] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[254] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[255] = 1U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; @@ -55578,246 +28111,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; __Vtableidx4 = 0; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[0] = 0U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[1] = 0U; @@ -55835,246 +28128,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[13] = 0U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[14] = 1U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[15] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[17] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[18] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[19] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[20] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[21] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[22] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[23] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[24] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[25] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[26] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[27] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[28] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[29] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[30] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[31] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[32] = 5U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[33] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[34] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[35] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[36] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[37] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[38] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[39] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[40] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[41] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[42] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[43] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[44] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[45] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[46] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[47] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[48] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[49] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[50] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[51] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[52] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[53] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[54] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[55] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[56] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[57] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[58] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[59] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[60] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[61] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[62] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[63] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[64] = 6U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[65] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[66] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[67] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[68] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[69] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[70] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[71] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[72] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[73] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[74] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[75] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[76] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[77] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[78] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[79] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[80] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[81] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[82] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[83] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[84] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[85] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[86] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[87] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[88] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[89] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[90] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[91] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[92] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[93] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[94] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[95] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[96] = 5U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[97] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[98] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[99] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[100] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[101] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[102] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[103] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[104] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[105] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[106] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[107] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[108] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[109] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[110] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[111] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[112] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[113] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[114] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[115] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[116] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[117] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[118] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[119] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[120] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[121] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[122] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[123] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[124] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[125] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[126] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[127] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[128] = 7U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[129] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[130] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[131] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[132] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[133] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[134] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[135] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[136] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[137] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[138] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[139] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[140] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[141] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[142] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[143] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[144] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[145] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[146] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[147] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[148] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[149] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[150] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[151] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[152] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[153] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[154] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[155] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[156] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[157] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[158] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[159] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[160] = 5U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[161] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[162] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[163] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[164] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[165] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[166] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[167] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[168] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[169] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[170] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[171] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[172] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[173] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[174] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[175] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[176] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[177] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[178] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[179] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[180] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[181] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[182] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[183] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[184] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[185] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[186] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[187] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[188] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[189] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[190] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[191] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[192] = 6U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[193] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[194] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[195] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[196] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[197] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[198] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[199] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[200] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[201] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[202] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[203] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[204] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[205] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[206] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[207] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[208] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[209] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[210] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[211] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[212] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[213] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[214] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[215] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[216] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[217] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[218] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[219] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[220] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[221] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[222] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[223] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[224] = 5U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[225] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[226] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[227] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[228] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[229] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[230] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[231] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[232] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[233] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[234] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[235] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[236] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[237] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[238] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[239] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[240] = 4U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[241] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[242] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[243] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[244] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[245] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[246] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[247] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[248] = 3U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[249] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[250] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[251] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[252] = 2U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[253] = 0U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[254] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[255] = 0U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[0] = 0U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[1] = 1U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[2] = 1U; @@ -56091,246 +28144,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[13] = 1U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[14] = 1U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[15] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[17] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[18] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[19] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[20] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[21] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[22] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[23] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[24] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[25] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[26] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[27] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[28] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[29] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[30] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[31] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[32] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[33] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[34] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[35] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[36] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[37] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[38] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[39] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[40] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[41] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[42] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[43] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[44] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[45] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[46] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[47] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[48] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[49] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[50] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[51] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[52] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[53] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[54] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[55] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[56] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[57] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[58] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[59] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[60] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[61] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[62] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[63] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[64] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[65] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[66] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[67] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[68] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[69] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[70] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[71] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[72] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[73] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[74] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[75] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[76] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[77] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[78] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[79] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[80] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[81] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[82] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[83] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[84] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[85] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[86] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[87] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[88] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[89] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[90] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[91] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[92] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[93] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[94] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[95] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[96] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[97] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[98] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[99] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[100] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[101] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[102] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[103] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[104] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[105] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[106] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[107] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[108] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[109] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[110] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[111] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[112] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[113] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[114] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[115] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[116] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[117] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[118] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[119] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[120] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[121] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[122] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[123] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[124] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[125] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[126] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[127] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[128] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[129] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[130] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[131] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[132] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[133] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[134] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[135] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[136] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[137] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[138] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[139] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[140] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[141] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[142] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[143] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[144] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[145] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[146] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[147] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[148] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[149] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[150] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[151] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[152] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[153] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[154] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[155] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[156] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[157] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[158] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[159] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[160] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[161] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[162] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[163] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[164] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[165] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[166] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[167] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[168] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[169] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[170] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[171] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[172] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[173] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[174] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[175] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[176] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[177] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[178] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[179] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[180] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[181] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[182] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[183] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[184] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[185] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[186] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[187] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[188] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[189] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[190] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[191] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[192] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[193] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[194] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[195] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[196] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[197] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[198] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[199] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[200] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[201] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[202] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[203] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[204] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[205] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[206] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[207] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[208] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[209] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[210] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[211] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[212] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[213] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[214] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[215] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[216] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[217] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[218] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[219] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[220] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[221] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[222] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[223] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[224] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[225] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[226] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[227] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[228] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[229] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[230] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[231] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[232] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[233] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[234] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[235] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[236] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[237] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[238] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[239] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[240] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[241] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[242] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[243] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[244] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[245] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[246] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[247] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[248] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[249] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[250] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[251] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[252] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[253] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[254] = 1U; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[255] = 1U; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; @@ -56347,246 +28160,6 @@ void VVX_cache::_ctor_var_reset() { __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[17] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[18] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[19] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[20] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[21] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[22] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[23] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[24] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[25] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[26] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[27] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[28] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[29] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[30] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[31] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[32] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[33] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[34] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[35] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[36] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[37] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[38] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[39] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[40] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[41] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[42] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[43] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[44] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[45] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[46] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[47] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[48] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[49] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[50] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[51] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[52] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[53] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[54] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[55] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[56] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[57] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[58] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[59] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[60] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[61] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[62] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[63] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[64] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[65] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[66] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[67] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[68] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[69] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[70] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[71] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[72] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[73] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[74] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[75] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[76] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[77] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[78] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[79] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[80] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[81] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[82] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[83] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[84] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[85] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[86] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[87] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[88] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[89] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[90] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[91] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[92] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[93] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[94] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[95] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[96] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[97] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[98] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[99] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[100] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[101] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[102] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[103] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[104] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[105] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[106] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[107] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[108] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[109] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[110] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[111] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[112] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[113] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[114] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[115] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[116] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[117] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[118] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[119] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[120] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[121] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[122] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[123] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[124] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[125] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[126] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[127] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[128] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[129] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[130] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[131] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[132] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[133] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[134] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[135] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[136] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[137] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[138] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[139] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[140] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[141] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[142] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[143] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[144] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[145] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[146] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[147] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[148] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[149] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[150] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[151] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[152] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[153] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[154] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[155] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[156] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[157] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[158] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[159] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[160] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[161] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[162] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[163] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[164] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[165] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[166] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[167] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[168] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[169] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[170] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[171] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[172] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[173] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[174] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[175] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[176] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[177] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[178] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[179] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[180] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[181] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[182] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[183] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[184] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[185] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[186] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[187] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[188] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[189] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[190] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[191] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[192] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[193] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[194] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[195] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[196] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[197] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[198] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[199] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[200] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[201] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[202] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[203] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[204] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[205] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[206] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[207] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[208] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[209] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[210] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[211] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[212] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[213] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[214] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[215] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[216] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[217] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[218] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[219] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[220] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[221] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[222] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[223] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[224] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[225] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[226] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[227] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[228] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[229] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[230] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[231] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[232] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[233] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[234] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[235] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[236] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[237] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[238] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[239] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[240] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[241] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[242] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[243] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[244] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[245] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[246] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[247] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[248] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[249] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[250] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[251] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[252] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[253] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[254] = 0xffffffffU; - __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[255] = 0xffffffffU; __Vtableidx5 = 0; __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; @@ -56783,201 +28356,5 @@ void VVX_cache::_ctor_var_reset() { __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; - __Vtableidx9 = 0; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; - __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; 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- __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; - __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; 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- __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; - __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; - __Vtableidx12 = 0; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[0] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[1] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[2] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[3] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[4] = 2U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[5] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[6] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[7] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[8] = 3U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[9] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[10] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[11] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[12] = 2U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[13] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[14] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[15] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[0] = 0U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[1] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[2] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[3] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[4] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[5] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[6] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[7] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[8] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[9] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[10] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[11] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[12] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[13] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[14] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[15] = 1U; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[3] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[4] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[5] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[6] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[7] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[8] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[9] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[10] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[11] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[12] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[13] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[14] = 0xffffffffU; - __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[15] = 0xffffffffU; __Vm_traceActivity = 0; } diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.h b/hw/unit_tests/cache/obj_dir/VVX_cache.h index 3fe788ef..8661c1ff 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache.h +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.h @@ -69,17 +69,17 @@ VL_MODULE(VVX_cache) { // Internals; generally not touched by application code // Anonymous structures to workaround compiler member-count bugs struct { - CData/*7:0*/ VX_cache__DOT__per_bank_core_req_ready; - CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_valid; - SData/*15:0*/ VX_cache__DOT__per_bank_core_rsp_tid; - CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_ready; - CData/*7:0*/ VX_cache__DOT__per_bank_dram_fill_req_valid; - CData/*7:0*/ VX_cache__DOT__per_bank_dram_fill_rsp_ready; - CData/*7:0*/ VX_cache__DOT__per_bank_dram_wb_req_ready; - CData/*7:0*/ VX_cache__DOT__per_bank_dram_wb_req_valid; - CData/*7:0*/ VX_cache__DOT__per_bank_snp_req_ready; - CData/*7:0*/ VX_cache__DOT__per_bank_snp_rsp_valid; - CData/*7:0*/ VX_cache__DOT__per_bank_snp_rsp_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_core_req_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_valid; + CData/*7:0*/ VX_cache__DOT__per_bank_core_rsp_tid; + CData/*3:0*/ VX_cache__DOT__per_bank_core_rsp_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_req_valid; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_fill_rsp_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_dram_wb_req_valid; + CData/*3:0*/ VX_cache__DOT__per_bank_snp_req_ready; + CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_valid; + CData/*3:0*/ VX_cache__DOT__per_bank_snp_rsp_ready; CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid; @@ -92,67 +92,49 @@ VL_MODULE(VVX_cache) { CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid; - CData/*7:0*/ VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel; + CData/*3:0*/ VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop; - CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank; CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing; - CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; - CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; - CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid; - CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; - CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request; - CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; - }; - struct { - CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; - CData/*7:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r; - CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual; - CData/*2:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; + CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual; + CData/*1:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index; CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid; - CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; - CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value; CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill; - CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original; - CData/*7:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; - CData/*2:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; + CData/*1:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank; CData/*0:0*/ VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid; - CData/*7:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r; + CData/*3:0*/ VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop; + }; + struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2; @@ -199,26 +181,26 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids; - }; - struct { CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match; + }; + struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write; @@ -232,12 +214,12 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; @@ -265,8 +247,6 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual; - }; - struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e; @@ -285,6 +265,8 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel; CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; + }; + struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing; CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; @@ -309,12 +291,12 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; @@ -331,17 +313,15 @@ VL_MODULE(VVX_cache) { CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr; CData/*4:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible; - }; - struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; @@ -351,6 +331,8 @@ VL_MODULE(VVX_cache) { CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + }; + struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; @@ -397,8 +379,6 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; CData/*4:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading; - }; - struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing; CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; @@ -413,12 +393,14 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + }; + struct { + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; @@ -438,12 +420,12 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; @@ -463,8 +445,6 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e; - }; - struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall; @@ -483,6 +463,8 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq; + }; + struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in; @@ -515,12 +497,12 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; @@ -529,8 +511,6 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we; - }; - struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss; @@ -542,13 +522,15 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; + CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; + CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; + }; + struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; CData/*2:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r; @@ -560,674 +542,144 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel; - CData/*4:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing; - }; - struct { - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r; - CData/*3:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; - CData/*4:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r; 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QData/*41:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; + }; + struct { + QData/*63:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty; + QData/*63:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; QData/*41:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; + QData/*63:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty; + QData/*63:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; QData/*41:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; - QData/*41:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; - QData/*41:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; - QData/*41:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r; - QData/*41:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag; - IData/*27:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[2]; - WData/*231:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[8][8]; + QData/*63:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty; + QData/*63:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid; + WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[4][4]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[1]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[1]; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[1]; IData/*31:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[1]; QData/*48:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[1]; @@ -1235,51 +687,51 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; WData/*84:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[1]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[1]; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[1]; IData/*31:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[1]; - }; - struct { QData/*48:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[1]; WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[1][4]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; WData/*84:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[1]; + }; + struct { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[1]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[1]; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[1]; IData/*31:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[1]; QData/*48:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[1]; @@ -1287,24 +739,24 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; WData/*84:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[1]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[1]; CData/*1:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[1]; IData/*31:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[1]; QData/*48:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[1]; @@ -1312,277 +764,111 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; + WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4][10]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; CData/*0:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - }; - struct { - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; + WData/*127:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[64][4]; + IData/*19:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[64]; + SData/*15:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[64]; WData/*84:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[1]; - CData/*1:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[1]; - IData/*31:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[1]; - QData/*48:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[1][4]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; - WData/*84:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[1]; - CData/*1:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[1]; - IData/*31:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[1]; - QData/*48:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[1][4]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; - WData/*84:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[1]; - CData/*1:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[1]; - IData/*31:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[1]; - QData/*48:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[1][4]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[1]; - }; - struct { - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; - WData/*84:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[1]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[1]; - CData/*1:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[1]; - IData/*31:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[1]; - QData/*48:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[1][4]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[1]; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[16]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[16][5]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[8][10]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[1]; - CData/*0:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[1]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[1]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[1]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[1][4]; - WData/*127:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data[16][4]; - IData/*20:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[16]; - SData/*15:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb[16]; - WData/*84:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[16][3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[8][3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; + WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4][3]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[4][7]; }; // LOCAL VARIABLES // Internals; generally not touched by application code // Anonymous structures to workaround compiler member-count bugs struct { - IData/*31:0*/ VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid; - CData/*7:0*/ __Vtableidx1; - CData/*7:0*/ __Vtableidx2; - CData/*7:0*/ __Vtableidx3; - CData/*7:0*/ __Vtableidx4; + SData/*15:0*/ VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid; + CData/*3:0*/ __Vtableidx1; + CData/*3:0*/ __Vtableidx2; + CData/*3:0*/ __Vtableidx3; + CData/*3:0*/ __Vtableidx4; CData/*3:0*/ __Vtableidx5; CData/*3:0*/ __Vtableidx6; CData/*3:0*/ __Vtableidx7; CData/*3:0*/ __Vtableidx8; - CData/*3:0*/ __Vtableidx9; - CData/*3:0*/ __Vtableidx10; - CData/*3:0*/ __Vtableidx11; - CData/*3:0*/ __Vtableidx12; CData/*0:0*/ __Vclklast__TOP__clk; WData/*127:0*/ VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[4]; - WData/*231:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[8]; - WData/*231:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[8]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; - WData/*241:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4]; + WData/*115:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in[4]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; WData/*315:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; - WData/*166:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; - WData/*241:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; WData/*315:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; - WData/*166:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; - WData/*241:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; WData/*315:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; - WData/*166:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; - WData/*241:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; + WData/*153:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; + WData/*242:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; WData/*315:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; WData/*75:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; + WData/*199:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; WData/*313:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; - WData/*166:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; - }; - struct { - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; 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- IData/*24:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; - WData/*241:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; - WData/*315:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; - WData/*166:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; - WData/*241:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; - WData/*315:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; - WData/*166:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[5]; - WData/*152:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in[5]; - WData/*241:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in[8]; - WData/*315:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in[10]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[3]; - WData/*75:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in[3]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[7]; - WData/*198:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in[7]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[10]; - WData/*313:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in[10]; - WData/*166:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; - IData/*24:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; + WData/*165:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in[6]; + IData/*25:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT____Vlvbound1; IData/*31:0*/ __Vm_traceActivity; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; }; struct { - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; - QData/*53:0*/ VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out; + QData/*54:0*/ VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in; }; - static CData/*2:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[256]; - static CData/*0:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[256]; - static IData/*31:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; - static CData/*2:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[256]; - static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[256]; - static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; - static CData/*2:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[256]; - static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[256]; - static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; - static CData/*2:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[256]; - static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[256]; - static IData/*31:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[256]; + static CData/*1:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index[16]; + static CData/*0:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request[16]; + static IData/*31:0*/ __Vtable1_VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank[16]; + static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16]; + static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16]; + static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16]; + static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; + static CData/*1:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16]; + static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16]; + static IData/*31:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; static CData/*1:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; static CData/*0:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; static IData/*31:0*/ __Vtable5_VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; @@ -1595,18 +881,6 @@ VL_MODULE(VVX_cache) { static CData/*1:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; static CData/*0:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; static IData/*31:0*/ __Vtable8_VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; - static CData/*1:0*/ __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; - static CData/*0:0*/ __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; - static IData/*31:0*/ __Vtable9_VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; - static CData/*1:0*/ __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; - static CData/*0:0*/ __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; - static IData/*31:0*/ __Vtable10_VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; - static CData/*1:0*/ __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; - static CData/*0:0*/ __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; - static IData/*31:0*/ __Vtable11_VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; - static CData/*1:0*/ __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index[16]; - static CData/*0:0*/ __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request[16]; - static IData/*31:0*/ __Vtable12_VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; // INTERNAL VARIABLES // Internals; generally not touched by application code diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.mk b/hw/unit_tests/cache/obj_dir/VVX_cache.mk index a7ab278e..2d37632a 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache.mk +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.mk @@ -33,14 +33,15 @@ VM_PREFIX = VVX_cache VM_MODPREFIX = VVX_cache # User CFLAGS (from -CFLAGS on Verilator command line) VM_USER_CFLAGS = \ - -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DWORD_SIZE=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \ + -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 \ # User LDLIBS (from -LDFLAGS on Verilator command line) VM_USER_LDLIBS = \ # User .cpp files (from .cpp's on Verilator command line) VM_USER_CLASSES = \ - cache_sim \ + cachesim \ + testbench \ # User .cpp directories (from .cpp's on Verilator command line) VM_USER_DIR = \ @@ -56,7 +57,9 @@ include $(VERILATOR_ROOT)/include/verilated.mk ### Executable rules... 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zHT=9{|ncG{HE*q{r~4V9%t71 z(_ytc80H<+J2|?mC(N6i z;$nI^$2fgX^8I5q`XA~^<)iavR+bB^q@vPTSoj%Y}J?^-5+4h zdt(ocu3-_m58=GD zn^}%`e%?Ol@$KE?v$!9fe&^@@gC5_-J&wm$eu(3HxX1JSo!<){v_IK$ymJl@di)5> z@y_oV4|@DW%kj?dBM*A~G|TZd9^&|Umg8$a#PQ24$Jcs@<2P82ul*3m?{tsn^Hb*` zj^ATB{@I5({;=iv=N{ttRQGs3zs~Os!S_GZXUHFyPyFcAs^?0rY^#;D+{yGu(tEZgr zGbi)^dc3pOz4Lc|$-pbn&)=DyF9-LB`|RHN2OZz#&|~+~0_W-UIKRIJpMNKxIhjF+ zd$Kg}U-uIg?*B^Qc;6xSUh%$v+V;QT^<3N_eIR`}+gm$AKM!`&WwNQ{3a7=Zml4<5PWKwDsR~k9YRtEBN>yeP6Vl|0MVPE4T+c z_bfB&68vHLN&zntj5 zZ0QfR^mi2fBL?{UqkLcIE4V*W^oJhyfB*3M7qj$_6aA?J{rx>y?)yBr|5ef7((MmC z=g$2vZt4F-^fw;l?;rO!{fk6@4@kXiZO3aeTHR{{4f0Hx52NK^$Mi zJ-%q5*!>uM{B-yDV1Ld%KGeCmcm@5{v%)<-Lr_4Mq5k~?&r2X8`0q=6$JyS0mRYX9 z^Su~2KJb0@tko!pW+@L?1AF~e%n3X_u;8o)P}*Kk!lKZyt~H xySwx6Pr=7KUk?7=#YdjT6a2^T3mo8}?-hLh&hu$I{^pPV_s{G>UkpC}e*h<4!ZQE> literal 0 HcmV?d00001 diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp index 35a510dc..3bb16217 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.cpp @@ -22,8 +22,6 @@ VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep) // Setup scopes __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue", "dfqq_queue", VerilatedScope::SCOPE_OTHER); __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.dram_fill_arb.dfqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue", "pfq_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.cache_dram_req_arb.prfqq.pfq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[0].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[0].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); @@ -64,44 +62,4 @@ VVX_cache__Syms::VVX_cache__Syms(VVX_cache* topp, const char* namep) __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[3].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[4].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[5].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[6].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue", "reqq_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.core_req_arb.reqq_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue", "cwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.cwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue", "dfp_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dfp_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue", "dwb_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.dwb_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue", "snp_req_queue", VerilatedScope::SCOPE_OTHER); - __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2.configure(this, name(), "VX_cache.genblk5[7].bank.snp_req_queue.genblk3.genblk2", "genblk2", VerilatedScope::SCOPE_OTHER); } diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h index b6041fd0..c6de6125 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Syms.h @@ -27,8 +27,6 @@ class VVX_cache__Syms : public VerilatedSyms { // SCOPE NAMES VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue; VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__dram_fill_arb__dfqq_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue; - VerilatedScope __Vscope_VX_cache__cache_dram_req_arb__prfqq__pfq_queue__genblk3__genblk2; VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue; VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; VerilatedScope __Vscope_VX_cache__genblk5__BRA__0__KET____bank__cwb_queue; @@ -69,46 +67,6 @@ class VVX_cache__Syms : public VerilatedSyms { VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__dwb_queue__genblk3__genblk2; VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue; VerilatedScope __Vscope_VX_cache__genblk5__BRA__3__KET____bank__snp_req_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__cwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dfp_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__dwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__4__KET____bank__snp_req_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__cwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dfp_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__dwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__5__KET____bank__snp_req_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__cwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dfp_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__dwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__6__KET____bank__snp_req_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__core_req_arb__reqq_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__cwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dfp_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__dwb_queue__genblk3__genblk2; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue; - VerilatedScope __Vscope_VX_cache__genblk5__BRA__7__KET____bank__snp_req_queue__genblk3__genblk2; // CREATORS VVX_cache__Syms(VVX_cache* topp, const char* namep); diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp index 956c0c84..bba93d74 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp @@ -55,10 +55,10 @@ void VVX_cache::traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc if (0 && vcdp && c) {} // Prevent unused // Body { - vcdp->chgBus(c+1,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid),32); - vcdp->chgBus(c+9,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready),8); - vcdp->chgBus(c+17,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready),8); - vcdp->chgBus(c+25,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready),8); + vcdp->chgBus(c+1,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid),16); + vcdp->chgBus(c+9,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready),4); + vcdp->chgBus(c+17,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready),4); + vcdp->chgBus(c+25,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready),4); vcdp->chgBus(c+33,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid),4); vcdp->chgBit(c+41,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)))); vcdp->chgBit(c+49,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)))); @@ -84,117 +84,49 @@ void VVX_cache::traceChgThis__2(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc >> 3U)))); vcdp->chgBit(c+153,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) >> 3U)))); - vcdp->chgBus(c+161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid),4); - vcdp->chgBit(c+169,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 4U)))); - vcdp->chgBit(c+177,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 4U)))); - vcdp->chgBit(c+185,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 4U)))); - vcdp->chgBus(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid),4); - vcdp->chgBit(c+201,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 5U)))); - vcdp->chgBit(c+209,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 5U)))); - vcdp->chgBit(c+217,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 5U)))); - vcdp->chgBus(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid),4); - vcdp->chgBit(c+233,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 6U)))); - vcdp->chgBit(c+241,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 6U)))); - vcdp->chgBit(c+249,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 6U)))); - vcdp->chgBus(c+257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid),4); - vcdp->chgBit(c+265,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 7U)))); - vcdp->chgBit(c+273,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 7U)))); - vcdp->chgBit(c+281,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 7U)))); - vcdp->chgBus(c+289,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),8); - vcdp->chgBit(c+297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); - vcdp->chgBit(c+305,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); - vcdp->chgBit(c+313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+401,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->chgBit(c+505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->chgBit(c+697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->chgBit(c+889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+1057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+1065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+1073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->chgBit(c+1081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+1089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+1097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+1113,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+1121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+1161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+1169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+1249,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+1257,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+1265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->chgBit(c+1273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+1281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+1289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+1305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+1313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+1353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+1361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+1441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+1449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+1457,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->chgBit(c+1465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+1473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+1497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+1505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+1545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+1553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+1633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+1641,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+1649,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->chgBit(c+1657,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->chgBit(c+1665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->chgQuad(c+1673,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->chgBit(c+1689,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->chgArray(c+1697,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->chgBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->chgArray(c+1745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->chgBit(c+1825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->chgBit(c+1833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->chgBit(c+1841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBus(c+161,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),4); + vcdp->chgBit(c+169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); + vcdp->chgBit(c+177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); + vcdp->chgBit(c+185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+201,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+265,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+361,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->chgBit(c+761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->chgBit(c+769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->chgQuad(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->chgBit(c+793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->chgArray(c+801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->chgBit(c+841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->chgArray(c+849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->chgBit(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->chgBit(c+937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->chgBit(c+945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); } } @@ -204,172 +136,92 @@ void VVX_cache::traceChgThis__3(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc if (0 && vcdp && c) {} // Prevent unused // Body { - vcdp->chgBit(c+1849,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) - & (~ ((~ (IData)((0U - != - (0xffU - & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) - | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); - vcdp->chgBit(c+1857,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1865,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); - vcdp->chgBit(c+1873,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + vcdp->chgBit(c+953,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U != + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); + vcdp->chgBit(c+961,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+969,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); + vcdp->chgBit(c+977,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+1881,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1889,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1897,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->chgBit(c+985,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+993,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+1001,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 1U))))); - vcdp->chgBit(c+1905,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) + vcdp->chgBit(c+1009,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+1913,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + vcdp->chgBit(c+1017,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1921,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + vcdp->chgBit(c+1025,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1929,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + vcdp->chgBit(c+1033,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 2U))))); - vcdp->chgBit(c+1937,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) + vcdp->chgBit(c+1041,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+1945,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + vcdp->chgBit(c+1049,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1953,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + vcdp->chgBit(c+1057,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1961,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + vcdp->chgBit(c+1065,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 3U))))); - vcdp->chgBit(c+1969,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) + vcdp->chgBit(c+1073,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+1977,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + vcdp->chgBit(c+1081,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1985,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+1993,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 4U))))); - vcdp->chgBit(c+2001,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+2009,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+2017,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+2025,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 5U))))); - vcdp->chgBit(c+2033,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+2041,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+2049,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+2057,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 6U))))); - vcdp->chgBit(c+2065,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+2073,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+2081,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+2089,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 7U))))); - vcdp->chgBit(c+2097,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->chgBit(c+2105,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); } } @@ -378,105 +230,69 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc int c = code; if (0 && vcdp && c) {} // Prevent unused // Variables - WData/*127:0*/ __Vtemp1366[4]; - WData/*127:0*/ __Vtemp1385[4]; - WData/*127:0*/ __Vtemp1404[4]; - WData/*127:0*/ __Vtemp1423[4]; - WData/*127:0*/ __Vtemp1442[4]; - WData/*127:0*/ __Vtemp1461[4]; - WData/*127:0*/ __Vtemp1480[4]; - WData/*127:0*/ __Vtemp1499[4]; - WData/*127:0*/ __Vtemp1339[4]; - WData/*127:0*/ __Vtemp1340[4]; - WData/*127:0*/ __Vtemp1341[4]; - WData/*127:0*/ __Vtemp1342[4]; - WData/*127:0*/ __Vtemp1343[4]; - WData/*127:0*/ __Vtemp1344[4]; - WData/*127:0*/ __Vtemp1345[4]; - WData/*127:0*/ __Vtemp1346[4]; - WData/*223:0*/ __Vtemp1347[7]; - WData/*127:0*/ __Vtemp1348[4]; - WData/*127:0*/ __Vtemp1353[4]; - WData/*127:0*/ __Vtemp1359[4]; - WData/*127:0*/ __Vtemp1360[4]; - WData/*127:0*/ __Vtemp1363[4]; - WData/*127:0*/ __Vtemp1364[4]; - WData/*127:0*/ __Vtemp1365[4]; - WData/*127:0*/ __Vtemp1367[4]; - WData/*127:0*/ __Vtemp1372[4]; - WData/*127:0*/ __Vtemp1378[4]; - WData/*127:0*/ __Vtemp1379[4]; - WData/*127:0*/ __Vtemp1382[4]; - WData/*127:0*/ __Vtemp1383[4]; - WData/*127:0*/ __Vtemp1384[4]; - WData/*127:0*/ __Vtemp1386[4]; - WData/*127:0*/ __Vtemp1391[4]; - WData/*127:0*/ __Vtemp1397[4]; - WData/*127:0*/ __Vtemp1398[4]; - WData/*127:0*/ __Vtemp1401[4]; - WData/*127:0*/ __Vtemp1402[4]; - WData/*127:0*/ __Vtemp1403[4]; - WData/*127:0*/ __Vtemp1405[4]; - WData/*127:0*/ __Vtemp1410[4]; - WData/*127:0*/ __Vtemp1416[4]; - WData/*127:0*/ __Vtemp1417[4]; - WData/*127:0*/ __Vtemp1420[4]; - WData/*127:0*/ __Vtemp1421[4]; - WData/*127:0*/ __Vtemp1422[4]; - WData/*127:0*/ __Vtemp1424[4]; - WData/*127:0*/ __Vtemp1429[4]; - WData/*127:0*/ __Vtemp1435[4]; - WData/*127:0*/ __Vtemp1436[4]; - WData/*127:0*/ __Vtemp1439[4]; - WData/*127:0*/ __Vtemp1440[4]; - WData/*127:0*/ __Vtemp1441[4]; - WData/*127:0*/ __Vtemp1443[4]; - WData/*127:0*/ __Vtemp1448[4]; - WData/*127:0*/ __Vtemp1454[4]; - WData/*127:0*/ __Vtemp1455[4]; - WData/*127:0*/ __Vtemp1458[4]; - WData/*127:0*/ __Vtemp1459[4]; - WData/*127:0*/ __Vtemp1460[4]; - WData/*127:0*/ __Vtemp1462[4]; - WData/*127:0*/ __Vtemp1467[4]; - WData/*127:0*/ __Vtemp1473[4]; - WData/*127:0*/ __Vtemp1474[4]; - WData/*127:0*/ __Vtemp1477[4]; - WData/*127:0*/ __Vtemp1478[4]; - WData/*127:0*/ __Vtemp1479[4]; - WData/*127:0*/ __Vtemp1481[4]; - WData/*127:0*/ __Vtemp1486[4]; - WData/*127:0*/ __Vtemp1492[4]; - WData/*127:0*/ __Vtemp1493[4]; - WData/*127:0*/ __Vtemp1496[4]; - WData/*127:0*/ __Vtemp1497[4]; - WData/*127:0*/ __Vtemp1498[4]; + WData/*127:0*/ __Vtemp662[4]; + WData/*127:0*/ __Vtemp681[4]; + WData/*127:0*/ __Vtemp700[4]; + WData/*127:0*/ __Vtemp719[4]; + WData/*127:0*/ __Vtemp637[4]; + WData/*127:0*/ __Vtemp638[4]; + WData/*127:0*/ __Vtemp639[4]; + WData/*127:0*/ __Vtemp640[4]; + WData/*127:0*/ __Vtemp643[4]; + WData/*127:0*/ __Vtemp644[4]; + WData/*127:0*/ __Vtemp649[4]; + WData/*127:0*/ __Vtemp655[4]; + WData/*127:0*/ __Vtemp656[4]; + WData/*127:0*/ __Vtemp659[4]; + WData/*127:0*/ __Vtemp660[4]; + WData/*127:0*/ __Vtemp661[4]; + WData/*127:0*/ __Vtemp663[4]; + WData/*127:0*/ __Vtemp668[4]; + WData/*127:0*/ __Vtemp674[4]; + WData/*127:0*/ __Vtemp675[4]; + WData/*127:0*/ __Vtemp678[4]; + WData/*127:0*/ __Vtemp679[4]; + WData/*127:0*/ __Vtemp680[4]; + WData/*127:0*/ __Vtemp682[4]; + WData/*127:0*/ __Vtemp687[4]; + WData/*127:0*/ __Vtemp693[4]; + WData/*127:0*/ __Vtemp694[4]; + WData/*127:0*/ __Vtemp697[4]; + WData/*127:0*/ __Vtemp698[4]; + WData/*127:0*/ __Vtemp699[4]; + WData/*127:0*/ __Vtemp701[4]; + WData/*127:0*/ __Vtemp706[4]; + WData/*127:0*/ __Vtemp712[4]; + WData/*127:0*/ __Vtemp713[4]; + WData/*127:0*/ __Vtemp716[4]; + WData/*127:0*/ __Vtemp717[4]; + WData/*127:0*/ __Vtemp718[4]; // Body { - vcdp->chgBus(c+2113,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),8); - vcdp->chgBus(c+2121,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),8); - vcdp->chgBus(c+2129,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),16); - vcdp->chgArray(c+2137,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),256); - vcdp->chgArray(c+2201,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),336); - vcdp->chgBus(c+2289,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),8); - vcdp->chgArray(c+2297,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),224); - vcdp->chgBus(c+2353,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),8); - vcdp->chgBus(c+2361,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),8); - vcdp->chgArray(c+2369,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),128); - vcdp->chgArray(c+2401,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),224); - vcdp->chgArray(c+2457,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),1024); - vcdp->chgBus(c+2713,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),8); - vcdp->chgBus(c+2721,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),8); - vcdp->chgArray(c+2729,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),224); - vcdp->chgBus(c+2785,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + vcdp->chgBus(c+1089,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),4); + vcdp->chgBus(c+1097,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),4); + vcdp->chgBus(c+1105,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),8); + vcdp->chgArray(c+1113,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),128); + vcdp->chgArray(c+1145,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),168); + vcdp->chgBus(c+1193,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),4); + vcdp->chgArray(c+1201,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),112); + vcdp->chgBus(c+1233,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),4); + vcdp->chgBus(c+1241,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),4); + vcdp->chgQuad(c+1249,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),64); + vcdp->chgArray(c+1265,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),112); + vcdp->chgArray(c+1297,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),512); + vcdp->chgBus(c+1425,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),4); + vcdp->chgBus(c+1433,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),4); + vcdp->chgArray(c+1441,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),112); + vcdp->chgBus(c+1473,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->chgBus(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+2801,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1489,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+2817,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+1505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ @@ -485,39 +301,39 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+2833,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->chgBit(c+1513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1521,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+2841,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1529,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1339[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1339[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1339[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1339[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+2849,(__Vtemp1339),128); - vcdp->chgBit(c+2881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+2889,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBus(c+2897,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0x1cU)))),26); + __Vtemp637[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp637[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp637[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp637[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1537,(__Vtemp637),128); + vcdp->chgBit(c+1569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1577,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+1585,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->chgBus(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+2913,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+1593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1601,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+2929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+1617,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ @@ -526,39 +342,39 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+2937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+2945,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->chgBit(c+1625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1633,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+2953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1641,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1340[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1340[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1340[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1340[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+2961,(__Vtemp1340),128); - vcdp->chgBit(c+2993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+3001,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBus(c+3009,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0x1cU)))),26); + __Vtemp638[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp638[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp638[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp638[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1649,(__Vtemp638),128); + vcdp->chgBit(c+1681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1689,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+1697,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->chgBus(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+3025,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+1705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1713,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+3041,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+1729,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ @@ -567,39 +383,39 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+3057,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->chgBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1745,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+3065,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1753,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1341[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1341[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1341[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1341[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+3073,(__Vtemp1341),128); - vcdp->chgBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+3113,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBus(c+3121,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + >> 0x1cU)))),26); + __Vtemp639[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp639[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp639[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp639[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1761,(__Vtemp639),128); + vcdp->chgBit(c+1793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1801,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBus(c+1809,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->chgBus(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+3137,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+1817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->chgQuad(c+1825,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+3153,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+1841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ @@ -608,197 +424,33 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+3169,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->chgBit(c+1849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->chgBus(c+1857,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+3177,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->chgBus(c+1865,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1342[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1342[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1342[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1342[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+3185,(__Vtemp1342),128); - vcdp->chgBit(c+3217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+3225,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBus(c+3233,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->chgBus(c+3241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+3249,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+3265,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+3273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+3281,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+3289,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1343[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1343[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1343[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1343[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+3297,(__Vtemp1343),128); - vcdp->chgBit(c+3329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+3337,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBus(c+3345,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->chgBus(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+3361,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+3377,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+3385,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+3393,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+3401,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1344[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1344[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1344[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1344[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+3409,(__Vtemp1344),128); - vcdp->chgBit(c+3441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+3449,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBus(c+3457,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->chgBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+3473,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+3489,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+3497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+3505,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+3513,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1345[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1345[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1345[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1345[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+3521,(__Vtemp1345),128); - vcdp->chgBit(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+3561,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBus(c+3569,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->chgBus(c+3577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->chgQuad(c+3585,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->chgBit(c+3601,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->chgBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->chgBus(c+3617,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->chgBus(c+3625,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp1346[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp1346[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp1346[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp1346[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->chgArray(c+3633,(__Vtemp1346),128); - vcdp->chgBit(c+3665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->chgBus(c+3673,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->chgBit(c+3681,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); - vcdp->chgBit(c+3689,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); - vcdp->chgBus(c+3697,(((0xdfU >= (0xffU & ((IData)(0x1cU) + >> 0x1cU)))),26); + __Vtemp640[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] + >> 0x1cU)); + __Vtemp640[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)); + __Vtemp640[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + >> 0x1cU)); + __Vtemp640[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + >> 0x1cU)); + vcdp->chgArray(c+1873,(__Vtemp640),128); + vcdp->chgBit(c+1905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->chgBus(c+1913,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->chgBit(c+1921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); + vcdp->chgBit(c+1929,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vcdp->chgBus(c+1937,(((0x6fU >= (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) ? (0xfffffffU & (((0U == @@ -810,7 +462,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U)))] @@ -821,7 +473,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U))] @@ -830,45 +482,43 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) : 0U)),28); - vcdp->chgBit(c+3705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+3713,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); - vcdp->chgBus(c+3721,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),3); - vcdp->chgBit(c+3729,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); - vcdp->chgBit(c+3737,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); - vcdp->chgBit(c+3745,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); - vcdp->chgBus(c+3753,((0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])),8); - __Vtemp1347[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; - __Vtemp1347[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; - __Vtemp1347[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; - __Vtemp1347[3U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]; - __Vtemp1347[4U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]; - __Vtemp1347[5U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]; - __Vtemp1347[6U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]; - vcdp->chgArray(c+3761,(__Vtemp1347),224); - vcdp->chgBus(c+3817,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),8); - vcdp->chgArray(c+3825,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),224); - vcdp->chgBus(c+3881,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) - & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),8); - vcdp->chgBit(c+3889,((1U & ((~ (IData)((0U + vcdp->chgBit(c+1945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+1953,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); + vcdp->chgBus(c+1961,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),2); + vcdp->chgBit(c+1969,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); + vcdp->chgBit(c+1977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); + vcdp->chgBit(c+1985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); + vcdp->chgBus(c+1993,((0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))),4); + __Vtemp643[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; + __Vtemp643[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; + __Vtemp643[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; + __Vtemp643[3U] = (0xffffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); + vcdp->chgArray(c+2001,(__Vtemp643),112); + vcdp->chgBus(c+2033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),4); + vcdp->chgArray(c+2041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),112); + vcdp->chgBus(c+2073,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),4); + vcdp->chgBit(c+2081,((1U & ((~ (IData)((0U != - (0xffU - & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+3897,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + vcdp->chgBit(c+2089,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+3905,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),3); - vcdp->chgBit(c+3913,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); - vcdp->chgArray(c+3921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),232); - vcdp->chgArray(c+3985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),232); - vcdp->chgBit(c+4049,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); - vcdp->chgBus(c+4057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->chgBus(c+4065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgBus(c+4073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->chgBus(c+4081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+4089,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); - vcdp->chgQuad(c+4121,(((0x14fU >= (0x1ffU & - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + vcdp->chgBus(c+2097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+2105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); + vcdp->chgArray(c+2113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),116); + vcdp->chgArray(c+2145,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),116); + vcdp->chgBit(c+2177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); + vcdp->chgBus(c+2185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBus(c+2201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+2217,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); + vcdp->chgQuad(c+2249,(((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (VL_ULL(0x3ffffffffff) & (((0U == (0x1fU & ((IData)(0x2aU) @@ -878,7 +528,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(2U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -890,7 +540,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -906,7 +556,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | ((QData)((IData)( vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))])) @@ -914,47 +564,47 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) : VL_ULL(0))),42); - vcdp->chgBus(c+4137,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),8); - vcdp->chgBus(c+4145,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),3); - vcdp->chgBit(c+4153,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); - vcdp->chgBus(c+4161,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->chgBus(c+4169,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + vcdp->chgBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); + vcdp->chgBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); + vcdp->chgBit(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); + vcdp->chgBus(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),8); - vcdp->chgBus(c+4177,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),4); + vcdp->chgBus(c+2305,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),8); - vcdp->chgBus(c+4185,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgBus(c+4193,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),3); - vcdp->chgBit(c+4201,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); - vcdp->chgBus(c+4209,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->chgBus(c+4217,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgBit(c+4225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+4233,((0x1ffffffU & (IData)( + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),4); + vcdp->chgBus(c+2313,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBus(c+2321,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),2); + vcdp->chgBit(c+2329,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); + vcdp->chgBus(c+2337,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2345,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgBit(c+2353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+2361,((0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+4241,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+2369,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))))); - vcdp->chgBus(c+4249,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+4257,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+4265,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1348[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1348[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1348[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1348[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+4273,(__Vtemp1348),128); - vcdp->chgBit(c+4305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+4313,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+4321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+4329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+4337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+4345,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + vcdp->chgBus(c+2377,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+2385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+2393,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp644[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp644[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp644[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp644[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+2401,(__Vtemp644),128); + vcdp->chgBit(c+2433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+2441,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+2449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+2457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+2465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+2473,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 2U))))),4); - vcdp->chgBus(c+4353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+4361,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + vcdp->chgBus(c+2481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+2489,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ ((IData)(1U) @@ -967,51 +617,51 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))))),32); - vcdp->chgBit(c+4369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+4393,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+4401,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + vcdp->chgBit(c+2497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+2505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+2513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+2521,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+2529,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))); - vcdp->chgBit(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+4417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+4449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+4457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+4513,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + vcdp->chgBit(c+2537,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+2545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+2553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+2561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+2569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+2577,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+2585,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+2593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+2601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+2609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+2617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+2625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+2633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+2641,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+4521,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU + vcdp->chgBus(c+2649,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -1019,40 +669,40 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+4529,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + : 0U)))))),26); + vcdp->chgBus(c+2657,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (3U & (( @@ -1063,7 +713,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) : 0U)))),2); - vcdp->chgBus(c+4537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBus(c+2665,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -1090,20 +740,20 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U)))) : 0U))),32); - __Vtemp1353[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1353[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1353[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1353[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+4545,(__Vtemp1353),128); - vcdp->chgQuad(c+4577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp649[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp649[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp649[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp649[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+2673,(__Vtemp649),128); + vcdp->chgQuad(c+2705,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -1154,20 +804,20 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + vcdp->chgBit(c+2721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))))); - vcdp->chgBit(c+4601,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBit(c+2729,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U))))); - vcdp->chgBit(c+4609,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBit(c+2737,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) @@ -1175,27 +825,27 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U))))); - vcdp->chgBit(c+4617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+4625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+4633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+4641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+4649,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+4665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+4713,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1359[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + vcdp->chgBit(c+2745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+2753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+2761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+2769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+2777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+2833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+2841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp655[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1359[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp655[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1359[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp655[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1359[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp655[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->chgBus(c+4721,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBus(c+2849,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))) - ? 0U : (__Vtemp1359[ + ? 0U : (__Vtemp655[ ((IData)(1U) + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]))] @@ -1204,303 +854,304 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp1359[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 - [0U])] + | (__Vtemp655[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))),32); - __Vtemp1360[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp656[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1360[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp656[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1360[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp656[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1360[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp656[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->chgArray(c+4729,(__Vtemp1360),128); - vcdp->chgBus(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+4777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+4785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + vcdp->chgArray(c+2857,(__Vtemp656),128); + vcdp->chgBus(c+2889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+2897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+2913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c [0U]),16); - vcdp->chgQuad(c+4793,((VL_ULL(0x3ffffffffff) + vcdp->chgQuad(c+2921,((VL_ULL(0x3ffffffffff) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 7U))),42); - vcdp->chgBus(c+4809,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBus(c+2937,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U]))),2); - vcdp->chgBit(c+4817,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBit(c+2945,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U))))); - vcdp->chgBus(c+4825,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBus(c+2953,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 2U)))),4); - vcdp->chgBit(c+4833,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + vcdp->chgBit(c+2961,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + vcdp->chgBit(c+2969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])); - vcdp->chgBit(c+4849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + vcdp->chgBit(c+2977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])); - vcdp->chgBit(c+4857,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+4865,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + vcdp->chgBit(c+2985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+2993,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U])))); - vcdp->chgBit(c+4873,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+4881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+3001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+3009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U])); - vcdp->chgBit(c+4889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + vcdp->chgBit(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U])); - vcdp->chgBit(c+4897,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+3025,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->chgBus(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+4913,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBus(c+3033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+3041,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->chgBit(c+4921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+4929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+3057,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+4937,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+3065,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->chgBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+4953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+4969,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + vcdp->chgBit(c+3073,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+3081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+3089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+3097,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+4985,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+3113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU))))))); - vcdp->chgBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + vcdp->chgBit(c+3121,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+5017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + vcdp->chgBit(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+3137,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+3145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+3153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] >> 6U)))); - vcdp->chgBit(c+5025,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+5041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+5105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+5113,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+3169,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+3185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+3193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+3233,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+3241,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))),4); - vcdp->chgBus(c+5121,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBus(c+3249,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x12U))),4); - vcdp->chgBus(c+5129,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBus(c+3257,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 2U))),16); - __Vtemp1363[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1363[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1363[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1363[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+5137,(__Vtemp1363),120); - __Vtemp1364[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1364[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1364[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1364[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+5169,(__Vtemp1364),128); - vcdp->chgQuad(c+5201,((VL_ULL(0x3ffffffffff) + __Vtemp659[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp659[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp659[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp659[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+3265,(__Vtemp659),120); + __Vtemp660[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp660[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp660[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp660[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+3297,(__Vtemp660),128); + vcdp->chgQuad(c+3329,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+5217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+5225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+5233,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBit(c+3345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+3361,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U) & VL_NEGATE_I((IData)( (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+5241,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+5321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+5329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+5337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+5345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+5409,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+5417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + vcdp->chgArray(c+3369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+3449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+3457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+3473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+3537,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+3545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])); - vcdp->chgBus(c+5425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + vcdp->chgBus(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U]),32); - __Vtemp1365[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp661[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][0U]; - __Vtemp1365[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp661[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][1U]; - __Vtemp1365[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp661[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][2U]; - __Vtemp1365[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp661[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][3U]; - vcdp->chgArray(c+5433,(__Vtemp1365),128); - vcdp->chgBus(c+5465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgArray(c+3561,(__Vtemp661),128); + vcdp->chgBus(c+3593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]),2); - vcdp->chgBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+5489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+5497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+5505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+5537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+5545,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + vcdp->chgBit(c+3601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+3617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+3625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+3633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+3665,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+3673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+3681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])]),16); - vcdp->chgBus(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1366[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + vcdp->chgBus(c+3689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp662[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1366[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + __Vtemp662[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1366[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + __Vtemp662[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1366[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + __Vtemp662[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->chgArray(c+5569,(__Vtemp1366),128); - vcdp->chgBit(c+5601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + vcdp->chgArray(c+3697,(__Vtemp662),128); + vcdp->chgBit(c+3729,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])); - vcdp->chgBit(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + vcdp->chgBit(c+3737,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U])); - vcdp->chgBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->chgArray(c+5625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->chgBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->chgBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->chgBit(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->chgBus(c+5681,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->chgBus(c+5689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->chgBit(c+5697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->chgBit(c+5705,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBus(c+3745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+3753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+3785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+3793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+3801,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+3809,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+3817,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+3825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+3833,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->chgBit(c+5713,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+3841,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->chgBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+5729,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + vcdp->chgBit(c+3849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+3857,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+5737,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+3865,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+5745,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+3873,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+5753,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+3881,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+5761,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+3889,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+5769,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+5777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+5825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+5905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+5913,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->chgBit(c+3897,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+3905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+3953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+4033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+4041,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+5921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+5929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+5937,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+5945,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + vcdp->chgBus(c+4049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+4057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+4065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+4073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+5953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+5961,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+5969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->chgBit(c+4081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+4089,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+4097,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+6001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+6025,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->chgBit(c+6153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+6161,((0x1ffffffU & (IData)( + vcdp->chgArray(c+4105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+4129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+4153,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+4161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+4217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+4273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+4281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+4289,((0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+6169,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+4297,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))))); - vcdp->chgBus(c+6177,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+6185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+6193,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1367[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1367[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1367[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1367[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+6201,(__Vtemp1367),128); - vcdp->chgBit(c+6233,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+6241,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+6249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+6257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+6265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+6273,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + vcdp->chgBus(c+4305,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+4313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+4321,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp663[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp663[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp663[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp663[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+4329,(__Vtemp663),128); + vcdp->chgBit(c+4361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+4369,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+4393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+4401,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 2U))))),4); - vcdp->chgBus(c+6281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+6289,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + vcdp->chgBus(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+4417,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ ((IData)(1U) @@ -1513,51 +1164,51 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))))),32); - vcdp->chgBit(c+6297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+6321,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+6329,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + vcdp->chgBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+4449,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+4457,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))); - vcdp->chgBit(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+6345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+6377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+6385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+6441,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + vcdp->chgBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+4513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+4521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+4529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+4537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+4545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+4553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+4561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+4569,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+6449,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU + vcdp->chgBus(c+4577,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -1565,40 +1216,40 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+6457,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + : 0U)))))),26); + vcdp->chgBus(c+4585,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (3U & (( @@ -1609,7 +1260,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) : 0U)))),2); - vcdp->chgBus(c+6465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBus(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -1636,20 +1287,20 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U)))) : 0U))),32); - __Vtemp1372[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1372[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1372[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1372[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+6473,(__Vtemp1372),128); - vcdp->chgQuad(c+6505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp668[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp668[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp668[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp668[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+4601,(__Vtemp668),128); + vcdp->chgQuad(c+4633,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -1700,20 +1351,20 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + vcdp->chgBit(c+4649,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))))); - vcdp->chgBit(c+6529,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBit(c+4657,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U))))); - vcdp->chgBit(c+6537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBit(c+4665,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) @@ -1721,27 +1372,27 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U))))); - vcdp->chgBit(c+6545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+6553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+6561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+6569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+6577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+6593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+6641,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1378[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + vcdp->chgBit(c+4673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+4681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+4689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+4721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+4753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp674[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1378[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp674[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1378[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp674[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1378[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp674[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->chgBus(c+6649,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBus(c+4777,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))) - ? 0U : (__Vtemp1378[ + ? 0U : (__Vtemp674[ ((IData)(1U) + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]))] @@ -1750,303 +1401,304 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp1378[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 - [0U])] + | (__Vtemp674[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))),32); - __Vtemp1379[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp675[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1379[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp675[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1379[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp675[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1379[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp675[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->chgArray(c+6657,(__Vtemp1379),128); - vcdp->chgBus(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+6705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+6713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + vcdp->chgArray(c+4785,(__Vtemp675),128); + vcdp->chgBus(c+4817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+4825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+4833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c [0U]),16); - vcdp->chgQuad(c+6721,((VL_ULL(0x3ffffffffff) + vcdp->chgQuad(c+4849,((VL_ULL(0x3ffffffffff) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 7U))),42); - vcdp->chgBus(c+6737,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBus(c+4865,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U]))),2); - vcdp->chgBit(c+6745,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBit(c+4873,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U))))); - vcdp->chgBus(c+6753,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBus(c+4881,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 2U)))),4); - vcdp->chgBit(c+6761,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + vcdp->chgBit(c+4889,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + vcdp->chgBit(c+4897,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])); - vcdp->chgBit(c+6777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + vcdp->chgBit(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])); - vcdp->chgBit(c+6785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+6793,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + vcdp->chgBit(c+4913,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+4921,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U])))); - vcdp->chgBit(c+6801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+6809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+4929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+4937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U])); - vcdp->chgBit(c+6817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + vcdp->chgBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U])); - vcdp->chgBit(c+6825,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+4953,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->chgBus(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+6841,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBus(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+4969,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->chgBit(c+6849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+6857,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+4985,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+6865,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->chgBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+6881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+6897,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + vcdp->chgBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+5017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+5025,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+6913,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+5041,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU))))))); - vcdp->chgBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + vcdp->chgBit(c+5049,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+6945,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + vcdp->chgBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+5073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+5081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] >> 6U)))); - vcdp->chgBit(c+6953,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+6969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+7033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+7041,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBit(c+5089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+5097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+5113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+5121,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+5161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+5169,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))),4); - vcdp->chgBus(c+7049,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBus(c+5177,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x12U))),4); - vcdp->chgBus(c+7057,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBus(c+5185,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 2U))),16); - __Vtemp1382[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1382[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1382[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1382[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+7065,(__Vtemp1382),120); - __Vtemp1383[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1383[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1383[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1383[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+7097,(__Vtemp1383),128); - vcdp->chgQuad(c+7129,((VL_ULL(0x3ffffffffff) + __Vtemp678[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp678[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp678[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp678[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+5193,(__Vtemp678),120); + __Vtemp679[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp679[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp679[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp679[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+5225,(__Vtemp679),128); + vcdp->chgQuad(c+5257,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+7145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+7153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+7161,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBit(c+5273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+5281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+5289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U) & VL_NEGATE_I((IData)( (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+7169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+7249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+7257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+7265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+7273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+7337,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+7345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + vcdp->chgArray(c+5297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+5377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+5385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+5393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+5401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+5465,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])); - vcdp->chgBus(c+7353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + vcdp->chgBus(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U]),32); - __Vtemp1384[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp680[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][0U]; - __Vtemp1384[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp680[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][1U]; - __Vtemp1384[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp680[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][2U]; - __Vtemp1384[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp680[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][3U]; - vcdp->chgArray(c+7361,(__Vtemp1384),128); - vcdp->chgBus(c+7393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgArray(c+5489,(__Vtemp680),128); + vcdp->chgBus(c+5521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]),2); - vcdp->chgBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+7417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+7425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+7433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+7465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+7473,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + vcdp->chgBit(c+5529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+5537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+5545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+5593,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+5601,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])]),16); - vcdp->chgBus(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1385[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + vcdp->chgBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp681[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1385[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + __Vtemp681[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1385[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + __Vtemp681[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1385[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + __Vtemp681[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->chgArray(c+7497,(__Vtemp1385),128); - vcdp->chgBit(c+7529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + vcdp->chgArray(c+5625,(__Vtemp681),128); + vcdp->chgBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])); - vcdp->chgBit(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + vcdp->chgBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U])); - vcdp->chgBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->chgArray(c+7553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->chgBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->chgBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->chgBit(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->chgBus(c+7609,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->chgBus(c+7617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->chgBit(c+7625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->chgBit(c+7633,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBus(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+5681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+5713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+5729,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+5737,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+5745,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+5753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+5761,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->chgBit(c+7641,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+5769,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->chgBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+7657,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + vcdp->chgBit(c+5777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+5785,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+7665,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+5793,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+7673,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+5801,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+7681,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+5809,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+7689,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+5817,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+7697,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+7753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+7833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+7841,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->chgBit(c+5825,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+5833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+5881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+5961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+5969,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+7849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+7857,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+7865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+7873,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + vcdp->chgBus(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+5985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+5993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+6001,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+7881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+7889,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+7897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->chgBit(c+6009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+6017,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+6025,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+7929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+7953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+7961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+8017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+8073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->chgBit(c+8081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+8089,((0x1ffffffU & (IData)( + vcdp->chgArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+6057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+6081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+6201,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+6209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+6217,((0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+8097,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+6225,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))))); - vcdp->chgBus(c+8105,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+8113,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+8121,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1386[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1386[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1386[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1386[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+8129,(__Vtemp1386),128); - vcdp->chgBit(c+8161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+8169,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+8177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+8185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+8193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+8201,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + vcdp->chgBus(c+6233,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+6241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+6249,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp682[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp682[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp682[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp682[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+6257,(__Vtemp682),128); + vcdp->chgBit(c+6289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+6297,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+6321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+6329,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 2U))))),4); - vcdp->chgBus(c+8209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+8217,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + vcdp->chgBus(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+6345,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ ((IData)(1U) @@ -2059,51 +1711,51 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))))),32); - vcdp->chgBit(c+8225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+8233,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+8241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+8249,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+8257,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + vcdp->chgBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+6377,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+6385,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))); - vcdp->chgBit(c+8265,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+8273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+8305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+8313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+8369,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + vcdp->chgBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+6441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+6449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+6457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+6465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+6473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+6481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+6489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+6497,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+8377,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU + vcdp->chgBus(c+6505,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -2111,40 +1763,40 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+8385,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + : 0U)))))),26); + vcdp->chgBus(c+6513,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (3U & (( @@ -2155,7 +1807,7 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) : 0U)))),2); - vcdp->chgBus(c+8393,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBus(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -2182,20 +1834,20 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U)))) : 0U))),32); - __Vtemp1391[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1391[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1391[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1391[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+8401,(__Vtemp1391),128); - vcdp->chgQuad(c+8433,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp687[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp687[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp687[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp687[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+6529,(__Vtemp687),128); + vcdp->chgQuad(c+6561,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -2246,20 +1898,20 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + vcdp->chgBit(c+6577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))))); - vcdp->chgBit(c+8457,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBit(c+6585,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U))))); - vcdp->chgBit(c+8465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->chgBit(c+6593,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) @@ -2267,27 +1919,27 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U))))); - vcdp->chgBit(c+8473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+8481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+8489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+8497,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+8505,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+8521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+8569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1397[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + vcdp->chgBit(c+6601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+6609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+6617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+6649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+6681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp693[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1397[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp693[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1397[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp693[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1397[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp693[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->chgBus(c+8577,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBus(c+6705,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))) - ? 0U : (__Vtemp1397[ + ? 0U : (__Vtemp693[ ((IData)(1U) + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]))] @@ -2296,3034 +1948,827 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp1397[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 - [0U])] + | (__Vtemp693[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))),32); - __Vtemp1398[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp694[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1398[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp694[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1398[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp694[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1398[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp694[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->chgArray(c+8585,(__Vtemp1398),128); - vcdp->chgBus(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+8633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+8641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + vcdp->chgArray(c+6713,(__Vtemp694),128); + vcdp->chgBus(c+6745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+6753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+6761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c [0U]),16); - vcdp->chgQuad(c+8649,((VL_ULL(0x3ffffffffff) + vcdp->chgQuad(c+6777,((VL_ULL(0x3ffffffffff) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 7U))),42); - vcdp->chgBus(c+8665,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBus(c+6793,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U]))),2); - vcdp->chgBit(c+8673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBit(c+6801,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U))))); - vcdp->chgBus(c+8681,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->chgBus(c+6809,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 2U)))),4); - vcdp->chgBit(c+8689,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + vcdp->chgBit(c+6817,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + vcdp->chgBit(c+6825,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])); - vcdp->chgBit(c+8705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + vcdp->chgBit(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])); - vcdp->chgBit(c+8713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+8721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + vcdp->chgBit(c+6841,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+6849,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U])))); - vcdp->chgBit(c+8729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+8737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+6857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+6865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U])); - vcdp->chgBit(c+8745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + vcdp->chgBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U])); - vcdp->chgBit(c+8753,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+6881,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->chgBus(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+8769,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBus(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+6897,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->chgBit(c+8777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+8785,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+6913,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+8793,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->chgBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+8809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+8825,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + vcdp->chgBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+6945,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+6953,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+8841,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->chgBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+6969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU))))))); - vcdp->chgBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + vcdp->chgBit(c+6977,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+8873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + vcdp->chgBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+7001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+7009,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] >> 6U)))); - vcdp->chgBit(c+8881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+8897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+8961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+8969,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBit(c+7017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+7025,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+7041,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+7049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+7089,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+7097,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))),4); - vcdp->chgBus(c+8977,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBus(c+7105,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x12U))),4); - vcdp->chgBus(c+8985,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBus(c+7113,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 2U))),16); - __Vtemp1401[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1401[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1401[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1401[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+8993,(__Vtemp1401),120); - __Vtemp1402[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1402[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1402[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1402[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+9025,(__Vtemp1402),128); - vcdp->chgQuad(c+9057,((VL_ULL(0x3ffffffffff) + __Vtemp697[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp697[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp697[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp697[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+7121,(__Vtemp697),120); + __Vtemp698[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp698[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp698[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp698[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+7153,(__Vtemp698),128); + vcdp->chgQuad(c+7185,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+9073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+9081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+9089,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->chgBit(c+7201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+7209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+7217,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U) & VL_NEGATE_I((IData)( (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+9097,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+9177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+9185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+9193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+9201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+9265,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+9273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + vcdp->chgArray(c+7225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+7305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+7313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+7321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+7329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+7393,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])); - vcdp->chgBus(c+9281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + vcdp->chgBus(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U]),32); - __Vtemp1403[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp699[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][0U]; - __Vtemp1403[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp699[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][1U]; - __Vtemp1403[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp699[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][2U]; - __Vtemp1403[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp699[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][3U]; - vcdp->chgArray(c+9289,(__Vtemp1403),128); - vcdp->chgBus(c+9321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgArray(c+7417,(__Vtemp699),128); + vcdp->chgBus(c+7449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]),2); - vcdp->chgBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+9345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+9353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+9361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+9393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+9401,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + vcdp->chgBit(c+7457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+7465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+7473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+7521,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+7529,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])]),16); - vcdp->chgBus(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1404[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + vcdp->chgBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp700[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1404[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + __Vtemp700[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1404[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + __Vtemp700[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1404[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + __Vtemp700[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->chgArray(c+9425,(__Vtemp1404),128); - vcdp->chgBit(c+9457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + vcdp->chgArray(c+7553,(__Vtemp700),128); + vcdp->chgBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])); - vcdp->chgBit(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + vcdp->chgBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U])); - vcdp->chgBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->chgArray(c+9481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->chgBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->chgBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->chgBit(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->chgBus(c+9537,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->chgBus(c+9545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->chgBit(c+9553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->chgBit(c+9561,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBus(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+7609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+7641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+7657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+7665,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+7673,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+7681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+7689,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->chgBit(c+9569,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->chgBit(c+7697,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->chgBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+9585,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + vcdp->chgBit(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+7713,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+9593,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+7721,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+9601,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+7729,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+9609,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+7737,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+9617,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->chgBit(c+7745,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+9625,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+9681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+9761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+9769,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->chgBit(c+7753,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+7761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+7809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+7889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+7897,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+9777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+9785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+9793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+9801,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + vcdp->chgBus(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+7913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+7921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+7929,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+9809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+9817,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+9825,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->chgBit(c+7937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+7945,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+7953,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+9833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+9857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+9881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+9889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+9945,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+10001,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->chgBit(c+10009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+10017,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+10025,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))))); - vcdp->chgBus(c+10033,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+10041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+10049,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1405[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1405[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1405[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1405[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+10057,(__Vtemp1405),128); - vcdp->chgBit(c+10089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+10097,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+10105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+10113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+10121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+10129,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->chgBus(c+10137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+10145,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->chgBit(c+10153,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+10161,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+10169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+10177,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+10185,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))); - vcdp->chgBit(c+10193,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+10201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+10209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+10217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+10225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+10233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+10241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+10249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+10257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+10265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+10273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+10281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+10289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+10297,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+10305,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+10313,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & ( - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->chgBus(c+10321,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1410[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1410[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1410[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1410[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+10329,(__Vtemp1410),128); - vcdp->chgQuad(c+10361,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+10377,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->chgBit(c+10385,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->chgBit(c+10393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->chgBit(c+10401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+10409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+10417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+10425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+10433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+10449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+10481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+10489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+10497,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1416[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1416[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1416[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1416[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgBus(c+10505,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U : (__Vtemp1416[ - ((IData)(1U) - + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << ((IData)(0x20U) - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp1416[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))),32); - __Vtemp1417[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1417[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1417[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1417[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgArray(c+10513,(__Vtemp1417),128); - vcdp->chgBus(c+10545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+10553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+10561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+10569,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); - vcdp->chgQuad(c+10577,((VL_ULL(0x3ffffffffff) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 7U))),42); - vcdp->chgBus(c+10593,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 - [0U]))),2); - vcdp->chgBit(c+10601,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U))))); - vcdp->chgBus(c+10609,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U)))),4); - vcdp->chgBit(c+10617,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+10625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])); - vcdp->chgBit(c+10633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])); - vcdp->chgBit(c+10641,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+10649,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U])))); - vcdp->chgBit(c+10657,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+10665,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U])); - vcdp->chgBit(c+10673,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])); - vcdp->chgBit(c+10681,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + vcdp->chgArray(c+7961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+7985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+8009,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+8017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+8073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+8129,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->chgBit(c+8137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)); + vcdp->chgBus(c+8145,((0x3ffffffU & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->chgBit(c+8153,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))))); + vcdp->chgBus(c+8161,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->chgBit(c+8169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->chgBus(c+8177,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp701[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp701[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp701[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp701[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->chgArray(c+8185,(__Vtemp701),128); + vcdp->chgBit(c+8217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)); + vcdp->chgBit(c+8225,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->chgBit(c+8233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->chgBus(c+8241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->chgBit(c+8249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->chgBus(c+8257,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))))),4); + vcdp->chgBus(c+8265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->chgBus(c+8273,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << ((IData)(0x20U) + - (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))),32); + vcdp->chgBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->chgBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->chgBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->chgBit(c+8305,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->chgBit(c+8313,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBus(c+10689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+10697,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+10705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+10713,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+10721,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBit(c+10729,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+10737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+10745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+10753,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+10761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+10769,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))))); - vcdp->chgBit(c+10777,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+10785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+10793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+10801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->chgBit(c+10809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+10817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+10825,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+10841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+10849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+10889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+10897,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->chgBus(c+10905,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->chgBus(c+10913,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1420[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1420[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1420[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1420[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+10921,(__Vtemp1420),120); - __Vtemp1421[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1421[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1421[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1421[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+10953,(__Vtemp1421),128); - vcdp->chgQuad(c+10985,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+11001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+11009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+11017,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & - VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+11025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+11105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+11113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+11121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+11129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+11193,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+11201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])); - vcdp->chgBus(c+11209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 - [0U]),32); - __Vtemp1422[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->chgBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->chgBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->chgBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->chgBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->chgBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->chgBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->chgBit(c+8369,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->chgBit(c+8377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->chgBit(c+8385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->chgBit(c+8393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->chgBit(c+8401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->chgBit(c+8409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->chgBit(c+8417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->chgBit(c+8425,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->chgBus(c+8433,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->chgBus(c+8441,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & (( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->chgBus(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp706[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp706[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp706[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp706[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->chgArray(c+8457,(__Vtemp706),128); + vcdp->chgQuad(c+8489,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) | + (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->chgBit(c+8505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->chgBit(c+8513,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->chgBit(c+8521,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->chgBit(c+8529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->chgBus(c+8537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->chgBus(c+8545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->chgBus(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->chgQuad(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->chgArray(c+8577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->chgBit(c+8609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->chgBit(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->chgBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp712[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1422[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + __Vtemp712[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1422[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + __Vtemp712[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1422[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + __Vtemp712[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->chgArray(c+11217,(__Vtemp1422),128); - vcdp->chgBus(c+11249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->chgBit(c+11257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+11265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+11273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+11281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+11289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+11321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+11329,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+11337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->chgBus(c+11345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1423[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + vcdp->chgBus(c+8633,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp712[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp712[(3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp713[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp713[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp713[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp713[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->chgArray(c+8641,(__Vtemp713),128); + vcdp->chgBus(c+8673,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->chgBit(c+8681,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e)); + vcdp->chgBit(c+8689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->chgBus(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->chgQuad(c+8705,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->chgBus(c+8721,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->chgBit(c+8729,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->chgBus(c+8737,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->chgBit(c+8745,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->chgBit(c+8753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->chgBit(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->chgBit(c+8769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->chgBit(c+8777,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->chgBit(c+8785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->chgBit(c+8793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->chgBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->chgBit(c+8809,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBus(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->chgBit(c+8825,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->chgBit(c+8841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->chgBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->chgBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->chgBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); + vcdp->chgBit(c+8873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->chgBit(c+8881,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->chgBit(c+8897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->chgBit(c+8905,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->chgBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->chgBit(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->chgBit(c+8929,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->chgBit(c+8937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->chgBit(c+8945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->chgQuad(c+8953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->chgBit(c+8969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->chgArray(c+8977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->chgBit(c+9017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->chgBus(c+9025,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->chgBus(c+9033,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->chgBus(c+9041,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp716[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp716[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp716[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp716[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->chgArray(c+9049,(__Vtemp716),120); + __Vtemp717[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp717[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp717[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp717[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->chgArray(c+9081,(__Vtemp717),128); + vcdp->chgQuad(c+9113,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->chgBit(c+9129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->chgBit(c+9137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->chgBus(c+9145,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->chgArray(c+9153,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->chgBit(c+9233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->chgBus(c+9241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+9249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->chgArray(c+9257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->chgBus(c+9321,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->chgBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->chgBus(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp718[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp718[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp718[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp718[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->chgArray(c+9345,(__Vtemp718),128); + vcdp->chgBus(c+9377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->chgBit(c+9385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->chgBit(c+9393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->chgBus(c+9401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->chgBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->chgArray(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->chgBit(c+9449,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBit(c+9457,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->chgBus(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->chgBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp719[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1423[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + __Vtemp719[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1423[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + __Vtemp719[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1423[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + __Vtemp719[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->chgArray(c+11353,(__Vtemp1423),128); - vcdp->chgBit(c+11385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->chgBit(c+11393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->chgBus(c+11401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->chgArray(c+11409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->chgBit(c+11441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->chgBit(c+11449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->chgBit(c+11457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->chgBus(c+11465,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->chgBus(c+11473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->chgBit(c+11481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->chgBit(c+11489,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + vcdp->chgArray(c+9481,(__Vtemp719),128); + vcdp->chgBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->chgBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->chgBus(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->chgArray(c+9537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->chgBit(c+9569,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->chgBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->chgBit(c+9585,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->chgBus(c+9593,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->chgBus(c+9601,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->chgBit(c+9609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->chgBit(c+9617,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->chgBit(c+9625,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+11497,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->chgBit(c+11505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+11513,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+11521,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+11529,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+11537,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+11545,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+11553,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+11561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+11609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+11689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+11697,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+11705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+11713,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+11721,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+11729,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+11737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+11745,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+11753,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+11761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+11785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+11809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+11817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+11873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+11929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->chgBit(c+11937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+11945,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+11953,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))))); - vcdp->chgBus(c+11961,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+11969,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+11977,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1424[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1424[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1424[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1424[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+11985,(__Vtemp1424),128); - vcdp->chgBit(c+12017,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+12025,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+12033,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+12041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+12049,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+12057,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->chgBus(c+12065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+12073,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->chgBit(c+12081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+12089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+12097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+12105,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+12113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))); - vcdp->chgBit(c+12121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+12129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+12137,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+12145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+12153,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+12161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+12169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+12177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+12185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+12193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+12201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+12209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+12217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+12225,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+12233,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+12241,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & ( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->chgBus(c+12249,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1429[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1429[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1429[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1429[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+12257,(__Vtemp1429),128); - vcdp->chgQuad(c+12289,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+12305,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->chgBit(c+12313,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->chgBit(c+12321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->chgBit(c+12329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+12337,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+12345,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+12353,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+12361,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+12377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+12409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+12417,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+12425,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1435[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1435[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1435[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1435[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgBus(c+12433,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U : (__Vtemp1435[ - ((IData)(1U) - + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << ((IData)(0x20U) - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp1435[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))),32); - __Vtemp1436[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1436[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1436[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1436[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgArray(c+12441,(__Vtemp1436),128); - vcdp->chgBus(c+12473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+12481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+12489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+12497,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); - vcdp->chgQuad(c+12505,((VL_ULL(0x3ffffffffff) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 7U))),42); - vcdp->chgBus(c+12521,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U]))),2); - vcdp->chgBit(c+12529,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U))))); - vcdp->chgBus(c+12537,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U)))),4); - vcdp->chgBit(c+12545,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+12553,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])); - vcdp->chgBit(c+12561,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])); - vcdp->chgBit(c+12569,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+12577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U])))); - vcdp->chgBit(c+12585,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+12593,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U])); - vcdp->chgBit(c+12601,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])); - vcdp->chgBit(c+12609,((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBus(c+12617,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+12625,((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+12633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+12641,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+12649,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBit(c+12657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+12665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+12673,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+12681,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+12689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+12697,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))))); - vcdp->chgBit(c+12705,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+12713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+12721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+12729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->chgBit(c+12737,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+12745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+12753,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+12769,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+12777,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+12817,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+12825,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->chgBus(c+12833,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->chgBus(c+12841,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1439[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1439[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1439[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1439[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+12849,(__Vtemp1439),120); - __Vtemp1440[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1440[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1440[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1440[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+12881,(__Vtemp1440),128); - vcdp->chgQuad(c+12913,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+12929,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+12937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+12945,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & - VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+12953,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+13033,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+13041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+13049,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+13057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+13121,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+13129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])); - vcdp->chgBus(c+13137,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1 - [0U]),32); - __Vtemp1441[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1441[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1441[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1441[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->chgArray(c+13145,(__Vtemp1441),128); - vcdp->chgBus(c+13177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->chgBit(c+13185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+13193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+13201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+13209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+13217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+13249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+13257,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+13265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->chgBus(c+13273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1442[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1442[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1442[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1442[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->chgArray(c+13281,(__Vtemp1442),128); - vcdp->chgBit(c+13313,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); 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- vcdp->chgBit(c+13433,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+13441,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+13449,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+13457,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+13465,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+13473,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+13481,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+13489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+13537,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+13617,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+13625,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+13633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+13649,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+13657,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+13673,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+13681,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+13713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+13737,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+13745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+13801,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+13857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->chgBit(c+13865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+13873,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+13881,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))))); - vcdp->chgBus(c+13889,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+13897,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+13905,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1443[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1443[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1443[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1443[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+13913,(__Vtemp1443),128); - vcdp->chgBit(c+13945,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+13953,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+13961,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+13969,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+13977,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+13985,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->chgBus(c+13993,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+14001,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->chgBit(c+14009,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+14017,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+14025,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+14033,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+14041,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))); - vcdp->chgBit(c+14049,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+14121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+14129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+14137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+14145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+14153,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+14161,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+14169,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & ( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->chgBus(c+14177,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1448[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1448[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1448[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1448[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+14185,(__Vtemp1448),128); - vcdp->chgQuad(c+14217,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+14233,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->chgBit(c+14241,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->chgBit(c+14249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->chgBit(c+14257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+14265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+14273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+14281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+14289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+14305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+14337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+14345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+14353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1454[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1454[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1454[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1454[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgBus(c+14361,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U : (__Vtemp1454[ - ((IData)(1U) - + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << ((IData)(0x20U) - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp1454[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))),32); - __Vtemp1455[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1455[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1455[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1455[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgArray(c+14369,(__Vtemp1455),128); - vcdp->chgBus(c+14401,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+14409,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+14417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+14425,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); - vcdp->chgQuad(c+14433,((VL_ULL(0x3ffffffffff) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 7U))),42); - vcdp->chgBus(c+14449,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U]))),2); - vcdp->chgBit(c+14457,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U))))); - vcdp->chgBus(c+14465,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U)))),4); - vcdp->chgBit(c+14473,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+14481,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])); - vcdp->chgBit(c+14489,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])); - vcdp->chgBit(c+14497,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+14505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U])))); - vcdp->chgBit(c+14513,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+14521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U])); - vcdp->chgBit(c+14529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])); - vcdp->chgBit(c+14537,((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBus(c+14545,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+14553,((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+14561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+14569,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+14577,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBit(c+14585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+14593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+14601,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+14609,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+14617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+14625,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))))); - vcdp->chgBit(c+14633,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+14641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+14649,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+14657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->chgBit(c+14665,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+14673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+14681,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+14697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+14705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+14745,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+14753,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->chgBus(c+14761,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->chgBus(c+14769,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1458[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1458[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1458[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1458[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+14777,(__Vtemp1458),120); - __Vtemp1459[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1459[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1459[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1459[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+14809,(__Vtemp1459),128); - vcdp->chgQuad(c+14841,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+14857,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+14873,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & - VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+14881,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+14961,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+14969,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+14977,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+14985,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+15049,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+15057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])); - vcdp->chgBus(c+15065,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1 - [0U]),32); - __Vtemp1460[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1460[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1460[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1460[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->chgArray(c+15073,(__Vtemp1460),128); - vcdp->chgBus(c+15105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->chgBit(c+15113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+15121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+15129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+15137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+15145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+15177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+15185,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+15193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->chgBus(c+15201,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1461[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1461[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1461[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1461[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->chgArray(c+15209,(__Vtemp1461),128); - vcdp->chgBit(c+15241,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->chgBit(c+15249,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->chgBus(c+15257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->chgArray(c+15265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->chgBit(c+15297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->chgBit(c+15305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->chgBit(c+15313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->chgBus(c+15321,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->chgBus(c+15329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->chgBit(c+15337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->chgBit(c+15345,((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+15353,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->chgBit(c+15361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+15369,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+15377,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+15385,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+15393,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+15401,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+15409,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+15417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+15465,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+15545,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+15553,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+15585,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+15601,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+15609,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+15617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+15641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+15673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+15729,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+15785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->chgBit(c+15793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+15801,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+15809,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))))); - vcdp->chgBus(c+15817,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+15825,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+15833,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1462[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1462[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1462[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1462[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+15841,(__Vtemp1462),128); - vcdp->chgBit(c+15873,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+15881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+15889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+15897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+15905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+15913,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->chgBus(c+15921,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+15929,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->chgBit(c+15937,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+15945,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+15953,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+15961,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+15969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))); - vcdp->chgBit(c+15977,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+15985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+15993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+16001,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+16009,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+16017,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+16025,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+16033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+16041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+16049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+16057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+16065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+16073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+16081,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+16089,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+16097,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & ( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->chgBus(c+16105,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1467[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1467[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1467[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1467[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+16113,(__Vtemp1467),128); - vcdp->chgQuad(c+16145,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+16161,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->chgBit(c+16169,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->chgBit(c+16177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->chgBit(c+16185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+16193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+16201,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+16209,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+16217,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+16233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+16265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+16273,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+16281,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1473[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1473[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1473[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1473[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgBus(c+16289,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U : (__Vtemp1473[ - ((IData)(1U) - + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << ((IData)(0x20U) - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp1473[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))),32); - __Vtemp1474[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1474[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1474[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1474[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgArray(c+16297,(__Vtemp1474),128); - vcdp->chgBus(c+16329,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+16337,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+16345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+16353,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); - vcdp->chgQuad(c+16361,((VL_ULL(0x3ffffffffff) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 7U))),42); - vcdp->chgBus(c+16377,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U]))),2); - vcdp->chgBit(c+16385,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U))))); - vcdp->chgBus(c+16393,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U)))),4); - vcdp->chgBit(c+16401,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+16409,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])); - vcdp->chgBit(c+16417,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])); - vcdp->chgBit(c+16425,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+16433,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U])))); - vcdp->chgBit(c+16441,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+16449,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U])); - vcdp->chgBit(c+16457,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])); - vcdp->chgBit(c+16465,((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBus(c+16473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+16481,((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+16489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+16497,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+16505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBit(c+16513,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+16521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+16529,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+16537,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+16545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+16553,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))))); - vcdp->chgBit(c+16561,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+16569,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+16577,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+16585,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->chgBit(c+16593,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+16601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+16609,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+16625,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+16633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+16673,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+16681,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->chgBus(c+16689,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->chgBus(c+16697,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1477[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1477[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1477[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1477[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+16705,(__Vtemp1477),120); - __Vtemp1478[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1478[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1478[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1478[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+16737,(__Vtemp1478),128); - vcdp->chgQuad(c+16769,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+16785,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+16793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+16801,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & - VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+16809,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+16889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+16897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+16905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+16913,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+16977,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+16985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])); - vcdp->chgBus(c+16993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1 - [0U]),32); - __Vtemp1479[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1479[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1479[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1479[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->chgArray(c+17001,(__Vtemp1479),128); - vcdp->chgBus(c+17033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->chgBit(c+17041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+17049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+17057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+17065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+17073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+17105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+17113,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+17121,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->chgBus(c+17129,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1480[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1480[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1480[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1480[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->chgArray(c+17137,(__Vtemp1480),128); - vcdp->chgBit(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->chgBit(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->chgBus(c+17185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->chgArray(c+17193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->chgBit(c+17225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->chgBit(c+17233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->chgBit(c+17241,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->chgBus(c+17249,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->chgBus(c+17257,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->chgBit(c+17265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->chgBit(c+17273,((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+17281,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->chgBit(c+17289,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+17297,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+17305,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+17313,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+17321,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+17329,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+17337,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+17345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+17393,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+17473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+17481,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+17489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+17497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+17505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+17513,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+17529,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+17537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+17593,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+17601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+17657,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+17713,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->chgBit(c+17721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)); - vcdp->chgBus(c+17729,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->chgBit(c+17737,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))))); - vcdp->chgBus(c+17745,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->chgBit(c+17753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->chgBus(c+17761,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1481[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1481[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1481[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1481[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->chgArray(c+17769,(__Vtemp1481),128); - vcdp->chgBit(c+17801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)); - vcdp->chgBit(c+17809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->chgBit(c+17817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->chgBus(c+17825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->chgBit(c+17833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->chgBus(c+17841,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->chgBus(c+17849,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->chgBus(c+17857,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->chgBit(c+17865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->chgBit(c+17873,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->chgBit(c+17881,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->chgBit(c+17889,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->chgBit(c+17897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))); - vcdp->chgBit(c+17905,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->chgBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->chgBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->chgBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->chgBit(c+17937,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->chgBit(c+17945,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->chgBit(c+17953,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->chgBit(c+17961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->chgBit(c+17969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->chgBit(c+17977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->chgBit(c+17985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->chgBit(c+17993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->chgBit(c+18001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->chgBit(c+18009,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->chgBus(c+18017,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->chgBus(c+18025,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & ( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->chgBus(c+18033,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1486[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1486[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1486[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1486[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->chgArray(c+18041,(__Vtemp1486),128); - vcdp->chgQuad(c+18073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) : VL_ULL(0))))),49); - vcdp->chgBit(c+18089,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->chgBit(c+18097,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->chgBit(c+18105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->chgBit(c+18113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->chgBus(c+18121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->chgBus(c+18129,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->chgBus(c+18137,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->chgQuad(c+18145,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->chgArray(c+18161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->chgBit(c+18193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->chgBit(c+18201,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->chgBit(c+18209,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1492[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1492[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1492[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1492[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgBus(c+18217,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))) - ? 0U : (__Vtemp1492[ - ((IData)(1U) - + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]))] - << ((IData)(0x20U) - - (0x1fU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))) - | (__Vtemp1492[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U])] - >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U] - << 5U))))),32); - __Vtemp1493[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1493[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1493[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1493[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->chgArray(c+18225,(__Vtemp1493),128); - vcdp->chgBus(c+18257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->chgBit(c+18265,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e)); - vcdp->chgBit(c+18273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->chgBus(c+18281,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); - vcdp->chgQuad(c+18289,((VL_ULL(0x3ffffffffff) - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 7U))),42); - vcdp->chgBus(c+18305,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U]))),2); - vcdp->chgBit(c+18313,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] >> 6U))))); - vcdp->chgBus(c+18321,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1 - [0U] - >> 2U)))),4); - vcdp->chgBit(c+18329,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->chgBit(c+18337,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])); - vcdp->chgBit(c+18345,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1 - [0U])); - vcdp->chgBit(c+18353,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->chgBit(c+18361,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U])))); - vcdp->chgBit(c+18369,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->chgBit(c+18377,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U])); - vcdp->chgBit(c+18385,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])); - vcdp->chgBit(c+18393,((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBus(c+18401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->chgBit(c+18409,((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+18417,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->chgBit(c+18425,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->chgBit(c+18433,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->chgBit(c+18441,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->chgBit(c+18449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add)); - vcdp->chgBit(c+18457,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->chgBit(c+18465,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+18473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->chgBit(c+18481,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & (~ - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))))); - vcdp->chgBit(c+18489,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->chgBit(c+18497,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->chgBit(c+18505,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->chgBit(c+18513,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->chgBit(c+18521,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->chgBit(c+18529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->chgQuad(c+18537,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->chgBit(c+18553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->chgArray(c+18561,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->chgBit(c+18601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->chgBus(c+18609,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->chgBus(c+18617,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->chgBus(c+18625,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1496[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1496[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1496[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1496[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->chgArray(c+18633,(__Vtemp1496),120); - __Vtemp1497[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1497[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1497[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1497[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->chgArray(c+18665,(__Vtemp1497),128); - vcdp->chgQuad(c+18697,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->chgBit(c+18713,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->chgBit(c+18721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->chgBus(c+18729,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) & - VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->chgArray(c+18737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->chgBit(c+18817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->chgBus(c+18825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->chgBus(c+18833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->chgArray(c+18841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->chgBus(c+18905,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->chgBit(c+18913,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])); - vcdp->chgBus(c+18921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1 - [0U]),32); - __Vtemp1498[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1498[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1498[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1498[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->chgArray(c+18929,(__Vtemp1498),128); - vcdp->chgBus(c+18961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->chgBit(c+18969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->chgBit(c+18977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->chgBus(c+18985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->chgBus(c+18993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->chgArray(c+19001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->chgBit(c+19033,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBit(c+19041,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->chgBus(c+19049,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->chgBus(c+19057,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1499[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1499[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1499[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1499[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->chgArray(c+19065,(__Vtemp1499),128); - vcdp->chgBit(c+19097,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->chgBit(c+19105,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->chgBus(c+19113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->chgArray(c+19121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->chgBit(c+19153,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->chgBit(c+19161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->chgBit(c+19169,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->chgBus(c+19177,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->chgBus(c+19185,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->chgBit(c+19193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->chgBit(c+19201,((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->chgBit(c+19209,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->chgBit(c+19217,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->chgBit(c+19225,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->chgBit(c+19233,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+19241,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+19249,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+19257,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->chgBit(c+19265,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->chgArray(c+19273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->chgArray(c+19321,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->chgBus(c+19401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->chgBus(c+19409,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->chgBus(c+19417,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->chgBit(c+19425,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->chgBit(c+19433,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->chgBit(c+19441,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->chgBit(c+19449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->chgBit(c+19457,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->chgBit(c+19465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->chgArray(c+19473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->chgArray(c+19497,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->chgBit(c+19521,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->chgArray(c+19529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->chgArray(c+19585,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->chgBit(c+19641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->chgBit(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->chgBit(c+9641,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->chgBit(c+9649,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9657,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9665,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9673,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->chgBit(c+9681,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->chgArray(c+9689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->chgArray(c+9737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->chgBus(c+9817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->chgBus(c+9825,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->chgBus(c+9833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->chgBit(c+9841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->chgBit(c+9849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->chgBit(c+9857,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->chgBit(c+9865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->chgBit(c+9873,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->chgBit(c+9881,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->chgArray(c+9889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->chgArray(c+9913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->chgBit(c+9937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->chgArray(c+9945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->chgArray(c+10001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->chgBit(c+10057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); } } @@ -5332,270 +2777,91 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc int c = code; if (0 && vcdp && c) {} // Prevent unused // Variables - WData/*127:0*/ __Vtemp1508[4]; - WData/*127:0*/ __Vtemp1509[4]; - WData/*127:0*/ __Vtemp1510[4]; - WData/*127:0*/ __Vtemp1511[4]; - WData/*127:0*/ __Vtemp1512[4]; - WData/*127:0*/ __Vtemp1513[4]; - WData/*127:0*/ __Vtemp1514[4]; - WData/*127:0*/ __Vtemp1515[4]; - WData/*127:0*/ __Vtemp1516[4]; - WData/*127:0*/ __Vtemp1517[4]; - WData/*127:0*/ __Vtemp1518[4]; - WData/*127:0*/ __Vtemp1519[4]; - WData/*127:0*/ __Vtemp1520[4]; - WData/*127:0*/ __Vtemp1521[4]; - WData/*127:0*/ __Vtemp1522[4]; - WData/*127:0*/ __Vtemp1523[4]; - WData/*127:0*/ __Vtemp1532[4]; - WData/*127:0*/ __Vtemp1533[4]; - WData/*127:0*/ __Vtemp1534[4]; - WData/*127:0*/ __Vtemp1535[4]; - WData/*127:0*/ __Vtemp1536[4]; - WData/*127:0*/ __Vtemp1537[4]; - WData/*127:0*/ __Vtemp1538[4]; - WData/*127:0*/ __Vtemp1539[4]; - WData/*127:0*/ __Vtemp1540[4]; - WData/*127:0*/ __Vtemp1541[4]; - WData/*127:0*/ __Vtemp1542[4]; - WData/*127:0*/ __Vtemp1543[4]; - WData/*127:0*/ __Vtemp1544[4]; - WData/*127:0*/ __Vtemp1545[4]; - WData/*127:0*/ __Vtemp1546[4]; - WData/*127:0*/ __Vtemp1547[4]; - WData/*127:0*/ __Vtemp1556[4]; - WData/*127:0*/ __Vtemp1557[4]; - WData/*127:0*/ __Vtemp1558[4]; - WData/*127:0*/ __Vtemp1559[4]; - WData/*127:0*/ __Vtemp1560[4]; - WData/*127:0*/ __Vtemp1561[4]; - WData/*127:0*/ __Vtemp1562[4]; - WData/*127:0*/ __Vtemp1563[4]; - WData/*127:0*/ __Vtemp1564[4]; - WData/*127:0*/ __Vtemp1565[4]; - WData/*127:0*/ __Vtemp1566[4]; - WData/*127:0*/ __Vtemp1567[4]; - WData/*127:0*/ __Vtemp1568[4]; - WData/*127:0*/ __Vtemp1569[4]; - WData/*127:0*/ __Vtemp1570[4]; - WData/*127:0*/ __Vtemp1571[4]; - WData/*127:0*/ __Vtemp1580[4]; - WData/*127:0*/ __Vtemp1581[4]; - WData/*127:0*/ __Vtemp1582[4]; - WData/*127:0*/ __Vtemp1583[4]; - WData/*127:0*/ __Vtemp1584[4]; - WData/*127:0*/ __Vtemp1585[4]; - WData/*127:0*/ __Vtemp1586[4]; - WData/*127:0*/ __Vtemp1587[4]; - WData/*127:0*/ __Vtemp1588[4]; - WData/*127:0*/ __Vtemp1589[4]; - WData/*127:0*/ __Vtemp1590[4]; - WData/*127:0*/ __Vtemp1591[4]; - WData/*127:0*/ __Vtemp1592[4]; - WData/*127:0*/ __Vtemp1593[4]; - WData/*127:0*/ __Vtemp1594[4]; - WData/*127:0*/ __Vtemp1595[4]; - WData/*127:0*/ __Vtemp1604[4]; - WData/*127:0*/ __Vtemp1605[4]; - WData/*127:0*/ __Vtemp1606[4]; - WData/*127:0*/ __Vtemp1607[4]; - WData/*127:0*/ __Vtemp1608[4]; - WData/*127:0*/ __Vtemp1609[4]; - WData/*127:0*/ __Vtemp1610[4]; - WData/*127:0*/ __Vtemp1611[4]; - WData/*127:0*/ __Vtemp1612[4]; - WData/*127:0*/ __Vtemp1613[4]; - WData/*127:0*/ __Vtemp1614[4]; - WData/*127:0*/ __Vtemp1615[4]; - WData/*127:0*/ __Vtemp1616[4]; - WData/*127:0*/ __Vtemp1617[4]; - WData/*127:0*/ __Vtemp1618[4]; - WData/*127:0*/ __Vtemp1619[4]; - WData/*127:0*/ __Vtemp1628[4]; - WData/*127:0*/ __Vtemp1629[4]; - WData/*127:0*/ __Vtemp1630[4]; - WData/*127:0*/ __Vtemp1631[4]; - WData/*127:0*/ __Vtemp1632[4]; - WData/*127:0*/ __Vtemp1633[4]; - WData/*127:0*/ __Vtemp1634[4]; - WData/*127:0*/ __Vtemp1635[4]; - WData/*127:0*/ __Vtemp1636[4]; - WData/*127:0*/ __Vtemp1637[4]; - WData/*127:0*/ __Vtemp1638[4]; - WData/*127:0*/ __Vtemp1639[4]; - WData/*127:0*/ __Vtemp1640[4]; - WData/*127:0*/ __Vtemp1641[4]; - WData/*127:0*/ __Vtemp1642[4]; - WData/*127:0*/ __Vtemp1643[4]; - WData/*127:0*/ __Vtemp1652[4]; - WData/*127:0*/ __Vtemp1653[4]; - WData/*127:0*/ __Vtemp1654[4]; - WData/*127:0*/ __Vtemp1655[4]; - WData/*127:0*/ __Vtemp1656[4]; - WData/*127:0*/ __Vtemp1657[4]; - WData/*127:0*/ __Vtemp1658[4]; - WData/*127:0*/ __Vtemp1659[4]; - WData/*127:0*/ __Vtemp1660[4]; - WData/*127:0*/ __Vtemp1661[4]; - WData/*127:0*/ __Vtemp1662[4]; - WData/*127:0*/ __Vtemp1663[4]; - WData/*127:0*/ __Vtemp1664[4]; - WData/*127:0*/ __Vtemp1665[4]; - WData/*127:0*/ __Vtemp1666[4]; - WData/*127:0*/ __Vtemp1667[4]; - WData/*127:0*/ __Vtemp1676[4]; - WData/*127:0*/ __Vtemp1677[4]; - WData/*127:0*/ __Vtemp1678[4]; - WData/*127:0*/ __Vtemp1679[4]; - WData/*127:0*/ __Vtemp1680[4]; - WData/*127:0*/ __Vtemp1681[4]; - WData/*127:0*/ __Vtemp1682[4]; - WData/*127:0*/ __Vtemp1683[4]; - WData/*127:0*/ __Vtemp1684[4]; - WData/*127:0*/ __Vtemp1685[4]; - WData/*127:0*/ __Vtemp1686[4]; - WData/*127:0*/ __Vtemp1687[4]; - WData/*127:0*/ __Vtemp1688[4]; - WData/*127:0*/ __Vtemp1689[4]; - WData/*127:0*/ __Vtemp1690[4]; - WData/*127:0*/ __Vtemp1691[4]; - WData/*127:0*/ __Vtemp1507[4]; - WData/*127:0*/ __Vtemp1531[4]; - WData/*127:0*/ __Vtemp1555[4]; - WData/*127:0*/ __Vtemp1579[4]; - WData/*127:0*/ __Vtemp1603[4]; - WData/*127:0*/ __Vtemp1627[4]; - WData/*127:0*/ __Vtemp1651[4]; - WData/*127:0*/ __Vtemp1675[4]; + WData/*127:0*/ __Vtemp727[4]; + WData/*127:0*/ __Vtemp735[4]; + WData/*127:0*/ __Vtemp743[4]; + WData/*127:0*/ __Vtemp751[4]; // Body { - vcdp->chgBit(c+19649,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19657,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19665,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19673,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + vcdp->chgBit(c+10065,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10073,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10081,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10089,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19681,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19689,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19697,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19713,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + >> 0x19U)))),26); + vcdp->chgBit(c+10097,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10105,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10113,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10121,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10129,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19721,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19729,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19737,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19745,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19753,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + >> 0x19U)))),26); + vcdp->chgBit(c+10137,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10145,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10153,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10161,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10169,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19761,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19769,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19777,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19785,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19793,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + >> 0x19U)))),26); + vcdp->chgBit(c+10177,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10185,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10193,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->chgBit(c+10201,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10209,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19801,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19817,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19825,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19833,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19841,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19849,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19857,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19865,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19873,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19889,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19897,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19905,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19913,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19921,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19929,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19937,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBit(c+19945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->chgBit(c+19961,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBit(c+19969,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->chgBus(c+19977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); - vcdp->chgBit(c+19985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBus(c+19993,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); - vcdp->chgBit(c+20001,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->chgBus(c+20009,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r)),28); - vcdp->chgBit(c+20017,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+20025,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+20033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); - vcdp->chgBus(c+20041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[0]),28); - vcdp->chgBus(c+20042,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[1]),28); - vcdp->chgBus(c+20057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),28); - vcdp->chgBus(c+20065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),28); - vcdp->chgBit(c+20073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)); - vcdp->chgBit(c+20081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)); - vcdp->chgBit(c+20089,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)); - vcdp->chgBit(c+20097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+20105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),8); - vcdp->chgArray(c+20113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),224); - vcdp->chgBit(c+20169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+20177,((1U & (~ (IData)((0U + >> 0x19U)))),26); + vcdp->chgBit(c+10217,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBit(c+10225,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->chgBus(c+10233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); + vcdp->chgBit(c+10241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+10249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); + vcdp->chgBit(c+10257,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->chgBus(c+10265,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r),28); + vcdp->chgBit(c+10273,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); + vcdp->chgBit(c+10281,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->chgBus(c+10289,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),4); + vcdp->chgArray(c+10297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),112); + vcdp->chgBit(c+10329,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10337,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))))); - vcdp->chgBus(c+20185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),4); - vcdp->chgArray(c+20193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),232); - vcdp->chgArray(c+20201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),232); - vcdp->chgArray(c+20209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),232); - vcdp->chgArray(c+20217,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),232); - vcdp->chgArray(c+20225,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[4]),232); - vcdp->chgArray(c+20233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[5]),232); - vcdp->chgArray(c+20241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[6]),232); - vcdp->chgArray(c+20249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[7]),232); - vcdp->chgArray(c+20705,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),232); - vcdp->chgArray(c+20769,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),232); - vcdp->chgBus(c+20833,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->chgBus(c+20841,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->chgBus(c+20849,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->chgBit(c+20857,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+20865,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),8); - vcdp->chgBit(c+20873,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); - vcdp->chgBus(c+20881,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),8); - vcdp->chgBit(c+20889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+20897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+20905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+20913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+20921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgQuad(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->chgBit(c+20945,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBit(c+20953,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+20961,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+10345,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),3); + vcdp->chgArray(c+10353,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),116); + vcdp->chgArray(c+10357,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),116); + vcdp->chgArray(c+10361,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),116); + vcdp->chgArray(c+10365,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),116); + vcdp->chgArray(c+10481,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),116); + vcdp->chgArray(c+10513,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),116); + vcdp->chgBus(c+10545,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+10553,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+10561,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+10569,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+10577,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),4); + vcdp->chgBit(c+10585,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); + vcdp->chgBus(c+10593,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),4); + vcdp->chgBit(c+10601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+10617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+10625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+10633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+10641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+10657,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+10665,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+10673,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->chgBus(c+20969,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) + vcdp->chgBus(c+10681,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U + ? (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -5603,37 +2869,37 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+20977,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->chgBus(c+10689,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->chgBus(c+20985,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+10697,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->chgQuad(c+20993,((VL_ULL(0x3ffffffffff) + vcdp->chgQuad(c+10705,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -5645,19 +2911,19 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->chgBus(c+21009,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+10721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->chgBit(c+21017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+10729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->chgBit(c+21025,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+10737,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+21033,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+21041,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+10745,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+10753,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -5666,422 +2932,222 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->chgBit(c+21057,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->chgBit(c+10769,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->chgBus(c+21065,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->chgBus(c+10777,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->chgBit(c+21073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+10785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->chgBit(c+21081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+10793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->chgBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->chgBus(c+21097,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->chgBus(c+21105,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1507[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1507[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1507[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1507[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+21113,(__Vtemp1507),128); - vcdp->chgBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+10801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+10809,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+10817,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp727[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp727[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp727[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp727[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+10825,(__Vtemp727),128); + vcdp->chgBit(c+10857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->chgBit(c+21153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBit(c+10865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->chgBus(c+21161,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+10873,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); 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+ vcdp->chgBit(c+12097,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+12105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+12113,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+12121,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+12129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+12161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+12193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+12201,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); 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- __Vtemp1509[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1509[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1509[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->chgArray(c+23433,(__Vtemp1509),128); - __Vtemp1510[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1510[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1510[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1510[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; 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+ vcdp->chgArray(c+13521,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+13524,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+13527,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+13530,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+13617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+13673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+13681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+13697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+13705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+13712,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+13719,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+13726,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+13929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+13985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+14041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+14049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+14129,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+14137,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+14145,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->chgBus(c+25609,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) + vcdp->chgBus(c+14153,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U + ? (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -6089,37 +3155,37 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+25617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->chgBus(c+14161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->chgBus(c+25625,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+14169,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->chgQuad(c+25633,((VL_ULL(0x3ffffffffff) + vcdp->chgQuad(c+14177,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -6131,19 +3197,19 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->chgBus(c+25649,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+14193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->chgBit(c+25657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+14201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->chgBit(c+25665,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+14209,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+25673,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+25681,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+14217,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+14225,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -6152,422 +3218,222 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->chgBit(c+25697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->chgBit(c+14241,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->chgBus(c+25705,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->chgBus(c+14249,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->chgBit(c+25713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+14257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->chgBit(c+25721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+14265,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->chgBus(c+25729,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->chgBus(c+25737,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->chgBus(c+25745,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1531[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1531[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1531[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1531[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+25753,(__Vtemp1531),128); - vcdp->chgBit(c+25785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+14273,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+14281,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+14289,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp735[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp735[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp735[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp735[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+14297,(__Vtemp735),128); + vcdp->chgBit(c+14329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->chgBit(c+25793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBit(c+14337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->chgBus(c+25801,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+14345,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); - vcdp->chgQuad(c+25809,((VL_ULL(0x1ffffffffffff) + vcdp->chgQuad(c+14353,((VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->chgBus(c+25825,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->chgBit(c+25833,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBus(c+14369,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->chgBit(c+14377,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U)))); - vcdp->chgBit(c+25841,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+14385,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vcdp->chgBit(c+25849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+14393,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x16U)))); - vcdp->chgBit(c+25857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+14401,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U)))); - vcdp->chgBit(c+25865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+14409,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)))); 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- vcdp->chgBus(c+25921,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->chgBus(c+25929,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->chgBit(c+14433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+14449,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+14457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+14465,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->chgBus(c+14473,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))),28); - vcdp->chgBit(c+25937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->chgBus(c+25945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->chgQuad(c+25953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->chgQuad(c+25955,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->chgQuad(c+25957,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->chgQuad(c+25959,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->chgQuad(c+25961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->chgQuad(c+25963,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->chgQuad(c+25965,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->chgQuad(c+25967,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->chgQuad(c+25969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->chgQuad(c+25971,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->chgQuad(c+25973,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->chgQuad(c+25975,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->chgQuad(c+25977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->chgQuad(c+25979,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->chgQuad(c+25981,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->chgQuad(c+25983,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->chgQuad(c+26209,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->chgQuad(c+26225,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); 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+ vcdp->chgQuad(c+14507,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->chgQuad(c+14509,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->chgQuad(c+14511,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->chgQuad(c+14513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->chgQuad(c+14515,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->chgQuad(c+14517,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->chgQuad(c+14519,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->chgQuad(c+14521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->chgQuad(c+14523,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->chgQuad(c+14525,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->chgQuad(c+14527,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->chgQuad(c+14753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->chgQuad(c+14769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->chgBus(c+14785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+14793,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); 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+ vcdp->chgArray(c+14850,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->chgArray(c+14855,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->chgArray(c+14860,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->chgArray(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->chgArray(c+14870,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->chgArray(c+14875,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->chgArray(c+14880,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->chgArray(c+14885,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->chgArray(c+14890,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->chgArray(c+14895,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->chgArray(c+14900,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->chgArray(c+15465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->chgArray(c+15505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->chgBus(c+15545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+15553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+15585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+15601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+15633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+15673,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); 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- __Vtemp1533[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1533[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1533[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->chgArray(c+28073,(__Vtemp1533),128); - __Vtemp1534[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1534[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1534[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1534[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; 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+ vcdp->chgArray(c+16993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+16996,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+16999,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+17002,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+17089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+17113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+17137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+17145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+17153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+17161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+17184,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+17191,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+17198,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+17401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+17457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+17513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+17529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+17537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+17561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+17577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+17585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+17601,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+17609,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+17617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->chgBus(c+30249,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) + vcdp->chgBus(c+17625,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U + ? (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -6575,37 +3441,37 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+30257,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->chgBus(c+17633,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->chgBus(c+30265,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+17641,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->chgQuad(c+30273,((VL_ULL(0x3ffffffffff) + vcdp->chgQuad(c+17649,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -6617,19 +3483,19 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->chgBus(c+30289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+17665,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->chgBit(c+30297,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+17673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->chgBit(c+30305,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+17681,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+30313,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+30321,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+17689,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+17697,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -6638,422 +3504,222 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->chgBit(c+30337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->chgBit(c+17713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->chgBus(c+30345,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->chgBus(c+17721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->chgBit(c+30353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+17729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->chgBit(c+30361,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+17737,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->chgBus(c+30369,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->chgBus(c+30377,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->chgBus(c+30385,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1555[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1555[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1555[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1555[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+30393,(__Vtemp1555),128); - vcdp->chgBit(c+30425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+17745,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+17753,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+17761,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp743[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp743[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp743[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp743[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+17769,(__Vtemp743),128); + vcdp->chgBit(c+17801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->chgBit(c+30433,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBit(c+17809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->chgBus(c+30441,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+17817,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); - vcdp->chgQuad(c+30449,((VL_ULL(0x1ffffffffffff) + vcdp->chgQuad(c+17825,((VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->chgBus(c+30465,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->chgBit(c+30473,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBus(c+17841,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->chgBit(c+17849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U)))); - vcdp->chgBit(c+30481,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+17857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vcdp->chgBit(c+30489,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+17865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x16U)))); - vcdp->chgBit(c+30497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+17873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U)))); - vcdp->chgBit(c+30505,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+17881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)))); 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- vcdp->chgBus(c+30561,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->chgBus(c+30569,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->chgBit(c+17905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+17937,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->chgBus(c+17945,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))),28); - vcdp->chgBit(c+30577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->chgBus(c+30585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->chgQuad(c+30593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->chgQuad(c+30595,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->chgQuad(c+30597,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->chgQuad(c+30599,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->chgQuad(c+30601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->chgQuad(c+30603,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->chgQuad(c+30605,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->chgQuad(c+30607,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->chgQuad(c+30609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->chgQuad(c+30611,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->chgQuad(c+30613,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->chgQuad(c+30615,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->chgQuad(c+30617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->chgQuad(c+30619,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->chgQuad(c+30621,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->chgQuad(c+30623,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->chgQuad(c+30849,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->chgQuad(c+30865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->chgBus(c+30881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->chgBus(c+30889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->chgBus(c+30897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->chgBit(c+30905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+30913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); - vcdp->chgArray(c+30921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); - vcdp->chgArray(c+30926,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); - vcdp->chgArray(c+30931,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); - vcdp->chgArray(c+30936,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); - vcdp->chgArray(c+30941,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); - vcdp->chgArray(c+30946,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); - vcdp->chgArray(c+30951,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); - vcdp->chgArray(c+30956,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); - vcdp->chgArray(c+30961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); - vcdp->chgArray(c+30966,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); - vcdp->chgArray(c+30971,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); - vcdp->chgArray(c+30976,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); - vcdp->chgArray(c+30981,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); - vcdp->chgArray(c+30986,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); - vcdp->chgArray(c+30991,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); - vcdp->chgArray(c+30996,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); - vcdp->chgArray(c+31561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); - vcdp->chgArray(c+31601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); - vcdp->chgBus(c+31641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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+ vcdp->chgArray(c+18322,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->chgArray(c+18327,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->chgArray(c+18332,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->chgArray(c+18337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->chgArray(c+18342,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->chgArray(c+18347,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->chgArray(c+18352,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->chgArray(c+18357,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->chgArray(c+18362,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->chgArray(c+18367,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->chgArray(c+18372,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->chgArray(c+18937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->chgArray(c+18977,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->chgBus(c+19017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+19025,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+19033,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+19041,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+19049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+19057,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+19065,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+19073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+19105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+19137,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+19145,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); 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- __Vtemp1557[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1557[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1557[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->chgArray(c+32713,(__Vtemp1557),128); - __Vtemp1558[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1558[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1558[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1558[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; 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+ vcdp->chgArray(c+20465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+20468,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+20471,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+20474,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+20561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+20585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+20609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+20617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+20625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+20633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+20641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+20649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+20656,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+20663,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+20670,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+20873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+20985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+20993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+21001,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+21009,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBit(c+21017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+21033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+21049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgQuad(c+21057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->chgBit(c+21073,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBit(c+21081,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->chgBus(c+34889,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) + vcdp->chgBus(c+21097,(((0x19fU >= (0x1ffU & + ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U + ? (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -7061,37 +3727,37 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+34897,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->chgBus(c+21105,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->chgBus(c+34905,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+21113,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->chgQuad(c+34913,((VL_ULL(0x3ffffffffff) + vcdp->chgQuad(c+21121,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -7103,19 +3769,19 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->chgBus(c+34929,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBus(c+21137,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->chgBit(c+34937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->chgBit(c+34945,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->chgBit(c+21153,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+34953,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+34961,((VL_ULL(0x3ffffffffff) + vcdp->chgBus(c+21161,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->chgQuad(c+21169,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -7124,2346 +3790,202 @@ void VVX_cache::traceChgThis__5(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->chgBit(c+34977,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->chgBit(c+21185,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->chgBus(c+34985,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->chgBus(c+21193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->chgBit(c+34993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+21201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->chgBit(c+35001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+21209,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->chgBus(c+35009,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->chgBus(c+35017,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->chgBus(c+35025,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1579[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1579[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1579[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1579[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+35033,(__Vtemp1579),128); - vcdp->chgBit(c+35065,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+21217,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->chgBus(c+21225,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->chgBus(c+21233,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp751[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp751[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp751[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp751[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->chgArray(c+21241,(__Vtemp751),128); + vcdp->chgBit(c+21273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->chgBit(c+35073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBit(c+21281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->chgBus(c+35081,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->chgBus(c+21289,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); - vcdp->chgQuad(c+35089,((VL_ULL(0x1ffffffffffff) + vcdp->chgQuad(c+21297,((VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->chgBus(c+35105,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->chgBit(c+35113,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBus(c+21313,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->chgBit(c+21321,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U)))); - vcdp->chgBit(c+35121,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+21329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vcdp->chgBit(c+35129,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+21337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x16U)))); - vcdp->chgBit(c+35137,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+21345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U)))); - vcdp->chgBit(c+35145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->chgBit(c+21353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)))); 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- vcdp->chgBus(c+35201,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->chgBus(c+35209,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->chgBit(c+21377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBit(c+21393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+21401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->chgBus(c+21409,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->chgBus(c+21417,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))),28); - vcdp->chgBit(c+35217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->chgBus(c+35225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->chgQuad(c+35233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->chgQuad(c+35235,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->chgQuad(c+35237,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->chgQuad(c+35239,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->chgQuad(c+35241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->chgQuad(c+35243,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->chgQuad(c+35245,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->chgQuad(c+35247,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->chgQuad(c+35249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->chgQuad(c+35251,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->chgQuad(c+35253,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->chgQuad(c+35255,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->chgQuad(c+35257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->chgQuad(c+35259,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->chgQuad(c+35261,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->chgQuad(c+35263,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->chgQuad(c+35489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->chgQuad(c+35505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); 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+ vcdp->chgArray(c+21794,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->chgArray(c+21799,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->chgArray(c+21804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->chgArray(c+21809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->chgArray(c+21814,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->chgArray(c+21819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->chgArray(c+21824,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->chgArray(c+21829,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->chgArray(c+21834,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->chgArray(c+21839,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->chgArray(c+21844,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->chgArray(c+22409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->chgArray(c+22449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->chgBus(c+22489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->chgBus(c+22497,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->chgBus(c+22505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->chgBit(c+22513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+22521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->chgBus(c+22529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->chgBus(c+22537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->chgArray(c+22545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->chgArray(c+22577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->chgBit(c+22609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->chgBit(c+22617,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); 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- __Vtemp1581[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1581[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1581[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->chgArray(c+37353,(__Vtemp1581),128); - __Vtemp1582[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1582[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1582[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1582[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; 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- vcdp->chgArray(c+38279,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); - vcdp->chgArray(c+38282,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); - vcdp->chgArray(c+38285,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); - vcdp->chgArray(c+38288,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); - vcdp->chgArray(c+38291,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); - vcdp->chgArray(c+38294,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); - vcdp->chgArray(c+38633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); - vcdp->chgBus(c+38737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); - vcdp->chgBus(c+38745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); - vcdp->chgBus(c+38753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); - vcdp->chgBus(c+38761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); - vcdp->chgBus(c+38769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); - vcdp->chgBus(c+38777,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); - vcdp->chgBit(c+38785,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+38793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); - vcdp->chgArray(c+38801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); - vcdp->chgArray(c+38804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); - vcdp->chgArray(c+38807,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); - vcdp->chgArray(c+38810,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); - vcdp->chgArray(c+38813,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); - vcdp->chgArray(c+38816,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); - vcdp->chgArray(c+38819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); - vcdp->chgArray(c+38822,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); - vcdp->chgArray(c+38993,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->chgArray(c+39017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->chgBus(c+39041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->chgBus(c+39049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->chgBus(c+39057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->chgBit(c+39065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+39073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->chgArray(c+39081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->chgArray(c+39088,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->chgArray(c+39095,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->chgArray(c+39102,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->chgArray(c+39305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->chgArray(c+39361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->chgBus(c+39417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->chgBus(c+39425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->chgBus(c+39433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->chgBit(c+39441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBit(c+39449,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+39457,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+39465,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+39473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+39481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgQuad(c+39489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->chgBit(c+39505,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBit(c+39513,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+39521,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))),2); - vcdp->chgBus(c+39529,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+39537,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->chgBus(c+39545,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->chgQuad(c+39553,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->chgBus(c+39569,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->chgBit(c+39577,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->chgBit(c+39585,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+39593,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+39601,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->chgBit(c+39617,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->chgBus(c+39625,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->chgBit(c+39633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->chgBit(c+39641,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); - vcdp->chgBus(c+39649,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->chgBus(c+39657,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->chgBus(c+39665,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1603[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1603[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1603[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1603[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+39673,(__Vtemp1603),128); - vcdp->chgBit(c+39705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->chgBit(c+39713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->chgBus(c+39721,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); - vcdp->chgQuad(c+39729,((VL_ULL(0x1ffffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->chgBus(c+39745,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->chgBit(c+39753,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U)))); - vcdp->chgBit(c+39761,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vcdp->chgBit(c+39769,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U)))); - vcdp->chgBit(c+39777,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vcdp->chgBit(c+39785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)))); - vcdp->chgBit(c+39793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)))); - vcdp->chgBit(c+39801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U)))); - vcdp->chgBit(c+39809,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+39817,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+39825,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+39833,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBus(c+39841,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->chgBus(c+39849,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))),28); - vcdp->chgBit(c+39857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->chgBus(c+39865,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->chgQuad(c+39873,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->chgQuad(c+39875,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->chgQuad(c+39877,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->chgQuad(c+39879,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->chgQuad(c+39881,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->chgQuad(c+39883,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->chgQuad(c+39885,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->chgQuad(c+39887,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->chgQuad(c+39889,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->chgQuad(c+39891,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->chgQuad(c+39893,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->chgQuad(c+39895,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->chgQuad(c+39897,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->chgQuad(c+39899,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->chgQuad(c+39901,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->chgQuad(c+39903,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->chgQuad(c+40129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->chgQuad(c+40145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->chgBus(c+40161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->chgBus(c+40169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->chgBus(c+40177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->chgBit(c+40185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+40193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); - vcdp->chgArray(c+40201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); - vcdp->chgArray(c+40206,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); - vcdp->chgArray(c+40211,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); - vcdp->chgArray(c+40216,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); - vcdp->chgArray(c+40221,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); - vcdp->chgArray(c+40226,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); - vcdp->chgArray(c+40231,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); - vcdp->chgArray(c+40236,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); - vcdp->chgArray(c+40241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); - vcdp->chgArray(c+40246,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); - vcdp->chgArray(c+40251,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); - vcdp->chgArray(c+40256,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); - vcdp->chgArray(c+40261,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); - vcdp->chgArray(c+40266,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); - vcdp->chgArray(c+40271,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); - vcdp->chgArray(c+40276,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); - vcdp->chgArray(c+40841,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); - vcdp->chgArray(c+40881,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); - vcdp->chgBus(c+40921,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->chgBus(c+40929,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->chgBus(c+40937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->chgBit(c+40945,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+40953,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); - vcdp->chgBus(c+40961,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); - vcdp->chgBus(c+40969,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); - vcdp->chgArray(c+40977,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); - vcdp->chgArray(c+41009,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); - vcdp->chgBit(c+41041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+41049,((1U & (~ (IData)((0U - != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); - vcdp->chgBus(c+41057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); - vcdp->chgArray(c+41065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); - vcdp->chgArray(c+41075,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); - vcdp->chgArray(c+41085,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); - vcdp->chgArray(c+41095,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); - vcdp->chgArray(c+41105,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); - vcdp->chgArray(c+41115,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); 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- __Vtemp1605[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1605[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1605[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->chgArray(c+41993,(__Vtemp1605),128); - __Vtemp1606[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1606[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1606[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1606[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; 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- __Vtemp1612[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1612[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1612[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->chgArray(c+42217,(__Vtemp1612),128); - __Vtemp1613[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1613[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1613[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; - __Vtemp1613[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; 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- __Vtemp1615[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->chgArray(c+42313,(__Vtemp1615),128); - __Vtemp1616[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1616[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1616[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1616[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->chgArray(c+42345,(__Vtemp1616),128); - __Vtemp1617[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1617[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1617[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1617[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->chgArray(c+42377,(__Vtemp1617),128); - __Vtemp1618[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1618[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1618[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1618[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; - vcdp->chgArray(c+42409,(__Vtemp1618),128); - __Vtemp1619[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][0U]; - __Vtemp1619[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][1U]; - __Vtemp1619[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][2U]; - __Vtemp1619[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][3U]; - vcdp->chgArray(c+42441,(__Vtemp1619),128); - vcdp->chgBus(c+42473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); - vcdp->chgBus(c+42474,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); - vcdp->chgBus(c+42475,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); - vcdp->chgBus(c+42476,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); 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- vcdp->chgBus(c+42484,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); - vcdp->chgBus(c+42485,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); - vcdp->chgBus(c+42486,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); - vcdp->chgBus(c+42487,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); - vcdp->chgBus(c+42488,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); - vcdp->chgBus(c+42601,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0U]),16); - vcdp->chgBus(c+42609,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [1U]),16); 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- vcdp->chgBus(c+42673,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [9U]),16); - vcdp->chgBus(c+42681,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xaU]),16); - vcdp->chgBus(c+42689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xbU]),16); - vcdp->chgBus(c+42697,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xcU]),16); - vcdp->chgBus(c+42705,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xdU]),16); - vcdp->chgBus(c+42713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xeU]),16); - vcdp->chgBus(c+42721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xfU]),16); - vcdp->chgBus(c+42729,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); - vcdp->chgBus(c+42737,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); - vcdp->chgBus(c+42745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); - vcdp->chgBus(c+42753,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); - vcdp->chgArray(c+42761,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); - vcdp->chgArray(c+42809,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); - vcdp->chgArray(c+42889,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); - vcdp->chgArray(c+42892,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); - vcdp->chgArray(c+42895,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); - vcdp->chgArray(c+42898,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); - vcdp->chgArray(c+42901,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); - vcdp->chgArray(c+42904,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); - vcdp->chgArray(c+42907,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); - vcdp->chgArray(c+42910,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); - vcdp->chgArray(c+42913,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); - vcdp->chgArray(c+42916,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); - vcdp->chgArray(c+42919,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); - vcdp->chgArray(c+42922,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); - vcdp->chgArray(c+42925,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); - vcdp->chgArray(c+42928,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); - vcdp->chgArray(c+42931,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); - vcdp->chgArray(c+42934,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); - vcdp->chgArray(c+43273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); - vcdp->chgBus(c+43377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); - vcdp->chgBus(c+43385,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); - vcdp->chgBus(c+43393,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); - vcdp->chgBus(c+43401,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); - vcdp->chgBus(c+43409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); - vcdp->chgBus(c+43417,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); - vcdp->chgBit(c+43425,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+43433,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); - vcdp->chgArray(c+43441,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); - vcdp->chgArray(c+43444,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); - vcdp->chgArray(c+43447,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); - vcdp->chgArray(c+43450,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); - vcdp->chgArray(c+43453,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); - vcdp->chgArray(c+43456,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); - vcdp->chgArray(c+43459,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); - vcdp->chgArray(c+43462,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); - vcdp->chgArray(c+43633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->chgArray(c+43657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->chgBus(c+43681,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->chgBus(c+43689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->chgBus(c+43697,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->chgBit(c+43705,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+43713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->chgArray(c+43721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->chgArray(c+43728,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->chgArray(c+43735,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->chgArray(c+43742,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->chgArray(c+43945,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->chgArray(c+44001,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->chgBus(c+44057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->chgBus(c+44065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->chgBus(c+44073,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->chgBit(c+44081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBit(c+44089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+44097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+44105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+44113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+44121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgQuad(c+44129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->chgBit(c+44145,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBit(c+44153,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+44161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))),2); - vcdp->chgBus(c+44169,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+44177,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->chgBus(c+44185,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->chgQuad(c+44193,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->chgBus(c+44209,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->chgBit(c+44217,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->chgBit(c+44225,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+44233,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+44241,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->chgBit(c+44257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->chgBus(c+44265,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->chgBit(c+44273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->chgBit(c+44281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); 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- __Vtemp1627[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1627[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+44313,(__Vtemp1627),128); - vcdp->chgBit(c+44345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->chgBit(c+44353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->chgBus(c+44361,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); - vcdp->chgQuad(c+44369,((VL_ULL(0x1ffffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); 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- vcdp->chgQuad(c+44537,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->chgQuad(c+44539,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->chgQuad(c+44541,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->chgQuad(c+44543,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->chgQuad(c+44769,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->chgQuad(c+44785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->chgBus(c+44801,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->chgBus(c+44809,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); 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- vcdp->chgBus(c+47124,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); - vcdp->chgBus(c+47125,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); - vcdp->chgBus(c+47126,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); - vcdp->chgBus(c+47127,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); - vcdp->chgBus(c+47128,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); - vcdp->chgBus(c+47241,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0U]),16); - vcdp->chgBus(c+47249,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [1U]),16); - vcdp->chgBus(c+47257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [2U]),16); - vcdp->chgBus(c+47265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [3U]),16); - vcdp->chgBus(c+47273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [4U]),16); - vcdp->chgBus(c+47281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [5U]),16); - vcdp->chgBus(c+47289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [6U]),16); - vcdp->chgBus(c+47297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [7U]),16); - vcdp->chgBus(c+47305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [8U]),16); - vcdp->chgBus(c+47313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [9U]),16); - vcdp->chgBus(c+47321,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xaU]),16); - vcdp->chgBus(c+47329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xbU]),16); - vcdp->chgBus(c+47337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xcU]),16); - vcdp->chgBus(c+47345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xdU]),16); - vcdp->chgBus(c+47353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xeU]),16); - vcdp->chgBus(c+47361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xfU]),16); - vcdp->chgBus(c+47369,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); - vcdp->chgBus(c+47377,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); - vcdp->chgBus(c+47385,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); - vcdp->chgBus(c+47393,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); - vcdp->chgArray(c+47401,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); - vcdp->chgArray(c+47449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); - vcdp->chgArray(c+47529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); - vcdp->chgArray(c+47532,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); - vcdp->chgArray(c+47535,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); - vcdp->chgArray(c+47538,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); - vcdp->chgArray(c+47541,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); - vcdp->chgArray(c+47544,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); - vcdp->chgArray(c+47547,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); - vcdp->chgArray(c+47550,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); - vcdp->chgArray(c+47553,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); - vcdp->chgArray(c+47556,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); - vcdp->chgArray(c+47559,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); - vcdp->chgArray(c+47562,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); - vcdp->chgArray(c+47565,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); - vcdp->chgArray(c+47568,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); - vcdp->chgArray(c+47571,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); - vcdp->chgArray(c+47574,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); - vcdp->chgArray(c+47913,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); - vcdp->chgBus(c+48017,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); - vcdp->chgBus(c+48025,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); - vcdp->chgBus(c+48033,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); - vcdp->chgBus(c+48041,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); - vcdp->chgBus(c+48049,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); - vcdp->chgBus(c+48057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); - vcdp->chgBit(c+48065,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+48073,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); - vcdp->chgArray(c+48081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); - vcdp->chgArray(c+48084,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); - vcdp->chgArray(c+48087,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); - vcdp->chgArray(c+48090,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); - vcdp->chgArray(c+48093,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); - vcdp->chgArray(c+48096,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); - vcdp->chgArray(c+48099,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); - vcdp->chgArray(c+48102,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); - vcdp->chgArray(c+48273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->chgArray(c+48297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->chgBus(c+48321,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->chgBus(c+48329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->chgBus(c+48337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->chgBit(c+48345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+48353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->chgArray(c+48361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->chgArray(c+48368,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->chgArray(c+48375,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->chgArray(c+48382,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->chgArray(c+48585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->chgArray(c+48641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->chgBus(c+48697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->chgBus(c+48705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->chgBus(c+48713,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->chgBit(c+48721,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBit(c+48729,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+48737,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+48745,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+48753,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+48761,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgQuad(c+48769,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->chgBit(c+48785,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBit(c+48793,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+48801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))),2); - vcdp->chgBus(c+48809,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+48817,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->chgBus(c+48825,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->chgQuad(c+48833,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->chgBus(c+48849,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->chgBit(c+48857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->chgBit(c+48865,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+48873,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+48881,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->chgBit(c+48897,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->chgBus(c+48905,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->chgBit(c+48913,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->chgBit(c+48921,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); - vcdp->chgBus(c+48929,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->chgBus(c+48937,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->chgBus(c+48945,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1651[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1651[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1651[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1651[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+48953,(__Vtemp1651),128); - vcdp->chgBit(c+48985,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->chgBit(c+48993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->chgBus(c+49001,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); - vcdp->chgQuad(c+49009,((VL_ULL(0x1ffffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); 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- vcdp->chgBit(c+53425,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBit(c+53433,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+53441,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))),2); - vcdp->chgBus(c+53449,(((0x18fU >= (0x1ffU & - ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->chgBus(c+53457,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->chgBus(c+53465,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->chgQuad(c+53473,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->chgBus(c+53489,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->chgBit(c+53497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->chgBit(c+53505,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->chgBus(c+53513,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->chgQuad(c+53521,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->chgBit(c+53537,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->chgBus(c+53545,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->chgBit(c+53553,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->chgBit(c+53561,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); - vcdp->chgBus(c+53569,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->chgBus(c+53577,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->chgBus(c+53585,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1675[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1675[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1675[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1675[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->chgArray(c+53593,(__Vtemp1675),128); - vcdp->chgBit(c+53625,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->chgBit(c+53633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->chgBus(c+53641,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); - vcdp->chgQuad(c+53649,((VL_ULL(0x1ffffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->chgBus(c+53665,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->chgBit(c+53673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U)))); - vcdp->chgBit(c+53681,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vcdp->chgBit(c+53689,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U)))); - vcdp->chgBit(c+53697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vcdp->chgBit(c+53705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)))); - vcdp->chgBit(c+53713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)))); - vcdp->chgBit(c+53721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U)))); - vcdp->chgBit(c+53729,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+53737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBit(c+53745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->chgBit(c+53753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->chgBus(c+53761,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->chgBus(c+53769,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))),28); - vcdp->chgBit(c+53777,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->chgBus(c+53785,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->chgQuad(c+53793,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->chgQuad(c+53795,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->chgQuad(c+53797,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->chgQuad(c+53799,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); 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- vcdp->chgBus(c+57305,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); - vcdp->chgBus(c+57313,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); - vcdp->chgBus(c+57321,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); - vcdp->chgBus(c+57329,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); - vcdp->chgBus(c+57337,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); - vcdp->chgBit(c+57345,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->chgBus(c+57353,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); - vcdp->chgArray(c+57361,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); - vcdp->chgArray(c+57364,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); - vcdp->chgArray(c+57367,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); - vcdp->chgArray(c+57370,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); - vcdp->chgArray(c+57373,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); - vcdp->chgArray(c+57376,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); - vcdp->chgArray(c+57379,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); - vcdp->chgArray(c+57382,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); - vcdp->chgArray(c+57553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->chgArray(c+57577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->chgBus(c+57601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->chgBus(c+57609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->chgBus(c+57617,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->chgBit(c+57625,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->chgBus(c+57633,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->chgArray(c+57641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->chgArray(c+57648,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->chgArray(c+57655,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->chgArray(c+57662,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->chgArray(c+57865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->chgArray(c+57921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->chgBus(c+57977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->chgBus(c+57985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->chgBus(c+57993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->chgBit(c+58001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+22625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->chgArray(c+22633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->chgArray(c+22643,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->chgArray(c+22653,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->chgArray(c+22663,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->chgArray(c+22953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->chgArray(c+23033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->chgBus(c+23113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+23121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+23129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+23137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgArray(c+23145,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->chgQuad(c+23209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->chgQuad(c+23225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->chgBus(c+23241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->chgBus(c+23249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->chgArray(c+23257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->chgArray(c+23305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->chgArray(c+23385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->chgArray(c+23388,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->chgArray(c+23391,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->chgArray(c+23394,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->chgArray(c+23397,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->chgArray(c+23400,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->chgArray(c+23403,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->chgArray(c+23406,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->chgArray(c+23409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->chgArray(c+23412,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->chgArray(c+23415,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->chgArray(c+23418,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->chgArray(c+23421,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->chgArray(c+23424,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->chgArray(c+23427,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->chgArray(c+23430,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->chgArray(c+23769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->chgBus(c+23873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->chgBus(c+23881,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->chgBus(c+23889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->chgBus(c+23897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->chgBus(c+23905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->chgBus(c+23913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->chgBit(c+23921,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->chgBus(c+23929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->chgArray(c+23937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->chgArray(c+23940,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->chgArray(c+23943,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->chgArray(c+23946,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->chgArray(c+24033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->chgArray(c+24057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->chgBus(c+24081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+24089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+24097,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+24105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->chgBus(c+24113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->chgArray(c+24121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->chgArray(c+24128,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->chgArray(c+24135,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->chgArray(c+24142,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->chgArray(c+24345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->chgArray(c+24401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->chgBus(c+24457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->chgBus(c+24465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->chgBus(c+24473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->chgBit(c+24481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); } } @@ -9473,88 +3995,72 @@ void VVX_cache::traceChgThis__6(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc if (0 && vcdp && c) {} // Prevent unused // Body { - vcdp->chgBit(c+58009,(vlTOPp->clk)); - vcdp->chgBit(c+58017,(vlTOPp->reset)); - vcdp->chgBus(c+58025,(vlTOPp->core_req_valid),4); - vcdp->chgBus(c+58033,(vlTOPp->core_req_rw),4); - vcdp->chgBus(c+58041,(vlTOPp->core_req_byteen),16); - vcdp->chgArray(c+58049,(vlTOPp->core_req_addr),120); - vcdp->chgArray(c+58081,(vlTOPp->core_req_data),128); - vcdp->chgQuad(c+58113,(vlTOPp->core_req_tag),42); - vcdp->chgBit(c+58129,(vlTOPp->core_req_ready)); - vcdp->chgBus(c+58137,(vlTOPp->core_rsp_valid),4); - vcdp->chgArray(c+58145,(vlTOPp->core_rsp_data),128); - vcdp->chgQuad(c+58177,(vlTOPp->core_rsp_tag),42); - vcdp->chgBit(c+58193,(vlTOPp->core_rsp_ready)); - vcdp->chgBit(c+58201,(vlTOPp->dram_req_valid)); - vcdp->chgBit(c+58209,(vlTOPp->dram_req_rw)); - vcdp->chgBus(c+58217,(vlTOPp->dram_req_byteen),16); - vcdp->chgBus(c+58225,(vlTOPp->dram_req_addr),28); - vcdp->chgArray(c+58233,(vlTOPp->dram_req_data),128); - vcdp->chgBus(c+58265,(vlTOPp->dram_req_tag),28); - vcdp->chgBit(c+58273,(vlTOPp->dram_req_ready)); - vcdp->chgBit(c+58281,(vlTOPp->dram_rsp_valid)); - vcdp->chgArray(c+58289,(vlTOPp->dram_rsp_data),128); - vcdp->chgBus(c+58321,(vlTOPp->dram_rsp_tag),28); - vcdp->chgBit(c+58329,(vlTOPp->dram_rsp_ready)); - vcdp->chgBit(c+58337,(vlTOPp->snp_req_valid)); - vcdp->chgBus(c+58345,(vlTOPp->snp_req_addr),28); - vcdp->chgBit(c+58353,(vlTOPp->snp_req_invalidate)); - vcdp->chgBus(c+58361,(vlTOPp->snp_req_tag),28); - vcdp->chgBit(c+58369,(vlTOPp->snp_req_ready)); - vcdp->chgBit(c+58377,(vlTOPp->snp_rsp_valid)); - vcdp->chgBus(c+58385,(vlTOPp->snp_rsp_tag),28); - vcdp->chgBit(c+58393,(vlTOPp->snp_rsp_ready)); - vcdp->chgBus(c+58401,(vlTOPp->snp_fwdout_valid),2); - vcdp->chgQuad(c+58409,(vlTOPp->snp_fwdout_addr),56); - vcdp->chgBus(c+58425,(vlTOPp->snp_fwdout_invalidate),2); - vcdp->chgBus(c+58433,(vlTOPp->snp_fwdout_tag),2); - vcdp->chgBus(c+58441,(vlTOPp->snp_fwdout_ready),2); - vcdp->chgBus(c+58449,(vlTOPp->snp_fwdin_valid),2); - vcdp->chgBus(c+58457,(vlTOPp->snp_fwdin_tag),2); - vcdp->chgBus(c+58465,(vlTOPp->snp_fwdin_ready),2); - vcdp->chgBit(c+58473,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) - >> (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58481,(((IData)(vlTOPp->dram_rsp_valid) - & (0U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBus(c+58489,((0x1ffffffU & (vlTOPp->dram_rsp_tag - >> 3U))),25); - vcdp->chgBit(c+58497,(((IData)(vlTOPp->snp_req_valid) - & (0U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBus(c+58505,((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U))),25); - vcdp->chgBit(c+58513,(((IData)(vlTOPp->dram_rsp_valid) - & (1U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBit(c+58521,(((IData)(vlTOPp->snp_req_valid) - & (1U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58529,(((IData)(vlTOPp->dram_rsp_valid) - & (2U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBit(c+58537,(((IData)(vlTOPp->snp_req_valid) - & (2U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58545,(((IData)(vlTOPp->dram_rsp_valid) - & (3U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBit(c+58553,(((IData)(vlTOPp->snp_req_valid) - & (3U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58561,(((IData)(vlTOPp->dram_rsp_valid) - & (4U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBit(c+58569,(((IData)(vlTOPp->snp_req_valid) - & (4U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58577,(((IData)(vlTOPp->dram_rsp_valid) - & (5U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBit(c+58585,(((IData)(vlTOPp->snp_req_valid) - & (5U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58593,(((IData)(vlTOPp->dram_rsp_valid) - & (6U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBit(c+58601,(((IData)(vlTOPp->snp_req_valid) - & (6U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58609,(((IData)(vlTOPp->dram_rsp_valid) - & (7U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->chgBit(c+58617,(((IData)(vlTOPp->snp_req_valid) - & (7U == (7U & vlTOPp->snp_req_addr))))); - vcdp->chgBit(c+58625,(((IData)(vlTOPp->dram_req_valid) + vcdp->chgBit(c+24489,(vlTOPp->clk)); + vcdp->chgBit(c+24497,(vlTOPp->reset)); + vcdp->chgBus(c+24505,(vlTOPp->core_req_valid),4); + vcdp->chgBus(c+24513,(vlTOPp->core_req_rw),4); + vcdp->chgBus(c+24521,(vlTOPp->core_req_byteen),16); + vcdp->chgArray(c+24529,(vlTOPp->core_req_addr),120); + vcdp->chgArray(c+24561,(vlTOPp->core_req_data),128); + vcdp->chgQuad(c+24593,(vlTOPp->core_req_tag),42); + vcdp->chgBit(c+24609,(vlTOPp->core_req_ready)); + vcdp->chgBus(c+24617,(vlTOPp->core_rsp_valid),4); + vcdp->chgArray(c+24625,(vlTOPp->core_rsp_data),128); + vcdp->chgQuad(c+24657,(vlTOPp->core_rsp_tag),42); + vcdp->chgBit(c+24673,(vlTOPp->core_rsp_ready)); + vcdp->chgBit(c+24681,(vlTOPp->dram_req_valid)); + vcdp->chgBit(c+24689,(vlTOPp->dram_req_rw)); + vcdp->chgBus(c+24697,(vlTOPp->dram_req_byteen),16); + vcdp->chgBus(c+24705,(vlTOPp->dram_req_addr),28); + vcdp->chgArray(c+24713,(vlTOPp->dram_req_data),128); + vcdp->chgBus(c+24745,(vlTOPp->dram_req_tag),28); + vcdp->chgBit(c+24753,(vlTOPp->dram_req_ready)); + vcdp->chgBit(c+24761,(vlTOPp->dram_rsp_valid)); + vcdp->chgArray(c+24769,(vlTOPp->dram_rsp_data),128); + vcdp->chgBus(c+24801,(vlTOPp->dram_rsp_tag),28); + vcdp->chgBit(c+24809,(vlTOPp->dram_rsp_ready)); + vcdp->chgBit(c+24817,(vlTOPp->snp_req_valid)); + vcdp->chgBus(c+24825,(vlTOPp->snp_req_addr),28); + vcdp->chgBit(c+24833,(vlTOPp->snp_req_invalidate)); + vcdp->chgBus(c+24841,(vlTOPp->snp_req_tag),28); + vcdp->chgBit(c+24849,(vlTOPp->snp_req_ready)); + vcdp->chgBit(c+24857,(vlTOPp->snp_rsp_valid)); + vcdp->chgBus(c+24865,(vlTOPp->snp_rsp_tag),28); + vcdp->chgBit(c+24873,(vlTOPp->snp_rsp_ready)); + vcdp->chgBus(c+24881,(vlTOPp->snp_fwdout_valid),2); + vcdp->chgQuad(c+24889,(vlTOPp->snp_fwdout_addr),56); + vcdp->chgBus(c+24905,(vlTOPp->snp_fwdout_invalidate),2); + vcdp->chgBus(c+24913,(vlTOPp->snp_fwdout_tag),2); + vcdp->chgBus(c+24921,(vlTOPp->snp_fwdout_ready),2); + vcdp->chgBus(c+24929,(vlTOPp->snp_fwdin_valid),2); + vcdp->chgBus(c+24937,(vlTOPp->snp_fwdin_tag),2); + vcdp->chgBus(c+24945,(vlTOPp->snp_fwdin_ready),2); + vcdp->chgBit(c+24953,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+24961,(((IData)(vlTOPp->dram_rsp_valid) + & (0U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBus(c+24969,((0x3ffffffU & (vlTOPp->dram_rsp_tag + >> 2U))),26); + vcdp->chgBit(c+24977,(((IData)(vlTOPp->snp_req_valid) + & (0U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBus(c+24985,((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U))),26); + vcdp->chgBit(c+24993,(((IData)(vlTOPp->dram_rsp_valid) + & (1U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+25001,(((IData)(vlTOPp->snp_req_valid) + & (1U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+25009,(((IData)(vlTOPp->dram_rsp_valid) + & (2U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+25017,(((IData)(vlTOPp->snp_req_valid) + & (2U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+25025,(((IData)(vlTOPp->dram_rsp_valid) + & (3U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->chgBit(c+25033,(((IData)(vlTOPp->snp_req_valid) + & (3U == (3U & vlTOPp->snp_req_addr))))); + vcdp->chgBit(c+25041,(((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))))); - vcdp->chgBit(c+58633,((((IData)(vlTOPp->dram_req_valid) + vcdp->chgBit(c+25049,((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); } } diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp index 7382e434..7aef5ddd 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp @@ -60,5630 +60,2853 @@ void VVX_cache::traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV if (0 && vcdp && c) {} // Prevent unused // Body { - vcdp->declBit(c+58009,"clk", false,-1); - vcdp->declBit(c+58017,"reset", false,-1); - vcdp->declBus(c+58025,"core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"core_req_tag", false,-1, 41,0); - vcdp->declBit(c+58129,"core_req_ready", false,-1); - vcdp->declBus(c+58137,"core_rsp_valid", false,-1, 3,0); - vcdp->declArray(c+58145,"core_rsp_data", false,-1, 127,0); - vcdp->declQuad(c+58177,"core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+58193,"core_rsp_ready", false,-1); - vcdp->declBit(c+58201,"dram_req_valid", false,-1); - vcdp->declBit(c+58209,"dram_req_rw", false,-1); - vcdp->declBus(c+58217,"dram_req_byteen", false,-1, 15,0); - vcdp->declBus(c+58225,"dram_req_addr", false,-1, 27,0); - vcdp->declArray(c+58233,"dram_req_data", false,-1, 127,0); - vcdp->declBus(c+58265,"dram_req_tag", false,-1, 27,0); - vcdp->declBit(c+58273,"dram_req_ready", false,-1); - vcdp->declBit(c+58281,"dram_rsp_valid", false,-1); - vcdp->declArray(c+58289,"dram_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58321,"dram_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+58329,"dram_rsp_ready", false,-1); - vcdp->declBit(c+58337,"snp_req_valid", false,-1); - vcdp->declBus(c+58345,"snp_req_addr", false,-1, 27,0); - vcdp->declBit(c+58353,"snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+58369,"snp_req_ready", false,-1); - vcdp->declBit(c+58377,"snp_rsp_valid", false,-1); - vcdp->declBus(c+58385,"snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+58393,"snp_rsp_ready", false,-1); - vcdp->declBus(c+58401,"snp_fwdout_valid", false,-1, 1,0); - vcdp->declQuad(c+58409,"snp_fwdout_addr", false,-1, 55,0); - vcdp->declBus(c+58425,"snp_fwdout_invalidate", false,-1, 1,0); - vcdp->declBus(c+58433,"snp_fwdout_tag", false,-1, 1,0); - vcdp->declBus(c+58441,"snp_fwdout_ready", false,-1, 1,0); - vcdp->declBus(c+58449,"snp_fwdin_valid", false,-1, 1,0); - vcdp->declBus(c+58457,"snp_fwdin_tag", false,-1, 1,0); - vcdp->declBus(c+58465,"snp_fwdin_ready", false,-1, 1,0); - vcdp->declBus(c+58641,"VX_cache CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache PRFQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache PRFQ_STRIDE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache DRAM_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58705,"VX_cache NUM_SNP_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache SNP_FWD_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache clk", false,-1); - vcdp->declBit(c+58017,"VX_cache reset", false,-1); - vcdp->declBus(c+58025,"VX_cache core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache core_req_tag", false,-1, 41,0); - vcdp->declBit(c+58129,"VX_cache core_req_ready", false,-1); - vcdp->declBus(c+58137,"VX_cache core_rsp_valid", false,-1, 3,0); - vcdp->declArray(c+58145,"VX_cache core_rsp_data", false,-1, 127,0); - vcdp->declQuad(c+58177,"VX_cache core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+58193,"VX_cache core_rsp_ready", false,-1); - vcdp->declBit(c+58201,"VX_cache dram_req_valid", false,-1); - vcdp->declBit(c+58209,"VX_cache dram_req_rw", false,-1); - vcdp->declBus(c+58217,"VX_cache dram_req_byteen", false,-1, 15,0); - vcdp->declBus(c+58225,"VX_cache dram_req_addr", false,-1, 27,0); - vcdp->declArray(c+58233,"VX_cache dram_req_data", false,-1, 127,0); - vcdp->declBus(c+58265,"VX_cache dram_req_tag", false,-1, 27,0); - vcdp->declBit(c+58273,"VX_cache dram_req_ready", false,-1); - vcdp->declBit(c+58281,"VX_cache dram_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache dram_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58321,"VX_cache dram_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+58329,"VX_cache dram_rsp_ready", false,-1); - vcdp->declBit(c+58337,"VX_cache snp_req_valid", false,-1); - vcdp->declBus(c+58345,"VX_cache snp_req_addr", false,-1, 27,0); - vcdp->declBit(c+58353,"VX_cache snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+58369,"VX_cache snp_req_ready", false,-1); - vcdp->declBit(c+58377,"VX_cache snp_rsp_valid", false,-1); - vcdp->declBus(c+58385,"VX_cache snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+58393,"VX_cache snp_rsp_ready", false,-1); - vcdp->declBus(c+58401,"VX_cache snp_fwdout_valid", false,-1, 1,0); - vcdp->declQuad(c+58409,"VX_cache snp_fwdout_addr", false,-1, 55,0); - vcdp->declBus(c+58425,"VX_cache snp_fwdout_invalidate", false,-1, 1,0); - vcdp->declBus(c+58433,"VX_cache snp_fwdout_tag", false,-1, 1,0); - vcdp->declBus(c+58441,"VX_cache snp_fwdout_ready", false,-1, 1,0); - vcdp->declBus(c+58449,"VX_cache snp_fwdin_valid", false,-1, 1,0); - vcdp->declBus(c+58457,"VX_cache snp_fwdin_tag", false,-1, 1,0); - vcdp->declBus(c+58465,"VX_cache snp_fwdin_ready", false,-1, 1,0); - vcdp->declBus(c+1,"VX_cache per_bank_valid", false,-1, 31,0); - vcdp->declBus(c+2113,"VX_cache per_bank_core_req_ready", false,-1, 7,0); - vcdp->declBus(c+2121,"VX_cache per_bank_core_rsp_valid", false,-1, 7,0); - vcdp->declBus(c+2129,"VX_cache per_bank_core_rsp_tid", false,-1, 15,0); - vcdp->declArray(c+2137,"VX_cache per_bank_core_rsp_data", false,-1, 255,0); - vcdp->declArray(c+2201,"VX_cache per_bank_core_rsp_tag", false,-1, 335,0); - vcdp->declBus(c+9,"VX_cache per_bank_core_rsp_ready", false,-1, 7,0); - vcdp->declBus(c+2289,"VX_cache per_bank_dram_fill_req_valid", false,-1, 7,0); - vcdp->declArray(c+2297,"VX_cache per_bank_dram_fill_req_addr", false,-1, 223,0); - vcdp->declBit(c+19649,"VX_cache dram_fill_req_ready", false,-1); - vcdp->declBus(c+2353,"VX_cache per_bank_dram_fill_rsp_ready", false,-1, 7,0); - vcdp->declBus(c+17,"VX_cache per_bank_dram_wb_req_ready", false,-1, 7,0); - vcdp->declBus(c+2361,"VX_cache per_bank_dram_wb_req_valid", false,-1, 7,0); - vcdp->declArray(c+2369,"VX_cache per_bank_dram_wb_req_byteen", false,-1, 127,0); - vcdp->declArray(c+2401,"VX_cache per_bank_dram_wb_req_addr", false,-1, 223,0); - vcdp->declArray(c+2457,"VX_cache per_bank_dram_wb_req_data", false,-1, 1023,0); - vcdp->declBus(c+2713,"VX_cache per_bank_snp_req_ready", false,-1, 7,0); - vcdp->declBus(c+2721,"VX_cache per_bank_snp_rsp_valid", false,-1, 7,0); - vcdp->declArray(c+2729,"VX_cache per_bank_snp_rsp_tag", false,-1, 223,0); - vcdp->declBus(c+25,"VX_cache per_bank_snp_rsp_ready", false,-1, 7,0); - vcdp->declBit(c+58337,"VX_cache snp_req_valid_qual", false,-1); - vcdp->declBus(c+58345,"VX_cache snp_req_addr_qual", false,-1, 27,0); - vcdp->declBit(c+58353,"VX_cache snp_req_invalidate_qual", false,-1); - vcdp->declBus(c+58361,"VX_cache snp_req_tag_qual", false,-1, 27,0); - vcdp->declBit(c+58473,"VX_cache snp_req_ready_qual", false,-1); + vcdp->declBit(c+24489,"clk", false,-1); + vcdp->declBit(c+24497,"reset", false,-1); + vcdp->declBus(c+24505,"core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"core_req_tag", false,-1, 41,0); + vcdp->declBit(c+24609,"core_req_ready", false,-1); + vcdp->declBus(c+24617,"core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+24625,"core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+24657,"core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+24673,"core_rsp_ready", false,-1); + vcdp->declBit(c+24681,"dram_req_valid", false,-1); + vcdp->declBit(c+24689,"dram_req_rw", false,-1); + vcdp->declBus(c+24697,"dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+24705,"dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+24713,"dram_req_data", false,-1, 127,0); + vcdp->declBus(c+24745,"dram_req_tag", false,-1, 27,0); + vcdp->declBit(c+24753,"dram_req_ready", false,-1); + vcdp->declBit(c+24761,"dram_rsp_valid", false,-1); + vcdp->declArray(c+24769,"dram_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24801,"dram_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24809,"dram_rsp_ready", false,-1); + vcdp->declBit(c+24817,"snp_req_valid", false,-1); + vcdp->declBus(c+24825,"snp_req_addr", false,-1, 27,0); + vcdp->declBit(c+24833,"snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+24849,"snp_req_ready", false,-1); + vcdp->declBit(c+24857,"snp_rsp_valid", false,-1); + vcdp->declBus(c+24865,"snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24873,"snp_rsp_ready", false,-1); + vcdp->declBus(c+24881,"snp_fwdout_valid", false,-1, 1,0); + vcdp->declQuad(c+24889,"snp_fwdout_addr", false,-1, 55,0); + vcdp->declBus(c+24905,"snp_fwdout_invalidate", false,-1, 1,0); + vcdp->declBus(c+24913,"snp_fwdout_tag", false,-1, 1,0); + vcdp->declBus(c+24921,"snp_fwdout_ready", false,-1, 1,0); + vcdp->declBus(c+24929,"snp_fwdin_valid", false,-1, 1,0); + vcdp->declBus(c+24937,"snp_fwdin_tag", false,-1, 1,0); + vcdp->declBus(c+24945,"snp_fwdin_ready", false,-1, 1,0); + vcdp->declBus(c+25057,"VX_cache CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache DRAM_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25121,"VX_cache NUM_SNP_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache SNP_FWD_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache clk", false,-1); + vcdp->declBit(c+24497,"VX_cache reset", false,-1); + vcdp->declBus(c+24505,"VX_cache core_req_valid", false,-1, 3,0); + vcdp->declBus(c+24513,"VX_cache core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache core_req_tag", false,-1, 41,0); + vcdp->declBit(c+24609,"VX_cache core_req_ready", false,-1); + vcdp->declBus(c+24617,"VX_cache core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+24625,"VX_cache core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+24657,"VX_cache core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+24673,"VX_cache core_rsp_ready", false,-1); + vcdp->declBit(c+24681,"VX_cache dram_req_valid", false,-1); + vcdp->declBit(c+24689,"VX_cache dram_req_rw", false,-1); + vcdp->declBus(c+24697,"VX_cache dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+24705,"VX_cache dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+24713,"VX_cache dram_req_data", false,-1, 127,0); + vcdp->declBus(c+24745,"VX_cache dram_req_tag", false,-1, 27,0); + vcdp->declBit(c+24753,"VX_cache dram_req_ready", false,-1); + vcdp->declBit(c+24761,"VX_cache dram_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache dram_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24801,"VX_cache dram_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24809,"VX_cache dram_rsp_ready", false,-1); + vcdp->declBit(c+24817,"VX_cache snp_req_valid", false,-1); + vcdp->declBus(c+24825,"VX_cache snp_req_addr", false,-1, 27,0); + vcdp->declBit(c+24833,"VX_cache snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+24849,"VX_cache snp_req_ready", false,-1); + vcdp->declBit(c+24857,"VX_cache snp_rsp_valid", false,-1); + vcdp->declBus(c+24865,"VX_cache snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24873,"VX_cache snp_rsp_ready", false,-1); + vcdp->declBus(c+24881,"VX_cache snp_fwdout_valid", false,-1, 1,0); + vcdp->declQuad(c+24889,"VX_cache snp_fwdout_addr", false,-1, 55,0); + vcdp->declBus(c+24905,"VX_cache snp_fwdout_invalidate", false,-1, 1,0); + vcdp->declBus(c+24913,"VX_cache snp_fwdout_tag", false,-1, 1,0); + vcdp->declBus(c+24921,"VX_cache snp_fwdout_ready", false,-1, 1,0); + vcdp->declBus(c+24929,"VX_cache snp_fwdin_valid", false,-1, 1,0); + vcdp->declBus(c+24937,"VX_cache snp_fwdin_tag", false,-1, 1,0); + vcdp->declBus(c+24945,"VX_cache snp_fwdin_ready", false,-1, 1,0); + vcdp->declBus(c+1,"VX_cache per_bank_valid", false,-1, 15,0); + vcdp->declBus(c+1089,"VX_cache per_bank_core_req_ready", false,-1, 3,0); + vcdp->declBus(c+1097,"VX_cache per_bank_core_rsp_valid", false,-1, 3,0); + vcdp->declBus(c+1105,"VX_cache per_bank_core_rsp_tid", false,-1, 7,0); + vcdp->declArray(c+1113,"VX_cache per_bank_core_rsp_data", false,-1, 127,0); + vcdp->declArray(c+1145,"VX_cache per_bank_core_rsp_tag", false,-1, 167,0); + vcdp->declBus(c+9,"VX_cache per_bank_core_rsp_ready", false,-1, 3,0); + vcdp->declBus(c+1193,"VX_cache per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+1201,"VX_cache per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBit(c+10065,"VX_cache dram_fill_req_ready", false,-1); + vcdp->declBus(c+1233,"VX_cache per_bank_dram_fill_rsp_ready", false,-1, 3,0); + vcdp->declBus(c+17,"VX_cache per_bank_dram_wb_req_ready", false,-1, 3,0); + vcdp->declBus(c+1241,"VX_cache per_bank_dram_wb_req_valid", false,-1, 3,0); + vcdp->declQuad(c+1249,"VX_cache per_bank_dram_wb_req_byteen", false,-1, 63,0); + vcdp->declArray(c+1265,"VX_cache per_bank_dram_wb_req_addr", false,-1, 111,0); + vcdp->declArray(c+1297,"VX_cache per_bank_dram_wb_req_data", false,-1, 511,0); + vcdp->declBus(c+1425,"VX_cache per_bank_snp_req_ready", false,-1, 3,0); + vcdp->declBus(c+1433,"VX_cache per_bank_snp_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+1441,"VX_cache per_bank_snp_rsp_tag", false,-1, 111,0); + vcdp->declBus(c+25,"VX_cache per_bank_snp_rsp_ready", false,-1, 3,0); + vcdp->declBit(c+24817,"VX_cache snp_req_valid_qual", false,-1); + vcdp->declBus(c+24825,"VX_cache snp_req_addr_qual", false,-1, 27,0); + vcdp->declBit(c+24833,"VX_cache snp_req_invalidate_qual", false,-1); + vcdp->declBus(c+24841,"VX_cache snp_req_tag_qual", false,-1, 27,0); + vcdp->declBit(c+24953,"VX_cache snp_req_ready_qual", false,-1); vcdp->declBus(c+33,"VX_cache genblk5[0] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[0] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[0] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[0] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[0] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[0] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19657,"VX_cache genblk5[0] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+2785,"VX_cache genblk5[0] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+2793,"VX_cache genblk5[0] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+2801,"VX_cache genblk5[0] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[0] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[0] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[0] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[0] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[0] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10073,"VX_cache genblk5[0] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1473,"VX_cache genblk5[0] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1481,"VX_cache genblk5[0] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1489,"VX_cache genblk5[0] curr_bank_core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+41,"VX_cache genblk5[0] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58481,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19665,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+2817,"VX_cache genblk5[0] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19673,"VX_cache genblk5[0] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[0] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+2825,"VX_cache genblk5[0] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+2833,"VX_cache genblk5[0] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+2841,"VX_cache genblk5[0] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+2849,"VX_cache genblk5[0] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+24961,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10081,"VX_cache genblk5[0] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1505,"VX_cache genblk5[0] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[0] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1513,"VX_cache genblk5[0] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1521,"VX_cache genblk5[0] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1529,"VX_cache genblk5[0] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1537,"VX_cache genblk5[0] curr_bank_dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+49,"VX_cache genblk5[0] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58497,"VX_cache genblk5[0] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[0] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[0] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[0] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19681,"VX_cache genblk5[0] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+2881,"VX_cache genblk5[0] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+2889,"VX_cache genblk5[0] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24977,"VX_cache genblk5[0] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[0] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[0] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[0] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10097,"VX_cache genblk5[0] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1569,"VX_cache genblk5[0] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1577,"VX_cache genblk5[0] curr_bank_snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+57,"VX_cache genblk5[0] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19689,"VX_cache genblk5[0] curr_bank_core_req_ready", false,-1); + vcdp->declBit(c+10105,"VX_cache genblk5[0] curr_bank_core_req_ready", false,-1); vcdp->declBus(c+65,"VX_cache genblk5[1] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[1] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[1] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[1] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[1] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[1] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19697,"VX_cache genblk5[1] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+2897,"VX_cache genblk5[1] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+2905,"VX_cache genblk5[1] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+2913,"VX_cache genblk5[1] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[1] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[1] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[1] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[1] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[1] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10113,"VX_cache genblk5[1] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1585,"VX_cache genblk5[1] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1593,"VX_cache genblk5[1] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1601,"VX_cache genblk5[1] curr_bank_core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+73,"VX_cache genblk5[1] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58513,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19705,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+2929,"VX_cache genblk5[1] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19713,"VX_cache genblk5[1] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[1] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+2937,"VX_cache genblk5[1] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+2945,"VX_cache genblk5[1] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+2953,"VX_cache genblk5[1] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+2961,"VX_cache genblk5[1] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+24993,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10121,"VX_cache genblk5[1] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1617,"VX_cache genblk5[1] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[1] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1625,"VX_cache genblk5[1] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1633,"VX_cache genblk5[1] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1641,"VX_cache genblk5[1] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1649,"VX_cache genblk5[1] curr_bank_dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+81,"VX_cache genblk5[1] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58521,"VX_cache genblk5[1] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[1] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[1] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[1] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19721,"VX_cache genblk5[1] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+2993,"VX_cache genblk5[1] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+3001,"VX_cache genblk5[1] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+25001,"VX_cache genblk5[1] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[1] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[1] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[1] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10137,"VX_cache genblk5[1] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1681,"VX_cache genblk5[1] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1689,"VX_cache genblk5[1] curr_bank_snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+89,"VX_cache genblk5[1] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19729,"VX_cache genblk5[1] curr_bank_core_req_ready", false,-1); + vcdp->declBit(c+10145,"VX_cache genblk5[1] curr_bank_core_req_ready", false,-1); vcdp->declBus(c+97,"VX_cache genblk5[2] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[2] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[2] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[2] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[2] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[2] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19737,"VX_cache genblk5[2] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+3009,"VX_cache genblk5[2] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3017,"VX_cache genblk5[2] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3025,"VX_cache genblk5[2] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[2] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[2] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[2] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[2] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[2] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10153,"VX_cache genblk5[2] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1697,"VX_cache genblk5[2] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1705,"VX_cache genblk5[2] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1713,"VX_cache genblk5[2] curr_bank_core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+105,"VX_cache genblk5[2] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58529,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19745,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3041,"VX_cache genblk5[2] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19753,"VX_cache genblk5[2] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[2] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+3049,"VX_cache genblk5[2] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+3057,"VX_cache genblk5[2] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3065,"VX_cache genblk5[2] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3073,"VX_cache genblk5[2] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+25009,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10161,"VX_cache genblk5[2] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1729,"VX_cache genblk5[2] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[2] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1737,"VX_cache genblk5[2] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1745,"VX_cache genblk5[2] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1753,"VX_cache genblk5[2] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1761,"VX_cache genblk5[2] curr_bank_dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+113,"VX_cache genblk5[2] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58537,"VX_cache genblk5[2] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[2] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[2] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[2] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19761,"VX_cache genblk5[2] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+3105,"VX_cache genblk5[2] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+3113,"VX_cache genblk5[2] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+25017,"VX_cache genblk5[2] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[2] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[2] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[2] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10177,"VX_cache genblk5[2] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1793,"VX_cache genblk5[2] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1801,"VX_cache genblk5[2] curr_bank_snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+121,"VX_cache genblk5[2] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19769,"VX_cache genblk5[2] curr_bank_core_req_ready", false,-1); + vcdp->declBit(c+10185,"VX_cache genblk5[2] curr_bank_core_req_ready", false,-1); vcdp->declBus(c+129,"VX_cache genblk5[3] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[3] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[3] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[3] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[3] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[3] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19777,"VX_cache genblk5[3] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+3121,"VX_cache genblk5[3] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3129,"VX_cache genblk5[3] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3137,"VX_cache genblk5[3] curr_bank_core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[3] curr_bank_core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[3] curr_bank_core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[3] curr_bank_core_req_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[3] curr_bank_core_req_tag", false,-1, 41,0); + vcdp->declArray(c+24561,"VX_cache genblk5[3] curr_bank_core_req_data", false,-1, 127,0); + vcdp->declBit(c+10193,"VX_cache genblk5[3] curr_bank_core_rsp_valid", false,-1); + vcdp->declBus(c+1809,"VX_cache genblk5[3] curr_bank_core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1817,"VX_cache genblk5[3] curr_bank_core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1825,"VX_cache genblk5[3] curr_bank_core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+137,"VX_cache genblk5[3] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58545,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19785,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3153,"VX_cache genblk5[3] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19793,"VX_cache genblk5[3] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[3] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+3161,"VX_cache genblk5[3] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+3169,"VX_cache genblk5[3] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3177,"VX_cache genblk5[3] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3185,"VX_cache genblk5[3] curr_bank_dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+25025,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10201,"VX_cache genblk5[3] curr_bank_dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1841,"VX_cache genblk5[3] curr_bank_dram_fill_req_valid", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] curr_bank_dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[3] curr_bank_dram_fill_req_ready", false,-1); + vcdp->declBit(c+1849,"VX_cache genblk5[3] curr_bank_dram_wb_req_valid", false,-1); + vcdp->declBus(c+1857,"VX_cache genblk5[3] curr_bank_dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1865,"VX_cache genblk5[3] curr_bank_dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1873,"VX_cache genblk5[3] curr_bank_dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+145,"VX_cache genblk5[3] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58553,"VX_cache genblk5[3] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[3] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[3] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[3] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19801,"VX_cache genblk5[3] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+3217,"VX_cache genblk5[3] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+3225,"VX_cache genblk5[3] curr_bank_snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+25033,"VX_cache genblk5[3] curr_bank_snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[3] curr_bank_snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[3] curr_bank_snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[3] curr_bank_snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10217,"VX_cache genblk5[3] curr_bank_snp_req_ready", false,-1); + vcdp->declBit(c+1905,"VX_cache genblk5[3] curr_bank_snp_rsp_valid", false,-1); + vcdp->declBus(c+1913,"VX_cache genblk5[3] curr_bank_snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+153,"VX_cache genblk5[3] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19809,"VX_cache genblk5[3] curr_bank_core_req_ready", false,-1); - vcdp->declBus(c+161,"VX_cache genblk5[4] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[4] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[4] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[4] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[4] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[4] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19817,"VX_cache genblk5[4] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+3233,"VX_cache genblk5[4] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3241,"VX_cache genblk5[4] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3249,"VX_cache genblk5[4] curr_bank_core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+169,"VX_cache genblk5[4] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58561,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19825,"VX_cache genblk5[4] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3265,"VX_cache genblk5[4] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19833,"VX_cache genblk5[4] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[4] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+3273,"VX_cache genblk5[4] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+3281,"VX_cache genblk5[4] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3289,"VX_cache genblk5[4] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3297,"VX_cache genblk5[4] curr_bank_dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+177,"VX_cache genblk5[4] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58569,"VX_cache genblk5[4] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[4] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[4] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[4] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19841,"VX_cache genblk5[4] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+3329,"VX_cache genblk5[4] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+3337,"VX_cache genblk5[4] curr_bank_snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+185,"VX_cache genblk5[4] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19849,"VX_cache genblk5[4] curr_bank_core_req_ready", false,-1); - vcdp->declBus(c+193,"VX_cache genblk5[5] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[5] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[5] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[5] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[5] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[5] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19857,"VX_cache genblk5[5] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+3345,"VX_cache genblk5[5] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3353,"VX_cache genblk5[5] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3361,"VX_cache genblk5[5] curr_bank_core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+201,"VX_cache genblk5[5] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58577,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19865,"VX_cache genblk5[5] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3377,"VX_cache genblk5[5] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19873,"VX_cache genblk5[5] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[5] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+3385,"VX_cache genblk5[5] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+3393,"VX_cache genblk5[5] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3401,"VX_cache genblk5[5] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3409,"VX_cache genblk5[5] curr_bank_dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+209,"VX_cache genblk5[5] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58585,"VX_cache genblk5[5] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[5] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[5] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[5] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19881,"VX_cache genblk5[5] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+3441,"VX_cache genblk5[5] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+3449,"VX_cache genblk5[5] curr_bank_snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+217,"VX_cache genblk5[5] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19889,"VX_cache genblk5[5] curr_bank_core_req_ready", false,-1); - vcdp->declBus(c+225,"VX_cache genblk5[6] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[6] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[6] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[6] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[6] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[6] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19897,"VX_cache genblk5[6] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+3457,"VX_cache genblk5[6] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3465,"VX_cache genblk5[6] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3473,"VX_cache genblk5[6] curr_bank_core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+233,"VX_cache genblk5[6] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58593,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19905,"VX_cache genblk5[6] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3489,"VX_cache genblk5[6] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19913,"VX_cache genblk5[6] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[6] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+3497,"VX_cache genblk5[6] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+3505,"VX_cache genblk5[6] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3513,"VX_cache genblk5[6] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3521,"VX_cache genblk5[6] curr_bank_dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+241,"VX_cache genblk5[6] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58601,"VX_cache genblk5[6] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[6] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[6] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[6] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19921,"VX_cache genblk5[6] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+3553,"VX_cache genblk5[6] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+3561,"VX_cache genblk5[6] curr_bank_snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+249,"VX_cache genblk5[6] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19929,"VX_cache genblk5[6] curr_bank_core_req_ready", false,-1); - vcdp->declBus(c+257,"VX_cache genblk5[7] curr_bank_core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[7] curr_bank_core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[7] curr_bank_core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[7] curr_bank_core_req_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[7] curr_bank_core_req_tag", false,-1, 41,0); - vcdp->declArray(c+58081,"VX_cache genblk5[7] curr_bank_core_req_data", false,-1, 127,0); - vcdp->declBit(c+19937,"VX_cache genblk5[7] curr_bank_core_rsp_valid", false,-1); - vcdp->declBus(c+3569,"VX_cache genblk5[7] curr_bank_core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3577,"VX_cache genblk5[7] curr_bank_core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3585,"VX_cache genblk5[7] curr_bank_core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+265,"VX_cache genblk5[7] curr_bank_core_rsp_ready", false,-1); - vcdp->declBit(c+58609,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19945,"VX_cache genblk5[7] curr_bank_dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3601,"VX_cache genblk5[7] curr_bank_dram_fill_req_valid", false,-1); - vcdp->declBus(c+19953,"VX_cache genblk5[7] curr_bank_dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[7] curr_bank_dram_fill_req_ready", false,-1); - vcdp->declBit(c+3609,"VX_cache genblk5[7] curr_bank_dram_wb_req_valid", false,-1); - vcdp->declBus(c+3617,"VX_cache genblk5[7] curr_bank_dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3625,"VX_cache genblk5[7] curr_bank_dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3633,"VX_cache genblk5[7] curr_bank_dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+273,"VX_cache genblk5[7] curr_bank_dram_wb_req_ready", false,-1); - vcdp->declBit(c+58617,"VX_cache genblk5[7] curr_bank_snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[7] curr_bank_snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[7] curr_bank_snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[7] curr_bank_snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19961,"VX_cache genblk5[7] curr_bank_snp_req_ready", false,-1); - vcdp->declBit(c+3665,"VX_cache genblk5[7] curr_bank_snp_rsp_valid", false,-1); - vcdp->declBus(c+3673,"VX_cache genblk5[7] curr_bank_snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+281,"VX_cache genblk5[7] curr_bank_snp_rsp_ready", false,-1); - vcdp->declBit(c+19969,"VX_cache genblk5[7] curr_bank_core_req_ready", false,-1); - vcdp->declBus(c+58657,"VX_cache cache_core_req_bank_sel BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache cache_core_req_bank_sel WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_core_req_bank_sel NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache cache_core_req_bank_sel NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58025,"VX_cache cache_core_req_bank_sel core_req_valid", false,-1, 3,0); - vcdp->declArray(c+58049,"VX_cache cache_core_req_bank_sel core_req_addr", false,-1, 119,0); - vcdp->declBus(c+2113,"VX_cache cache_core_req_bank_sel per_bank_ready", false,-1, 7,0); - vcdp->declBus(c+1,"VX_cache cache_core_req_bank_sel per_bank_valid", false,-1, 31,0); - vcdp->declBit(c+58129,"VX_cache cache_core_req_bank_sel core_req_ready", false,-1); - vcdp->declBus(c+58713,"VX_cache cache_core_req_bank_sel i", false,-1, 31,0); - vcdp->declBus(c+289,"VX_cache cache_core_req_bank_sel genblk2 per_bank_ready_sel", false,-1, 7,0); - vcdp->declBus(c+58657,"VX_cache cache_dram_req_arb BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache cache_dram_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb PRFQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb PRFQ_STRIDE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb reset", false,-1); - vcdp->declBus(c+2289,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_valid", false,-1, 7,0); - vcdp->declArray(c+2297,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_addr", false,-1, 223,0); - vcdp->declBit(c+19649,"VX_cache cache_dram_req_arb dram_fill_req_ready", false,-1); - vcdp->declBus(c+2361,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_valid", false,-1, 7,0); - vcdp->declArray(c+2369,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_byteen", false,-1, 127,0); - vcdp->declArray(c+2401,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_addr", false,-1, 223,0); - vcdp->declArray(c+2457,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_data", false,-1, 1023,0); - vcdp->declBus(c+17,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_ready", false,-1, 7,0); - vcdp->declBit(c+58201,"VX_cache cache_dram_req_arb dram_req_valid", false,-1); - vcdp->declBit(c+58209,"VX_cache cache_dram_req_arb dram_req_rw", false,-1); - vcdp->declBus(c+58217,"VX_cache cache_dram_req_arb dram_req_byteen", false,-1, 15,0); - vcdp->declBus(c+58225,"VX_cache cache_dram_req_arb dram_req_addr", false,-1, 27,0); - vcdp->declArray(c+58233,"VX_cache cache_dram_req_arb dram_req_data", false,-1, 127,0); - vcdp->declBit(c+58273,"VX_cache cache_dram_req_arb dram_req_ready", false,-1); - vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb pref_pop", false,-1); - vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb pref_valid", false,-1); - vcdp->declBus(c+19977,"VX_cache cache_dram_req_arb pref_addr", false,-1, 27,0); - vcdp->declBit(c+3681,"VX_cache cache_dram_req_arb dwb_valid", false,-1); - vcdp->declBit(c+3689,"VX_cache cache_dram_req_arb dfqq_req", false,-1); - vcdp->declBus(c+3697,"VX_cache cache_dram_req_arb dfqq_req_addr", false,-1, 27,0); - vcdp->declBit(c+3705,"VX_cache cache_dram_req_arb dfqq_empty", false,-1); - vcdp->declBit(c+297,"VX_cache cache_dram_req_arb dfqq_pop", false,-1); - vcdp->declBit(c+3713,"VX_cache cache_dram_req_arb dfqq_push", false,-1); - vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dfqq_full", false,-1); - vcdp->declBus(c+3721,"VX_cache cache_dram_req_arb dwb_bank", false,-1, 2,0); - vcdp->declBus(c+58657,"VX_cache cache_dram_req_arb prfqq BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache cache_dram_req_arb prfqq WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb prfqq PRFQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb prfqq PRFQ_STRIDE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb prfqq clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb prfqq reset", false,-1); - vcdp->declBit(c+58625,"VX_cache cache_dram_req_arb prfqq dram_req", false,-1); - vcdp->declBus(c+58225,"VX_cache cache_dram_req_arb prfqq dram_req_addr", false,-1, 27,0); - vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb prfqq pref_pop", false,-1); - vcdp->declBit(c+58721,"VX_cache cache_dram_req_arb prfqq pref_valid", false,-1); - vcdp->declBus(c+19977,"VX_cache cache_dram_req_arb prfqq pref_addr", false,-1, 27,0); - vcdp->declBus(c+19993,"VX_cache cache_dram_req_arb prfqq use_valid", false,-1, 1,0); - vcdp->declBus(c+19977,"VX_cache cache_dram_req_arb prfqq use_addr", false,-1, 27,0); - vcdp->declBit(c+20001,"VX_cache cache_dram_req_arb prfqq current_valid", false,-1); - vcdp->declBus(c+20009,"VX_cache cache_dram_req_arb prfqq current_addr", false,-1, 27,0); - vcdp->declBit(c+20017,"VX_cache cache_dram_req_arb prfqq current_full", false,-1); - vcdp->declBit(c+20025,"VX_cache cache_dram_req_arb prfqq current_empty", false,-1); - vcdp->declBit(c+3729,"VX_cache cache_dram_req_arb prfqq update_use", false,-1); - vcdp->declBus(c+58697,"VX_cache cache_dram_req_arb prfqq pfq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache cache_dram_req_arb prfqq pfq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache cache_dram_req_arb prfqq pfq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb prfqq pfq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb prfqq pfq_queue reset", false,-1); - vcdp->declBit(c+58633,"VX_cache cache_dram_req_arb prfqq pfq_queue push", false,-1); - vcdp->declBit(c+3729,"VX_cache cache_dram_req_arb prfqq pfq_queue pop", false,-1); - vcdp->declBus(c+58225,"VX_cache cache_dram_req_arb prfqq pfq_queue data_in", false,-1, 27,0); - vcdp->declBus(c+20009,"VX_cache cache_dram_req_arb prfqq pfq_queue data_out", false,-1, 27,0); - vcdp->declBit(c+20025,"VX_cache cache_dram_req_arb prfqq pfq_queue empty", false,-1); - vcdp->declBit(c+20017,"VX_cache cache_dram_req_arb prfqq pfq_queue full", false,-1); - vcdp->declBus(c+20033,"VX_cache cache_dram_req_arb prfqq pfq_queue size", false,-1, 0,0); - vcdp->declBus(c+20033,"VX_cache cache_dram_req_arb prfqq pfq_queue size_r", false,-1, 0,0); - vcdp->declBit(c+3737,"VX_cache cache_dram_req_arb prfqq pfq_queue reading", false,-1); - vcdp->declBit(c+3745,"VX_cache cache_dram_req_arb prfqq pfq_queue writing", false,-1); - {int i; for (i=0; i<2; i++) { - vcdp->declBus(c+20041+i*1,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 data", true,(i+-1), 27,0);}} - vcdp->declBus(c+20057,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 head_r", false,-1, 27,0); - vcdp->declBus(c+20065,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 curr_r", false,-1, 27,0); - vcdp->declBus(c+20073,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 wr_ptr_r", false,-1, 0,0); - vcdp->declBus(c+20081,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 rd_ptr_r", false,-1, 0,0); - vcdp->declBus(c+20089,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 0,0); - vcdp->declBit(c+20025,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+20017,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+20097,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58657,"VX_cache cache_dram_req_arb dram_fill_arb BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb DFQQ_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb dram_fill_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb dram_fill_arb reset", false,-1); - vcdp->declBit(c+3713,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_push", false,-1); - vcdp->declBus(c+2289,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_valid", false,-1, 7,0); - vcdp->declArray(c+2297,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_addr", false,-1, 223,0); - vcdp->declBit(c+297,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_pop", false,-1); - vcdp->declBit(c+3689,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req", false,-1); - vcdp->declBus(c+3697,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req_addr", false,-1, 27,0); - vcdp->declBit(c+3705,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_empty", false,-1); - vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_full", false,-1); - vcdp->declBus(c+20105,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_valid", false,-1, 7,0); - vcdp->declArray(c+20113,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_addr", false,-1, 223,0); - vcdp->declBus(c+3753,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_valid", false,-1, 7,0); - vcdp->declArray(c+3761,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_addr", false,-1, 223,0); - vcdp->declBus(c+3817,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bqual_bank_dram_fill_req_valid", false,-1, 7,0); - vcdp->declArray(c+3825,"VX_cache cache_dram_req_arb dram_fill_arb qual_bank_dram_fill_req_addr", false,-1, 223,0); - vcdp->declBus(c+3881,"VX_cache cache_dram_req_arb dram_fill_arb updated_bank_dram_fill_req_valid", false,-1, 7,0); - vcdp->declBit(c+20169,"VX_cache cache_dram_req_arb dram_fill_arb o_empty", false,-1); - vcdp->declBit(c+20177,"VX_cache cache_dram_req_arb dram_fill_arb use_empty", false,-1); - vcdp->declBit(c+3889,"VX_cache cache_dram_req_arb dram_fill_arb out_empty", false,-1); - vcdp->declBit(c+3897,"VX_cache cache_dram_req_arb dram_fill_arb push_qual", false,-1); - vcdp->declBit(c+1849,"VX_cache cache_dram_req_arb dram_fill_arb pop_qual", false,-1); - vcdp->declBus(c+3905,"VX_cache cache_dram_req_arb dram_fill_arb qual_request_index", false,-1, 2,0); - vcdp->declBit(c+3913,"VX_cache cache_dram_req_arb dram_fill_arb qual_has_request", false,-1); - vcdp->declBus(c+58729,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reset", false,-1); - vcdp->declBit(c+3897,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue push", false,-1); - vcdp->declBit(c+1849,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue pop", false,-1); - vcdp->declArray(c+3921,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_in", false,-1, 231,0); - vcdp->declArray(c+3985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_out", false,-1, 231,0); - vcdp->declBit(c+20169,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue empty", false,-1); - vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue full", false,-1); - vcdp->declBus(c+20185,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size", false,-1, 3,0); - vcdp->declBus(c+20185,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+305,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reading", false,-1); - vcdp->declBit(c+4049,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+20193+i*8,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 data", true,(i+0), 231,0);}} - vcdp->declArray(c+20705,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 head_r", false,-1, 231,0); - vcdp->declArray(c+20769,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 curr_r", false,-1, 231,0); - vcdp->declBus(c+20833,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+20841,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+20849,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+20169,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+19985,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+20857,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank reset", false,-1); - vcdp->declBus(c+3817,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank requests", false,-1, 7,0); - vcdp->declBus(c+3905,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_index", false,-1, 2,0); - vcdp->declBus(c+4057,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_onehot", false,-1, 7,0); - vcdp->declBit(c+3913,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+4057,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 grant_onehot_r", false,-1, 7,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+3817,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_in", false,-1, 7,0); - vcdp->declBus(c+3905,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_out", false,-1, 2,0); - vcdp->declBit(c+3913,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+4065,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb sel_dwb N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_dram_req_arb sel_dwb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_dram_req_arb sel_dwb reset", false,-1); - vcdp->declBus(c+2361,"VX_cache cache_dram_req_arb sel_dwb requests", false,-1, 7,0); - vcdp->declBus(c+3721,"VX_cache cache_dram_req_arb sel_dwb grant_index", false,-1, 2,0); - vcdp->declBus(c+4073,"VX_cache cache_dram_req_arb sel_dwb grant_onehot", false,-1, 7,0); - vcdp->declBit(c+3681,"VX_cache cache_dram_req_arb sel_dwb grant_valid", false,-1); - vcdp->declBus(c+4073,"VX_cache cache_dram_req_arb sel_dwb genblk2 grant_onehot_r", false,-1, 7,0); - vcdp->declBus(c+58665,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+2361,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_in", false,-1, 7,0); - vcdp->declBus(c+3721,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_out", false,-1, 2,0); - vcdp->declBit(c+3681,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+4081,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache cache_core_rsp_merge WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache cache_core_rsp_merge NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache cache_core_rsp_merge CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_core_rsp_merge clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_core_rsp_merge reset", false,-1); - vcdp->declBus(c+2129,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tid", false,-1, 15,0); - vcdp->declBus(c+2121,"VX_cache cache_core_rsp_merge per_bank_core_rsp_valid", false,-1, 7,0); - vcdp->declArray(c+2137,"VX_cache cache_core_rsp_merge per_bank_core_rsp_data", false,-1, 255,0); - vcdp->declArray(c+2201,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tag", false,-1, 335,0); - vcdp->declBus(c+9,"VX_cache cache_core_rsp_merge per_bank_core_rsp_ready", false,-1, 7,0); - vcdp->declBus(c+58137,"VX_cache cache_core_rsp_merge core_rsp_valid", false,-1, 3,0); - vcdp->declArray(c+4089,"VX_cache cache_core_rsp_merge core_rsp_data", false,-1, 127,0); - vcdp->declQuad(c+4121,"VX_cache cache_core_rsp_merge core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+58193,"VX_cache cache_core_rsp_merge core_rsp_ready", false,-1); - vcdp->declBus(c+4137,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 7,0); - vcdp->declBus(c+4145,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 2,0); - vcdp->declBit(c+4153,"VX_cache cache_core_rsp_merge grant_valid", false,-1); - vcdp->declBus(c+58737,"VX_cache cache_core_rsp_merge i", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache cache_core_rsp_merge sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache cache_core_rsp_merge sel_bank reset", false,-1); - vcdp->declBus(c+2121,"VX_cache cache_core_rsp_merge sel_bank requests", false,-1, 7,0); - vcdp->declBus(c+4145,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 2,0); - vcdp->declBus(c+4161,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 7,0); - vcdp->declBit(c+4153,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1); - vcdp->declBus(c+20865,"VX_cache cache_core_rsp_merge sel_bank genblk2 requests_use", false,-1, 7,0); - vcdp->declBus(c+4169,"VX_cache cache_core_rsp_merge sel_bank genblk2 update_value", false,-1, 7,0); - vcdp->declBus(c+4177,"VX_cache cache_core_rsp_merge sel_bank genblk2 late_value", false,-1, 7,0); - vcdp->declBit(c+20873,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill", false,-1); - vcdp->declBus(c+2121,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_value", false,-1, 7,0); - vcdp->declBus(c+20881,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_original", false,-1, 7,0); - vcdp->declBus(c+4161,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 7,0); - vcdp->declBus(c+58665,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+20865,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_in", false,-1, 7,0); - vcdp->declBus(c+4145,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 2,0); - vcdp->declBit(c+4153,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+4185,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache snp_rsp_arb NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache snp_rsp_arb BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache snp_rsp_arb SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache snp_rsp_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache snp_rsp_arb reset", false,-1); - vcdp->declBus(c+2721,"VX_cache snp_rsp_arb per_bank_snp_rsp_valid", false,-1, 7,0); - vcdp->declArray(c+2729,"VX_cache snp_rsp_arb per_bank_snp_rsp_tag", false,-1, 223,0); - vcdp->declBus(c+25,"VX_cache snp_rsp_arb per_bank_snp_rsp_ready", false,-1, 7,0); - vcdp->declBit(c+58377,"VX_cache snp_rsp_arb snp_rsp_valid", false,-1); - vcdp->declBus(c+58385,"VX_cache snp_rsp_arb snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+58393,"VX_cache snp_rsp_arb snp_rsp_ready", false,-1); - vcdp->declBus(c+4193,"VX_cache snp_rsp_arb fsq_bank", false,-1, 2,0); - vcdp->declBit(c+4201,"VX_cache snp_rsp_arb fsq_valid", false,-1); - vcdp->declBus(c+58665,"VX_cache snp_rsp_arb sel_ffsq N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache snp_rsp_arb sel_ffsq clk", false,-1); - vcdp->declBit(c+58017,"VX_cache snp_rsp_arb sel_ffsq reset", false,-1); - vcdp->declBus(c+2721,"VX_cache snp_rsp_arb sel_ffsq requests", false,-1, 7,0); - vcdp->declBus(c+4193,"VX_cache snp_rsp_arb sel_ffsq grant_index", false,-1, 2,0); - vcdp->declBus(c+4209,"VX_cache snp_rsp_arb sel_ffsq grant_onehot", false,-1, 7,0); - vcdp->declBit(c+4201,"VX_cache snp_rsp_arb sel_ffsq grant_valid", false,-1); - vcdp->declBus(c+4209,"VX_cache snp_rsp_arb sel_ffsq genblk2 grant_onehot_r", false,-1, 7,0); - vcdp->declBus(c+58665,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+2721,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_in", false,-1, 7,0); - vcdp->declBus(c+4193,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_out", false,-1, 2,0); - vcdp->declBit(c+4201,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+4217,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[0] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58745,"VX_cache genblk5[0] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[0] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[0] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[0] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[0] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank reset", false,-1); + vcdp->declBit(c+10225,"VX_cache genblk5[3] curr_bank_core_req_ready", false,-1); + vcdp->declBus(c+25073,"VX_cache cache_core_req_bank_sel BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_req_bank_sel WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_req_bank_sel NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_req_bank_sel NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+24505,"VX_cache cache_core_req_bank_sel core_req_valid", false,-1, 3,0); + vcdp->declArray(c+24529,"VX_cache cache_core_req_bank_sel core_req_addr", false,-1, 119,0); + vcdp->declBus(c+1089,"VX_cache cache_core_req_bank_sel per_bank_ready", false,-1, 3,0); + vcdp->declBus(c+1,"VX_cache cache_core_req_bank_sel per_bank_valid", false,-1, 15,0); + vcdp->declBit(c+24609,"VX_cache cache_core_req_bank_sel core_req_ready", false,-1); + vcdp->declBus(c+25129,"VX_cache cache_core_req_bank_sel i", false,-1, 31,0); + vcdp->declBus(c+161,"VX_cache cache_core_req_bank_sel genblk2 per_bank_ready_sel", false,-1, 3,0); + vcdp->declBus(c+25073,"VX_cache cache_dram_req_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache cache_dram_req_arb PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb reset", false,-1); + vcdp->declBus(c+1193,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+1201,"VX_cache cache_dram_req_arb per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBit(c+10065,"VX_cache cache_dram_req_arb dram_fill_req_ready", false,-1); + vcdp->declBus(c+1241,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_valid", false,-1, 3,0); + vcdp->declQuad(c+1249,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_byteen", false,-1, 63,0); + vcdp->declArray(c+1265,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_addr", false,-1, 111,0); + vcdp->declArray(c+1297,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_data", false,-1, 511,0); + vcdp->declBus(c+17,"VX_cache cache_dram_req_arb per_bank_dram_wb_req_ready", false,-1, 3,0); + vcdp->declBit(c+24681,"VX_cache cache_dram_req_arb dram_req_valid", false,-1); + vcdp->declBit(c+24689,"VX_cache cache_dram_req_arb dram_req_rw", false,-1); + vcdp->declBus(c+24697,"VX_cache cache_dram_req_arb dram_req_byteen", false,-1, 15,0); + vcdp->declBus(c+24705,"VX_cache cache_dram_req_arb dram_req_addr", false,-1, 27,0); + vcdp->declArray(c+24713,"VX_cache cache_dram_req_arb dram_req_data", false,-1, 127,0); + vcdp->declBit(c+24753,"VX_cache cache_dram_req_arb dram_req_ready", false,-1); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb pref_pop", false,-1); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb pref_valid", false,-1); + vcdp->declBus(c+10233,"VX_cache cache_dram_req_arb pref_addr", false,-1, 27,0); + vcdp->declBit(c+1921,"VX_cache cache_dram_req_arb dwb_valid", false,-1); + vcdp->declBit(c+1929,"VX_cache cache_dram_req_arb dfqq_req", false,-1); + vcdp->declBus(c+1937,"VX_cache cache_dram_req_arb dfqq_req_addr", false,-1, 27,0); + vcdp->declBit(c+1945,"VX_cache cache_dram_req_arb dfqq_empty", false,-1); + vcdp->declBit(c+169,"VX_cache cache_dram_req_arb dfqq_pop", false,-1); + vcdp->declBit(c+1953,"VX_cache cache_dram_req_arb dfqq_push", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dfqq_full", false,-1); + vcdp->declBus(c+1961,"VX_cache cache_dram_req_arb dwb_bank", false,-1, 1,0); + vcdp->declBus(c+25073,"VX_cache cache_dram_req_arb prfqq BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb prfqq WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb prfqq PRFQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache cache_dram_req_arb prfqq PRFQ_STRIDE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb prfqq clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb prfqq reset", false,-1); + vcdp->declBit(c+25041,"VX_cache cache_dram_req_arb prfqq dram_req", false,-1); + vcdp->declBus(c+24705,"VX_cache cache_dram_req_arb prfqq dram_req_addr", false,-1, 27,0); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb prfqq pref_pop", false,-1); + vcdp->declBit(c+25137,"VX_cache cache_dram_req_arb prfqq pref_valid", false,-1); + vcdp->declBus(c+10233,"VX_cache cache_dram_req_arb prfqq pref_addr", false,-1, 27,0); + vcdp->declBus(c+10249,"VX_cache cache_dram_req_arb prfqq use_valid", false,-1, 1,0); + vcdp->declBus(c+10233,"VX_cache cache_dram_req_arb prfqq use_addr", false,-1, 27,0); + vcdp->declBit(c+10257,"VX_cache cache_dram_req_arb prfqq current_valid", false,-1); + vcdp->declBus(c+10265,"VX_cache cache_dram_req_arb prfqq current_addr", false,-1, 27,0); + vcdp->declBit(c+10257,"VX_cache cache_dram_req_arb prfqq current_full", false,-1); + vcdp->declBit(c+10273,"VX_cache cache_dram_req_arb prfqq current_empty", false,-1); + vcdp->declBit(c+1969,"VX_cache cache_dram_req_arb prfqq update_use", false,-1); + vcdp->declBus(c+25113,"VX_cache cache_dram_req_arb prfqq pfq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb prfqq pfq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb prfqq pfq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb prfqq pfq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb prfqq pfq_queue reset", false,-1); + vcdp->declBit(c+25049,"VX_cache cache_dram_req_arb prfqq pfq_queue push", false,-1); + vcdp->declBit(c+1969,"VX_cache cache_dram_req_arb prfqq pfq_queue pop", false,-1); + vcdp->declBus(c+24705,"VX_cache cache_dram_req_arb prfqq pfq_queue data_in", false,-1, 27,0); + vcdp->declBus(c+10265,"VX_cache cache_dram_req_arb prfqq pfq_queue data_out", false,-1, 27,0); + vcdp->declBit(c+10273,"VX_cache cache_dram_req_arb prfqq pfq_queue empty", false,-1); + vcdp->declBit(c+10257,"VX_cache cache_dram_req_arb prfqq pfq_queue full", false,-1); + vcdp->declBus(c+10281,"VX_cache cache_dram_req_arb prfqq pfq_queue size", false,-1, 0,0); + vcdp->declBus(c+10281,"VX_cache cache_dram_req_arb prfqq pfq_queue size_r", false,-1, 0,0); + vcdp->declBit(c+1977,"VX_cache cache_dram_req_arb prfqq pfq_queue reading", false,-1); + vcdp->declBit(c+1985,"VX_cache cache_dram_req_arb prfqq pfq_queue writing", false,-1); + vcdp->declBus(c+10265,"VX_cache cache_dram_req_arb prfqq pfq_queue genblk2 head_r", false,-1, 27,0); + vcdp->declBus(c+25073,"VX_cache cache_dram_req_arb dram_fill_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb DFQQ_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb dram_fill_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb dram_fill_arb reset", false,-1); + vcdp->declBit(c+1953,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_push", false,-1); + vcdp->declBus(c+1193,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+1201,"VX_cache cache_dram_req_arb dram_fill_arb per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBit(c+169,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_pop", false,-1); + vcdp->declBit(c+1929,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req", false,-1); + vcdp->declBus(c+1937,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_req_addr", false,-1, 27,0); + vcdp->declBit(c+1945,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_empty", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_full", false,-1); + vcdp->declBus(c+10289,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+10297,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBus(c+1993,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+2001,"VX_cache cache_dram_req_arb dram_fill_arb out_per_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBus(c+2033,"VX_cache cache_dram_req_arb dram_fill_arb use_per_bqual_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declArray(c+2041,"VX_cache cache_dram_req_arb dram_fill_arb qual_bank_dram_fill_req_addr", false,-1, 111,0); + vcdp->declBus(c+2073,"VX_cache cache_dram_req_arb dram_fill_arb updated_bank_dram_fill_req_valid", false,-1, 3,0); + vcdp->declBit(c+10329,"VX_cache cache_dram_req_arb dram_fill_arb o_empty", false,-1); + vcdp->declBit(c+10337,"VX_cache cache_dram_req_arb dram_fill_arb use_empty", false,-1); + vcdp->declBit(c+2081,"VX_cache cache_dram_req_arb dram_fill_arb out_empty", false,-1); + vcdp->declBit(c+2089,"VX_cache cache_dram_req_arb dram_fill_arb push_qual", false,-1); + vcdp->declBit(c+953,"VX_cache cache_dram_req_arb dram_fill_arb pop_qual", false,-1); + vcdp->declBus(c+2097,"VX_cache cache_dram_req_arb dram_fill_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+2105,"VX_cache cache_dram_req_arb dram_fill_arb qual_has_request", false,-1); + vcdp->declBus(c+25145,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reset", false,-1); + vcdp->declBit(c+2089,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue push", false,-1); + vcdp->declBit(c+953,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue pop", false,-1); + vcdp->declArray(c+2113,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_in", false,-1, 115,0); + vcdp->declArray(c+2145,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue data_out", false,-1, 115,0); + vcdp->declBit(c+10329,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue empty", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue full", false,-1); + vcdp->declBus(c+10345,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size", false,-1, 2,0); + vcdp->declBus(c+10345,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+177,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue reading", false,-1); + vcdp->declBit(c+2177,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+10353+i*4,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 data", true,(i+0), 115,0);}} + vcdp->declArray(c+10481,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 head_r", false,-1, 115,0); + vcdp->declArray(c+10513,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 curr_r", false,-1, 115,0); + vcdp->declBus(c+10545,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+10553,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+10561,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+10329,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10241,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+10569,"VX_cache cache_dram_req_arb dram_fill_arb dfqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank reset", false,-1); + vcdp->declBus(c+2033,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+2097,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+2185,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2105,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+2185,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+2033,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2097,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2105,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2193,"VX_cache cache_dram_req_arb dram_fill_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb sel_dwb N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_dram_req_arb sel_dwb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_dram_req_arb sel_dwb reset", false,-1); + vcdp->declBus(c+1241,"VX_cache cache_dram_req_arb sel_dwb requests", false,-1, 3,0); + vcdp->declBus(c+1961,"VX_cache cache_dram_req_arb sel_dwb grant_index", false,-1, 1,0); + vcdp->declBus(c+2201,"VX_cache cache_dram_req_arb sel_dwb grant_onehot", false,-1, 3,0); + vcdp->declBit(c+1921,"VX_cache cache_dram_req_arb sel_dwb grant_valid", false,-1); + vcdp->declBus(c+2201,"VX_cache cache_dram_req_arb sel_dwb genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+1241,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+1961,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+1921,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2209,"VX_cache cache_dram_req_arb sel_dwb genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache cache_core_rsp_merge CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache cache_core_rsp_merge CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_core_rsp_merge clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_core_rsp_merge reset", false,-1); + vcdp->declBus(c+1105,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tid", false,-1, 7,0); + vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge per_bank_core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+1113,"VX_cache cache_core_rsp_merge per_bank_core_rsp_data", false,-1, 127,0); + vcdp->declArray(c+1145,"VX_cache cache_core_rsp_merge per_bank_core_rsp_tag", false,-1, 167,0); + vcdp->declBus(c+9,"VX_cache cache_core_rsp_merge per_bank_core_rsp_ready", false,-1, 3,0); + vcdp->declBus(c+24617,"VX_cache cache_core_rsp_merge core_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+2217,"VX_cache cache_core_rsp_merge core_rsp_data", false,-1, 127,0); + vcdp->declQuad(c+2249,"VX_cache cache_core_rsp_merge core_rsp_tag", false,-1, 41,0); + vcdp->declBit(c+24673,"VX_cache cache_core_rsp_merge core_rsp_ready", false,-1); + vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 3,0); + vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 1,0); + vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge grant_valid", false,-1); + vcdp->declBus(c+25129,"VX_cache cache_core_rsp_merge i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache cache_core_rsp_merge sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache cache_core_rsp_merge sel_bank reset", false,-1); + vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+2289,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1); + vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 requests_use", false,-1, 3,0); + vcdp->declBus(c+2297,"VX_cache cache_core_rsp_merge sel_bank genblk2 update_value", false,-1, 3,0); + vcdp->declBus(c+2305,"VX_cache cache_core_rsp_merge sel_bank genblk2 late_value", false,-1, 3,0); + vcdp->declBit(c+10585,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill", false,-1); + vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_value", false,-1, 3,0); + vcdp->declBus(c+10593,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_original", false,-1, 3,0); + vcdp->declBus(c+2289,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2313,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache snp_rsp_arb NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache snp_rsp_arb BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache snp_rsp_arb SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache snp_rsp_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache snp_rsp_arb reset", false,-1); + vcdp->declBus(c+1433,"VX_cache snp_rsp_arb per_bank_snp_rsp_valid", false,-1, 3,0); + vcdp->declArray(c+1441,"VX_cache snp_rsp_arb per_bank_snp_rsp_tag", false,-1, 111,0); + vcdp->declBus(c+25,"VX_cache snp_rsp_arb per_bank_snp_rsp_ready", false,-1, 3,0); + vcdp->declBit(c+24857,"VX_cache snp_rsp_arb snp_rsp_valid", false,-1); + vcdp->declBus(c+24865,"VX_cache snp_rsp_arb snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24873,"VX_cache snp_rsp_arb snp_rsp_ready", false,-1); + vcdp->declBus(c+2321,"VX_cache snp_rsp_arb fsq_bank", false,-1, 1,0); + vcdp->declBit(c+2329,"VX_cache snp_rsp_arb fsq_valid", false,-1); + vcdp->declBus(c+25081,"VX_cache snp_rsp_arb sel_ffsq N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache snp_rsp_arb sel_ffsq clk", false,-1); + vcdp->declBit(c+24497,"VX_cache snp_rsp_arb sel_ffsq reset", false,-1); + vcdp->declBus(c+1433,"VX_cache snp_rsp_arb sel_ffsq requests", false,-1, 3,0); + vcdp->declBus(c+2321,"VX_cache snp_rsp_arb sel_ffsq grant_index", false,-1, 1,0); + vcdp->declBus(c+2337,"VX_cache snp_rsp_arb sel_ffsq grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2329,"VX_cache snp_rsp_arb sel_ffsq grant_valid", false,-1); + vcdp->declBus(c+2337,"VX_cache snp_rsp_arb sel_ffsq genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+1433,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2321,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2329,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2345,"VX_cache snp_rsp_arb sel_ffsq genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25153,"VX_cache genblk5[0] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[0] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[0] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[0] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[0] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank reset", false,-1); vcdp->declBus(c+33,"VX_cache genblk5[0] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[0] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[0] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[0] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[0] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[0] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19689,"VX_cache genblk5[0] bank core_req_ready", false,-1); - vcdp->declBit(c+19657,"VX_cache genblk5[0] bank core_rsp_valid", false,-1); - vcdp->declBus(c+2785,"VX_cache genblk5[0] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+2793,"VX_cache genblk5[0] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+2801,"VX_cache genblk5[0] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[0] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[0] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[0] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[0] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[0] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10105,"VX_cache genblk5[0] bank core_req_ready", false,-1); + vcdp->declBit(c+10073,"VX_cache genblk5[0] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1473,"VX_cache genblk5[0] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1481,"VX_cache genblk5[0] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1489,"VX_cache genblk5[0] bank core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+41,"VX_cache genblk5[0] bank core_rsp_ready", false,-1); - vcdp->declBit(c+2817,"VX_cache genblk5[0] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19673,"VX_cache genblk5[0] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[0] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58481,"VX_cache genblk5[0] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[0] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[0] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19665,"VX_cache genblk5[0] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+2825,"VX_cache genblk5[0] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+2833,"VX_cache genblk5[0] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+2841,"VX_cache genblk5[0] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+2849,"VX_cache genblk5[0] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+1505,"VX_cache genblk5[0] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[0] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+24961,"VX_cache genblk5[0] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[0] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[0] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10081,"VX_cache genblk5[0] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1513,"VX_cache genblk5[0] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1521,"VX_cache genblk5[0] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1529,"VX_cache genblk5[0] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1537,"VX_cache genblk5[0] bank dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+49,"VX_cache genblk5[0] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58497,"VX_cache genblk5[0] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[0] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[0] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[0] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19681,"VX_cache genblk5[0] bank snp_req_ready", false,-1); - vcdp->declBit(c+2881,"VX_cache genblk5[0] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+2889,"VX_cache genblk5[0] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+24977,"VX_cache genblk5[0] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[0] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[0] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[0] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10097,"VX_cache genblk5[0] bank snp_req_ready", false,-1); + vcdp->declBit(c+1569,"VX_cache genblk5[0] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1577,"VX_cache genblk5[0] bank snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+57,"VX_cache genblk5[0] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+4225,"VX_cache genblk5[0] bank snrq_pop", false,-1); - vcdp->declBit(c+20889,"VX_cache genblk5[0] bank snrq_empty", false,-1); - vcdp->declBit(c+20897,"VX_cache genblk5[0] bank snrq_full", false,-1); - vcdp->declBus(c+4233,"VX_cache genblk5[0] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+4241,"VX_cache genblk5[0] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+4249,"VX_cache genblk5[0] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+4257,"VX_cache genblk5[0] bank dfpq_pop", false,-1); - vcdp->declBit(c+20905,"VX_cache genblk5[0] bank dfpq_empty", false,-1); - vcdp->declBit(c+20913,"VX_cache genblk5[0] bank dfpq_full", false,-1); - vcdp->declBus(c+4265,"VX_cache genblk5[0] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+4273,"VX_cache genblk5[0] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+4305,"VX_cache genblk5[0] bank reqq_pop", false,-1); - vcdp->declBit(c+1857,"VX_cache genblk5[0] bank reqq_push", false,-1); - vcdp->declBit(c+4313,"VX_cache genblk5[0] bank reqq_empty", false,-1); - vcdp->declBit(c+20921,"VX_cache genblk5[0] bank reqq_full", false,-1); - vcdp->declBit(c+4321,"VX_cache genblk5[0] bank reqq_req_st0", false,-1); - vcdp->declBus(c+4329,"VX_cache genblk5[0] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+4337,"VX_cache genblk5[0] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+4345,"VX_cache genblk5[0] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+4353,"VX_cache genblk5[0] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+4361,"VX_cache genblk5[0] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+4369,"VX_cache genblk5[0] bank mrvq_pop", false,-1); - vcdp->declBit(c+20945,"VX_cache genblk5[0] bank mrvq_full", false,-1); - vcdp->declBit(c+20953,"VX_cache genblk5[0] bank mrvq_stop", false,-1); - vcdp->declBit(c+4377,"VX_cache genblk5[0] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+20961,"VX_cache genblk5[0] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+20969,"VX_cache genblk5[0] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+20977,"VX_cache genblk5[0] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+20985,"VX_cache genblk5[0] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+20993,"VX_cache genblk5[0] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+4385,"VX_cache genblk5[0] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+21009,"VX_cache genblk5[0] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+21017,"VX_cache genblk5[0] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+21025,"VX_cache genblk5[0] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+4393,"VX_cache genblk5[0] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+4401,"VX_cache genblk5[0] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+4409,"VX_cache genblk5[0] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+21033,"VX_cache genblk5[0] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+21041,"VX_cache genblk5[0] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+21057,"VX_cache genblk5[0] bank miss_add_rw", false,-1); - vcdp->declBus(c+21065,"VX_cache genblk5[0] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19673,"VX_cache genblk5[0] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+21073,"VX_cache genblk5[0] bank is_fill_st2", false,-1); - vcdp->declBit(c+4417,"VX_cache genblk5[0] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+4425,"VX_cache genblk5[0] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+4433,"VX_cache genblk5[0] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+4441,"VX_cache genblk5[0] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+4449,"VX_cache genblk5[0] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+4457,"VX_cache genblk5[0] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+4465,"VX_cache genblk5[0] bank is_fill_in_pipe", false,-1); + vcdp->declBit(c+2353,"VX_cache genblk5[0] bank snrq_pop", false,-1); + vcdp->declBit(c+10601,"VX_cache genblk5[0] bank snrq_empty", false,-1); + vcdp->declBit(c+10609,"VX_cache genblk5[0] bank snrq_full", false,-1); + vcdp->declBus(c+2361,"VX_cache genblk5[0] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+2369,"VX_cache genblk5[0] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+2377,"VX_cache genblk5[0] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+2385,"VX_cache genblk5[0] bank dfpq_pop", false,-1); + vcdp->declBit(c+10617,"VX_cache genblk5[0] bank dfpq_empty", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[0] bank dfpq_full", false,-1); + vcdp->declBus(c+2393,"VX_cache genblk5[0] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+2401,"VX_cache genblk5[0] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+2433,"VX_cache genblk5[0] bank reqq_pop", false,-1); + vcdp->declBit(c+961,"VX_cache genblk5[0] bank reqq_push", false,-1); + vcdp->declBit(c+2441,"VX_cache genblk5[0] bank reqq_empty", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank reqq_full", false,-1); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank reqq_req_st0", false,-1); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+2465,"VX_cache genblk5[0] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+2473,"VX_cache genblk5[0] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+2481,"VX_cache genblk5[0] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+2489,"VX_cache genblk5[0] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2497,"VX_cache genblk5[0] bank mrvq_pop", false,-1); + vcdp->declBit(c+10657,"VX_cache genblk5[0] bank mrvq_full", false,-1); + vcdp->declBit(c+10665,"VX_cache genblk5[0] bank mrvq_stop", false,-1); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+10673,"VX_cache genblk5[0] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+10681,"VX_cache genblk5[0] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+10689,"VX_cache genblk5[0] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+10697,"VX_cache genblk5[0] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+10705,"VX_cache genblk5[0] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2513,"VX_cache genblk5[0] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+10721,"VX_cache genblk5[0] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+10729,"VX_cache genblk5[0] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+10737,"VX_cache genblk5[0] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+2521,"VX_cache genblk5[0] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+2529,"VX_cache genblk5[0] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+2537,"VX_cache genblk5[0] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+10745,"VX_cache genblk5[0] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+10753,"VX_cache genblk5[0] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+10769,"VX_cache genblk5[0] bank miss_add_rw", false,-1); + vcdp->declBus(c+10777,"VX_cache genblk5[0] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+10785,"VX_cache genblk5[0] bank is_fill_st2", false,-1); + vcdp->declBit(c+2545,"VX_cache genblk5[0] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+2553,"VX_cache genblk5[0] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+2561,"VX_cache genblk5[0] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+2569,"VX_cache genblk5[0] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+2577,"VX_cache genblk5[0] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+2593,"VX_cache genblk5[0] bank is_fill_in_pipe", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+4473+i*1,"VX_cache genblk5[0] bank is_fill_st1", true,(i+0));}} + vcdp->declBit(c+2601+i*1,"VX_cache genblk5[0] bank is_fill_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+4481+i*1,"VX_cache genblk5[0] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[0] bank j", false,-1, 31,0); - vcdp->declBit(c+4377,"VX_cache genblk5[0] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+4489,"VX_cache genblk5[0] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+4497,"VX_cache genblk5[0] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+4505,"VX_cache genblk5[0] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+4489,"VX_cache genblk5[0] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+4513,"VX_cache genblk5[0] bank qual_valid_st0", false,-1); - vcdp->declBus(c+4521,"VX_cache genblk5[0] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+4529,"VX_cache genblk5[0] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+4377,"VX_cache genblk5[0] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+4537,"VX_cache genblk5[0] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+4545,"VX_cache genblk5[0] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+4577,"VX_cache genblk5[0] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+4593,"VX_cache genblk5[0] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+4601,"VX_cache genblk5[0] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+4609,"VX_cache genblk5[0] bank qual_snp_invalidate_st0", false,-1); + vcdp->declBit(c+2609+i*1,"VX_cache genblk5[0] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[0] bank j", false,-1, 31,0); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+2617,"VX_cache genblk5[0] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+2625,"VX_cache genblk5[0] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+2633,"VX_cache genblk5[0] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+2617,"VX_cache genblk5[0] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+2641,"VX_cache genblk5[0] bank qual_valid_st0", false,-1); + vcdp->declBus(c+2649,"VX_cache genblk5[0] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+2657,"VX_cache genblk5[0] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+2665,"VX_cache genblk5[0] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+2673,"VX_cache genblk5[0] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+2705,"VX_cache genblk5[0] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+2721,"VX_cache genblk5[0] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+2729,"VX_cache genblk5[0] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+2737,"VX_cache genblk5[0] bank qual_snp_invalidate_st0", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+4617+i*1,"VX_cache genblk5[0] bank valid_st1", true,(i+0));}} + vcdp->declBit(c+2745+i*1,"VX_cache genblk5[0] bank valid_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+4625+i*1,"VX_cache genblk5[0] bank addr_st1", true,(i+0), 24,0);}} + vcdp->declBus(c+2753+i*1,"VX_cache genblk5[0] bank addr_st1", true,(i+0), 25,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+4633+i*1,"VX_cache genblk5[0] bank wsel_st1", true,(i+0), 1,0);}} + vcdp->declBus(c+2761+i*1,"VX_cache genblk5[0] bank wsel_st1", true,(i+0), 1,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+4641+i*1,"VX_cache genblk5[0] bank writeword_st1", true,(i+0), 31,0);}} + vcdp->declBus(c+2769+i*1,"VX_cache genblk5[0] bank writeword_st1", true,(i+0), 31,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+4649+i*2,"VX_cache genblk5[0] bank inst_meta_st1", true,(i+0), 48,0);}} + vcdp->declQuad(c+2777+i*2,"VX_cache genblk5[0] bank inst_meta_st1", true,(i+0), 48,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+4665+i*4,"VX_cache genblk5[0] bank writedata_st1", true,(i+0), 127,0);}} + vcdp->declArray(c+2793+i*4,"VX_cache genblk5[0] bank writedata_st1", true,(i+0), 127,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+4697+i*1,"VX_cache genblk5[0] bank is_snp_st1", true,(i+0));}} + vcdp->declBit(c+2825+i*1,"VX_cache genblk5[0] bank is_snp_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+4705+i*1,"VX_cache genblk5[0] bank snp_invalidate_st1", true,(i+0));}} + vcdp->declBit(c+2833+i*1,"VX_cache genblk5[0] bank snp_invalidate_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+4713+i*1,"VX_cache genblk5[0] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+4721,"VX_cache genblk5[0] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+4729,"VX_cache genblk5[0] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+4761,"VX_cache genblk5[0] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+4769,"VX_cache genblk5[0] bank miss_st1e", false,-1); - vcdp->declBit(c+4777,"VX_cache genblk5[0] bank dirty_st1e", false,-1); - vcdp->declBus(c+4785,"VX_cache genblk5[0] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+4793,"VX_cache genblk5[0] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+4809,"VX_cache genblk5[0] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+4817,"VX_cache genblk5[0] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+4825,"VX_cache genblk5[0] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+4833,"VX_cache genblk5[0] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+4841,"VX_cache genblk5[0] bank is_snp_st1e", false,-1); - vcdp->declBit(c+4849,"VX_cache genblk5[0] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+4857,"VX_cache genblk5[0] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+4865,"VX_cache genblk5[0] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+4873,"VX_cache genblk5[0] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+4881,"VX_cache genblk5[0] bank valid_st1e", false,-1); - vcdp->declBit(c+4889,"VX_cache genblk5[0] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+4897,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+4905,"VX_cache genblk5[0] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+4913,"VX_cache genblk5[0] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+4889,"VX_cache genblk5[0] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+21081,"VX_cache genblk5[0] bank valid_st2", false,-1); - vcdp->declBus(c+21089,"VX_cache genblk5[0] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+21097,"VX_cache genblk5[0] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+21105,"VX_cache genblk5[0] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+21113,"VX_cache genblk5[0] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+21145,"VX_cache genblk5[0] bank miss_st2", false,-1); - vcdp->declBit(c+21153,"VX_cache genblk5[0] bank dirty_st2", false,-1); - vcdp->declBus(c+21161,"VX_cache genblk5[0] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+21169,"VX_cache genblk5[0] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+21185,"VX_cache genblk5[0] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+21193,"VX_cache genblk5[0] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+21201,"VX_cache genblk5[0] bank is_snp_st2", false,-1); - vcdp->declBit(c+21209,"VX_cache genblk5[0] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+21217,"VX_cache genblk5[0] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+21225,"VX_cache genblk5[0] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+4921,"VX_cache genblk5[0] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+21233,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+21241,"VX_cache genblk5[0] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+4929,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+4937,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+21217,"VX_cache genblk5[0] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+4945,"VX_cache genblk5[0] bank miss_add_unqual", false,-1); - vcdp->declBit(c+4953,"VX_cache genblk5[0] bank miss_add", false,-1); - vcdp->declBus(c+19673,"VX_cache genblk5[0] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+21089,"VX_cache genblk5[0] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+21097,"VX_cache genblk5[0] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+21201,"VX_cache genblk5[0] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+21209,"VX_cache genblk5[0] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+4961,"VX_cache genblk5[0] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+4969,"VX_cache genblk5[0] bank cwbq_push", false,-1); - vcdp->declBit(c+1865,"VX_cache genblk5[0] bank cwbq_pop", false,-1); - vcdp->declBit(c+21249,"VX_cache genblk5[0] bank cwbq_empty", false,-1); - vcdp->declBit(c+21257,"VX_cache genblk5[0] bank cwbq_full", false,-1); - vcdp->declBit(c+4977,"VX_cache genblk5[0] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+21105,"VX_cache genblk5[0] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+21033,"VX_cache genblk5[0] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+21041,"VX_cache genblk5[0] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+4945,"VX_cache genblk5[0] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+4985,"VX_cache genblk5[0] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+4993,"VX_cache genblk5[0] bank dwbq_push", false,-1); - vcdp->declBit(c+1873,"VX_cache genblk5[0] bank dwbq_pop", false,-1); - vcdp->declBit(c+21265,"VX_cache genblk5[0] bank dwbq_empty", false,-1); - vcdp->declBit(c+21273,"VX_cache genblk5[0] bank dwbq_full", false,-1); - vcdp->declBit(c+5001,"VX_cache genblk5[0] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+5009,"VX_cache genblk5[0] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+5017,"VX_cache genblk5[0] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+5025,"VX_cache genblk5[0] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+5033,"VX_cache genblk5[0] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+21281,"VX_cache genblk5[0] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+21289,"VX_cache genblk5[0] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+313,"VX_cache genblk5[0] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+321,"VX_cache genblk5[0] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+21297,"VX_cache genblk5[0] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[0] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58497,"VX_cache genblk5[0] bank snp_req_queue push", false,-1); - vcdp->declBit(c+4225,"VX_cache genblk5[0] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+329,"VX_cache genblk5[0] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+5041,"VX_cache genblk5[0] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+20889,"VX_cache genblk5[0] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+20897,"VX_cache genblk5[0] bank snp_req_queue full", false,-1); - vcdp->declBus(c+21305,"VX_cache genblk5[0] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+21305,"VX_cache genblk5[0] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+5057,"VX_cache genblk5[0] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+345,"VX_cache genblk5[0] bank snp_req_queue writing", false,-1); + vcdp->declBit(c+2841+i*1,"VX_cache genblk5[0] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+2849,"VX_cache genblk5[0] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+2857,"VX_cache genblk5[0] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+2889,"VX_cache genblk5[0] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank miss_st1e", false,-1); + vcdp->declBit(c+2905,"VX_cache genblk5[0] bank dirty_st1e", false,-1); + vcdp->declBus(c+2913,"VX_cache genblk5[0] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+2921,"VX_cache genblk5[0] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+2937,"VX_cache genblk5[0] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+2945,"VX_cache genblk5[0] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+2953,"VX_cache genblk5[0] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+2961,"VX_cache genblk5[0] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+2969,"VX_cache genblk5[0] bank is_snp_st1e", false,-1); + vcdp->declBit(c+2977,"VX_cache genblk5[0] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+2985,"VX_cache genblk5[0] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+2993,"VX_cache genblk5[0] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+3001,"VX_cache genblk5[0] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+3009,"VX_cache genblk5[0] bank valid_st1e", false,-1); + vcdp->declBit(c+3017,"VX_cache genblk5[0] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+3025,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+3033,"VX_cache genblk5[0] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+3041,"VX_cache genblk5[0] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+3017,"VX_cache genblk5[0] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+10793,"VX_cache genblk5[0] bank valid_st2", false,-1); + vcdp->declBus(c+10801,"VX_cache genblk5[0] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+10809,"VX_cache genblk5[0] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+10817,"VX_cache genblk5[0] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+10825,"VX_cache genblk5[0] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+10857,"VX_cache genblk5[0] bank miss_st2", false,-1); + vcdp->declBit(c+10865,"VX_cache genblk5[0] bank dirty_st2", false,-1); + vcdp->declBus(c+10873,"VX_cache genblk5[0] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+10881,"VX_cache genblk5[0] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+10897,"VX_cache genblk5[0] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+10905,"VX_cache genblk5[0] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+10913,"VX_cache genblk5[0] bank is_snp_st2", false,-1); + vcdp->declBit(c+10921,"VX_cache genblk5[0] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+10929,"VX_cache genblk5[0] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+10937,"VX_cache genblk5[0] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+3049,"VX_cache genblk5[0] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+10945,"VX_cache genblk5[0] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+10953,"VX_cache genblk5[0] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+3057,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+3065,"VX_cache genblk5[0] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+10929,"VX_cache genblk5[0] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+3073,"VX_cache genblk5[0] bank miss_add_unqual", false,-1); + vcdp->declBit(c+3081,"VX_cache genblk5[0] bank miss_add", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+10801,"VX_cache genblk5[0] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+10809,"VX_cache genblk5[0] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+10913,"VX_cache genblk5[0] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+10921,"VX_cache genblk5[0] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+3089,"VX_cache genblk5[0] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+3097,"VX_cache genblk5[0] bank cwbq_push", false,-1); + vcdp->declBit(c+969,"VX_cache genblk5[0] bank cwbq_pop", false,-1); + vcdp->declBit(c+10961,"VX_cache genblk5[0] bank cwbq_empty", false,-1); + vcdp->declBit(c+10969,"VX_cache genblk5[0] bank cwbq_full", false,-1); + vcdp->declBit(c+3105,"VX_cache genblk5[0] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+10817,"VX_cache genblk5[0] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+10745,"VX_cache genblk5[0] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+10753,"VX_cache genblk5[0] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+3073,"VX_cache genblk5[0] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+3113,"VX_cache genblk5[0] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+3121,"VX_cache genblk5[0] bank dwbq_push", false,-1); + vcdp->declBit(c+977,"VX_cache genblk5[0] bank dwbq_pop", false,-1); + vcdp->declBit(c+10977,"VX_cache genblk5[0] bank dwbq_empty", false,-1); + vcdp->declBit(c+10985,"VX_cache genblk5[0] bank dwbq_full", false,-1); + vcdp->declBit(c+3129,"VX_cache genblk5[0] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+3137,"VX_cache genblk5[0] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+3145,"VX_cache genblk5[0] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+3153,"VX_cache genblk5[0] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+3161,"VX_cache genblk5[0] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+10993,"VX_cache genblk5[0] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+11001,"VX_cache genblk5[0] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+185,"VX_cache genblk5[0] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+193,"VX_cache genblk5[0] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+11009,"VX_cache genblk5[0] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[0] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+24977,"VX_cache genblk5[0] bank snp_req_queue push", false,-1); + vcdp->declBit(c+2353,"VX_cache genblk5[0] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+201,"VX_cache genblk5[0] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+3169,"VX_cache genblk5[0] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+10601,"VX_cache genblk5[0] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+10609,"VX_cache genblk5[0] bank snp_req_queue full", false,-1); + vcdp->declBus(c+11017,"VX_cache genblk5[0] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+11017,"VX_cache genblk5[0] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+3185,"VX_cache genblk5[0] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+217,"VX_cache genblk5[0] bank snp_req_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+21313+i*2,"VX_cache genblk5[0] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+21569,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+21585,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+21601,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+21609,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+21617,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+20889,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+20897,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+21625,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[0] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58481,"VX_cache genblk5[0] bank dfp_queue push", false,-1); - vcdp->declBit(c+4257,"VX_cache genblk5[0] bank dfp_queue pop", false,-1); - vcdp->declArray(c+353,"VX_cache genblk5[0] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+5065,"VX_cache genblk5[0] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+20905,"VX_cache genblk5[0] bank dfp_queue empty", false,-1); - vcdp->declBit(c+20913,"VX_cache genblk5[0] bank dfp_queue full", false,-1); - vcdp->declBus(c+21633,"VX_cache genblk5[0] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+21633,"VX_cache genblk5[0] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+5105,"VX_cache genblk5[0] bank dfp_queue reading", false,-1); - vcdp->declBit(c+393,"VX_cache genblk5[0] bank dfp_queue writing", false,-1); + vcdp->declQuad(c+11025+i*2,"VX_cache genblk5[0] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+11281,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+11297,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+11313,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+11321,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+11329,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+10601,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10609,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+11337,"VX_cache genblk5[0] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[0] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank dfp_queue reset", false,-1); + vcdp->declBit(c+24961,"VX_cache genblk5[0] bank dfp_queue push", false,-1); + vcdp->declBit(c+2385,"VX_cache genblk5[0] bank dfp_queue pop", false,-1); + vcdp->declArray(c+225,"VX_cache genblk5[0] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+3193,"VX_cache genblk5[0] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+10617,"VX_cache genblk5[0] bank dfp_queue empty", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[0] bank dfp_queue full", false,-1); + vcdp->declBus(c+11345,"VX_cache genblk5[0] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+11345,"VX_cache genblk5[0] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+3233,"VX_cache genblk5[0] bank dfp_queue reading", false,-1); + vcdp->declBit(c+265,"VX_cache genblk5[0] bank dfp_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+21641+i*5,"VX_cache genblk5[0] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+22281,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+22321,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+22361,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+22369,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+22377,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+20905,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+20913,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+22385,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank core_req_arb reset", false,-1); - vcdp->declBit(c+1857,"VX_cache genblk5[0] bank core_req_arb reqq_push", false,-1); + vcdp->declArray(c+11353+i*5,"VX_cache genblk5[0] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+11993,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+12033,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+12073,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+12081,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+12089,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+10617,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10625,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+12097,"VX_cache genblk5[0] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[0] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank core_req_arb reset", false,-1); + vcdp->declBit(c+961,"VX_cache genblk5[0] bank core_req_arb reqq_push", false,-1); vcdp->declBus(c+33,"VX_cache genblk5[0] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[0] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[0] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[0] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[0] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[0] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+4305,"VX_cache genblk5[0] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+4337,"VX_cache genblk5[0] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+4345,"VX_cache genblk5[0] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+4353,"VX_cache genblk5[0] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+4361,"VX_cache genblk5[0] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+4313,"VX_cache genblk5[0] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+20921,"VX_cache genblk5[0] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+5113,"VX_cache genblk5[0] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+5121,"VX_cache genblk5[0] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+5129,"VX_cache genblk5[0] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+5137,"VX_cache genblk5[0] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+5169,"VX_cache genblk5[0] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+5201,"VX_cache genblk5[0] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+22401,"VX_cache genblk5[0] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+22409,"VX_cache genblk5[0] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+22417,"VX_cache genblk5[0] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+22449,"VX_cache genblk5[0] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+22401,"VX_cache genblk5[0] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+22409,"VX_cache genblk5[0] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+22417,"VX_cache genblk5[0] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+22449,"VX_cache genblk5[0] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+20929,"VX_cache genblk5[0] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+22481,"VX_cache genblk5[0] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+22489,"VX_cache genblk5[0] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+5217,"VX_cache genblk5[0] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+1881,"VX_cache genblk5[0] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+5225,"VX_cache genblk5[0] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+5233,"VX_cache genblk5[0] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[0] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+1881,"VX_cache genblk5[0] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+5225,"VX_cache genblk5[0] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+401,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+5241,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+22481,"VX_cache genblk5[0] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+20921,"VX_cache genblk5[0] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+22497,"VX_cache genblk5[0] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+22497,"VX_cache genblk5[0] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+5321,"VX_cache genblk5[0] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+481,"VX_cache genblk5[0] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+22505+i*10,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+23145,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+23225,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+23305,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+23313,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+23321,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+22481,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+20921,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+23329,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+5329,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+5329,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+22393,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+4329,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+4321,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+5337,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[0] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[0] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+4457,"VX_cache genblk5[0] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[0] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+5345,"VX_cache genblk5[0] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+23337,"VX_cache genblk5[0] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+23337,"VX_cache genblk5[0] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[0] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank tag_data_access reset", false,-1); - vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access stall", false,-1); - vcdp->declBit(c+4841,"VX_cache genblk5[0] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+4849,"VX_cache genblk5[0] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+4409,"VX_cache genblk5[0] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+4905,"VX_cache genblk5[0] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+4881,"VX_cache genblk5[0] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+5417,"VX_cache genblk5[0] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+5425,"VX_cache genblk5[0] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+5433,"VX_cache genblk5[0] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+4817,"VX_cache genblk5[0] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+4825,"VX_cache genblk5[0] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+5465,"VX_cache genblk5[0] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+4721,"VX_cache genblk5[0] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+4729,"VX_cache genblk5[0] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+4761,"VX_cache genblk5[0] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+4769,"VX_cache genblk5[0] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+4777,"VX_cache genblk5[0] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+4785,"VX_cache genblk5[0] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+4833,"VX_cache genblk5[0] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+4857,"VX_cache genblk5[0] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+4865,"VX_cache genblk5[0] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+5473+i*1,"VX_cache genblk5[0] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+5481+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+5489+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+5497+i*1,"VX_cache genblk5[0] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+5505+i*4,"VX_cache genblk5[0] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+5537,"VX_cache genblk5[0] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+5545,"VX_cache genblk5[0] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+5553,"VX_cache genblk5[0] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+5561,"VX_cache genblk5[0] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+5569,"VX_cache genblk5[0] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+5601,"VX_cache genblk5[0] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+5609,"VX_cache genblk5[0] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+4785,"VX_cache genblk5[0] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+4761,"VX_cache genblk5[0] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+4729,"VX_cache genblk5[0] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+5617,"VX_cache genblk5[0] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+5625,"VX_cache genblk5[0] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+4769,"VX_cache genblk5[0] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+5657,"VX_cache genblk5[0] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+5665,"VX_cache genblk5[0] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+5673,"VX_cache genblk5[0] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+5681,"VX_cache genblk5[0] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+5689,"VX_cache genblk5[0] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+5625,"VX_cache genblk5[0] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+5697,"VX_cache genblk5[0] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+5657,"VX_cache genblk5[0] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+5705,"VX_cache genblk5[0] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+5713,"VX_cache genblk5[0] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+5721,"VX_cache genblk5[0] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+5729,"VX_cache genblk5[0] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+5737,"VX_cache genblk5[0] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+5745,"VX_cache genblk5[0] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+5753,"VX_cache genblk5[0] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+5761,"VX_cache genblk5[0] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[0] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+5537,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+5545,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+5553,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+5561,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+5569,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+5657,"VX_cache genblk5[0] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+5617,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+5673,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+5409,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+5681,"VX_cache genblk5[0] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+5625,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+4769,"VX_cache genblk5[0] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+23401,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+23433,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+23465,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+23497,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+23529,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+23561,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+23593,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+23625,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+23657,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+23689,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+23721,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+23753,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+23785,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+23817,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+23849,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+23881,"VX_cache genblk5[0] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+23913+i*1,"VX_cache genblk5[0] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+24041,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+24049,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+24057,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+24065,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+24073,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+24081,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+24089,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+24097,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+24105,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+24113,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+24121,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+24129,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+24137,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+24145,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+24153,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+24161,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+24169,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+24177,"VX_cache genblk5[0] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+5769,"VX_cache genblk5[0] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+24185,"VX_cache genblk5[0] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+24193,"VX_cache genblk5[0] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+4457,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+5777,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+5777,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+24201,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[0] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[0] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+4457,"VX_cache genblk5[0] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[0] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+5825,"VX_cache genblk5[0] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+24249,"VX_cache genblk5[0] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+24249,"VX_cache genblk5[0] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[0] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58745,"VX_cache genblk5[0] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[0] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[0] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[0] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+4953,"VX_cache genblk5[0] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+4961,"VX_cache genblk5[0] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19673,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+21089,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+21097,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+21033,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+21041,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+21057,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+21065,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+4921,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+21201,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+21209,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+20945,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+20953,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+5417,"VX_cache genblk5[0] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+4905,"VX_cache genblk5[0] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+4393,"VX_cache genblk5[0] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+4369,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+4377,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+20969,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+20977,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+20985,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+20961,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+20993,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+4385,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+21009,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+21017,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+21025,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+24329+i*3,"VX_cache genblk5[0] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+24713,"VX_cache genblk5[0] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+24817,"VX_cache genblk5[0] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+24825,"VX_cache genblk5[0] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+24833,"VX_cache genblk5[0] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+24841,"VX_cache genblk5[0] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+24849,"VX_cache genblk5[0] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+24857,"VX_cache genblk5[0] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+24865,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+24849,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+5905,"VX_cache genblk5[0] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+5913,"VX_cache genblk5[0] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+5921,"VX_cache genblk5[0] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+4377,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+24833,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+5929,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+5937,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+5945,"VX_cache genblk5[0] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+5953,"VX_cache genblk5[0] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+5961,"VX_cache genblk5[0] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+5969,"VX_cache genblk5[0] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[0] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[0] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank cwb_queue reset", false,-1); - vcdp->declBit(c+4969,"VX_cache genblk5[0] bank cwb_queue push", false,-1); - vcdp->declBit(c+1865,"VX_cache genblk5[0] bank cwb_queue pop", false,-1); - vcdp->declArray(c+5977,"VX_cache genblk5[0] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+6001,"VX_cache genblk5[0] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+21249,"VX_cache genblk5[0] bank cwb_queue empty", false,-1); - vcdp->declBit(c+21257,"VX_cache genblk5[0] bank cwb_queue full", false,-1); - vcdp->declBus(c+24873,"VX_cache genblk5[0] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+24873,"VX_cache genblk5[0] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+489,"VX_cache genblk5[0] bank cwb_queue reading", false,-1); - vcdp->declBit(c+6025,"VX_cache genblk5[0] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+24881+i*3,"VX_cache genblk5[0] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+25073,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+25097,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+25121,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+25129,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+25137,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+21249,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+21257,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+25145,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[0] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[0] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[0] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[0] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[0] bank dwb_queue reset", false,-1); - vcdp->declBit(c+4993,"VX_cache genblk5[0] bank dwb_queue push", false,-1); - vcdp->declBit(c+1873,"VX_cache genblk5[0] bank dwb_queue pop", false,-1); - vcdp->declArray(c+6033,"VX_cache genblk5[0] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+6089,"VX_cache genblk5[0] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+21265,"VX_cache genblk5[0] bank dwb_queue empty", false,-1); - vcdp->declBit(c+21273,"VX_cache genblk5[0] bank dwb_queue full", false,-1); - vcdp->declBus(c+25153,"VX_cache genblk5[0] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+25153,"VX_cache genblk5[0] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+497,"VX_cache genblk5[0] bank dwb_queue reading", false,-1); - vcdp->declBit(c+6145,"VX_cache genblk5[0] bank dwb_queue writing", false,-1); + vcdp->declBus(c+24513,"VX_cache genblk5[0] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[0] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[0] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[0] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[0] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+2433,"VX_cache genblk5[0] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+2465,"VX_cache genblk5[0] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+2473,"VX_cache genblk5[0] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+2481,"VX_cache genblk5[0] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+2489,"VX_cache genblk5[0] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2441,"VX_cache genblk5[0] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+3241,"VX_cache genblk5[0] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+3249,"VX_cache genblk5[0] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+3257,"VX_cache genblk5[0] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+3265,"VX_cache genblk5[0] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+3297,"VX_cache genblk5[0] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+3329,"VX_cache genblk5[0] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+12113,"VX_cache genblk5[0] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+12121,"VX_cache genblk5[0] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+12129,"VX_cache genblk5[0] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+12161,"VX_cache genblk5[0] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+12113,"VX_cache genblk5[0] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+12121,"VX_cache genblk5[0] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+12129,"VX_cache genblk5[0] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+12161,"VX_cache genblk5[0] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+10641,"VX_cache genblk5[0] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+12193,"VX_cache genblk5[0] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+12201,"VX_cache genblk5[0] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+3345,"VX_cache genblk5[0] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+985,"VX_cache genblk5[0] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+3353,"VX_cache genblk5[0] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+3361,"VX_cache genblk5[0] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[0] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+985,"VX_cache genblk5[0] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+3353,"VX_cache genblk5[0] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+273,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+3369,"VX_cache genblk5[0] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+12193,"VX_cache genblk5[0] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+12209,"VX_cache genblk5[0] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+12209,"VX_cache genblk5[0] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+3449,"VX_cache genblk5[0] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+353,"VX_cache genblk5[0] bank core_req_arb reqq_queue writing", false,-1); {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+25161+i*7,"VX_cache genblk5[0] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+25385,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+25441,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+25497,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+25505,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+25513,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+21265,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+21273,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+25521,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58641,"VX_cache genblk5[1] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58753,"VX_cache genblk5[1] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[1] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[1] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[1] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[1] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank reset", false,-1); + vcdp->declArray(c+12217+i*10,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+12537,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+12617,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+12697,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+12705,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+12713,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+12193,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10633,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+12721,"VX_cache genblk5[0] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+3457,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+3457,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+12105,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+2457,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2449,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+3465,"VX_cache genblk5[0] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[0] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[0] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+3473,"VX_cache genblk5[0] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+12729,"VX_cache genblk5[0] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+12729,"VX_cache genblk5[0] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[0] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank tag_data_access reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access stall", false,-1); + vcdp->declBit(c+2969,"VX_cache genblk5[0] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+2977,"VX_cache genblk5[0] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+2537,"VX_cache genblk5[0] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+3033,"VX_cache genblk5[0] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+3009,"VX_cache genblk5[0] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+3545,"VX_cache genblk5[0] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+3553,"VX_cache genblk5[0] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+3561,"VX_cache genblk5[0] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+2945,"VX_cache genblk5[0] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+2953,"VX_cache genblk5[0] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+3593,"VX_cache genblk5[0] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+2849,"VX_cache genblk5[0] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+2857,"VX_cache genblk5[0] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+2889,"VX_cache genblk5[0] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+2905,"VX_cache genblk5[0] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+2913,"VX_cache genblk5[0] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+2961,"VX_cache genblk5[0] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+2985,"VX_cache genblk5[0] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+2993,"VX_cache genblk5[0] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+3601+i*1,"VX_cache genblk5[0] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+3609+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+3617+i*1,"VX_cache genblk5[0] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+3625+i*1,"VX_cache genblk5[0] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+3633+i*4,"VX_cache genblk5[0] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+3665,"VX_cache genblk5[0] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+3673,"VX_cache genblk5[0] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+3681,"VX_cache genblk5[0] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+3689,"VX_cache genblk5[0] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+3697,"VX_cache genblk5[0] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+3729,"VX_cache genblk5[0] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+3737,"VX_cache genblk5[0] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+2913,"VX_cache genblk5[0] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+2889,"VX_cache genblk5[0] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+2857,"VX_cache genblk5[0] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+3745,"VX_cache genblk5[0] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+3753,"VX_cache genblk5[0] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+3785,"VX_cache genblk5[0] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+3793,"VX_cache genblk5[0] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+3801,"VX_cache genblk5[0] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+3809,"VX_cache genblk5[0] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+3817,"VX_cache genblk5[0] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+3753,"VX_cache genblk5[0] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+3825,"VX_cache genblk5[0] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+3785,"VX_cache genblk5[0] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+3833,"VX_cache genblk5[0] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+3841,"VX_cache genblk5[0] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+3849,"VX_cache genblk5[0] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+3857,"VX_cache genblk5[0] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+3865,"VX_cache genblk5[0] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+3873,"VX_cache genblk5[0] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+3881,"VX_cache genblk5[0] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+3889,"VX_cache genblk5[0] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[0] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+3665,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+3673,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+3681,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+3689,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+3697,"VX_cache genblk5[0] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+3785,"VX_cache genblk5[0] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+3745,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+3801,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+3537,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+3809,"VX_cache genblk5[0] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+3753,"VX_cache genblk5[0] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+2897,"VX_cache genblk5[0] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+12793,"VX_cache genblk5[0] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+12809,"VX_cache genblk5[0] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+3897,"VX_cache genblk5[0] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+12825,"VX_cache genblk5[0] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+12833,"VX_cache genblk5[0] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+3905,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+3905,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+12841,"VX_cache genblk5[0] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[0] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+2585,"VX_cache genblk5[0] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[0] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+3953,"VX_cache genblk5[0] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+12889,"VX_cache genblk5[0] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+12889,"VX_cache genblk5[0] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[0] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25153,"VX_cache genblk5[0] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[0] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[0] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[0] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+3081,"VX_cache genblk5[0] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+3089,"VX_cache genblk5[0] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10089,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+10801,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+10809,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+10745,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+10753,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+10769,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+10777,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+3049,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+10913,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+10921,"VX_cache genblk5[0] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+10657,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+10665,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+3545,"VX_cache genblk5[0] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+3033,"VX_cache genblk5[0] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+2521,"VX_cache genblk5[0] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+2497,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+10681,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+10689,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+10697,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+10673,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+10705,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+2513,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+10721,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+10729,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+10737,"VX_cache genblk5[0] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+12969+i*3,"VX_cache genblk5[0] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+13353,"VX_cache genblk5[0] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+13457,"VX_cache genblk5[0] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+13465,"VX_cache genblk5[0] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+13473,"VX_cache genblk5[0] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+13481,"VX_cache genblk5[0] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+13489,"VX_cache genblk5[0] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+13497,"VX_cache genblk5[0] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+13505,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+13489,"VX_cache genblk5[0] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+4033,"VX_cache genblk5[0] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+4041,"VX_cache genblk5[0] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+4049,"VX_cache genblk5[0] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+2505,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+13473,"VX_cache genblk5[0] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+4057,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+4065,"VX_cache genblk5[0] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+4073,"VX_cache genblk5[0] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+4081,"VX_cache genblk5[0] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+4089,"VX_cache genblk5[0] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+4097,"VX_cache genblk5[0] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[0] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank cwb_queue reset", false,-1); + vcdp->declBit(c+3097,"VX_cache genblk5[0] bank cwb_queue push", false,-1); + vcdp->declBit(c+969,"VX_cache genblk5[0] bank cwb_queue pop", false,-1); + vcdp->declArray(c+4105,"VX_cache genblk5[0] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+4129,"VX_cache genblk5[0] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+10961,"VX_cache genblk5[0] bank cwb_queue empty", false,-1); + vcdp->declBit(c+10969,"VX_cache genblk5[0] bank cwb_queue full", false,-1); + vcdp->declBus(c+13513,"VX_cache genblk5[0] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+13513,"VX_cache genblk5[0] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+361,"VX_cache genblk5[0] bank cwb_queue reading", false,-1); + vcdp->declBit(c+4153,"VX_cache genblk5[0] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+13521+i*3,"VX_cache genblk5[0] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+13617,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+13641,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+13665,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+13673,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+13681,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+10961,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10969,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+13689,"VX_cache genblk5[0] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[0] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[0] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[0] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[0] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[0] bank dwb_queue reset", false,-1); + vcdp->declBit(c+3121,"VX_cache genblk5[0] bank dwb_queue push", false,-1); + vcdp->declBit(c+977,"VX_cache genblk5[0] bank dwb_queue pop", false,-1); + vcdp->declArray(c+4161,"VX_cache genblk5[0] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+4217,"VX_cache genblk5[0] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+10977,"VX_cache genblk5[0] bank dwb_queue empty", false,-1); + vcdp->declBit(c+10985,"VX_cache genblk5[0] bank dwb_queue full", false,-1); + vcdp->declBus(c+13697,"VX_cache genblk5[0] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+13697,"VX_cache genblk5[0] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+369,"VX_cache genblk5[0] bank dwb_queue reading", false,-1); + vcdp->declBit(c+4273,"VX_cache genblk5[0] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+13705+i*7,"VX_cache genblk5[0] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+13929,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+13985,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+14041,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+14049,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+14057,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+10977,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+10985,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+14065,"VX_cache genblk5[0] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25161,"VX_cache genblk5[1] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[1] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[1] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[1] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[1] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank reset", false,-1); vcdp->declBus(c+65,"VX_cache genblk5[1] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[1] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[1] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[1] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[1] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[1] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19729,"VX_cache genblk5[1] bank core_req_ready", false,-1); - vcdp->declBit(c+19697,"VX_cache genblk5[1] bank core_rsp_valid", false,-1); - vcdp->declBus(c+2897,"VX_cache genblk5[1] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+2905,"VX_cache genblk5[1] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+2913,"VX_cache genblk5[1] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[1] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[1] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[1] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[1] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[1] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10145,"VX_cache genblk5[1] bank core_req_ready", false,-1); + vcdp->declBit(c+10113,"VX_cache genblk5[1] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1585,"VX_cache genblk5[1] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1593,"VX_cache genblk5[1] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1601,"VX_cache genblk5[1] bank core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+73,"VX_cache genblk5[1] bank core_rsp_ready", false,-1); - vcdp->declBit(c+2929,"VX_cache genblk5[1] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19713,"VX_cache genblk5[1] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[1] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58513,"VX_cache genblk5[1] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[1] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[1] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19705,"VX_cache genblk5[1] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+2937,"VX_cache genblk5[1] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+2945,"VX_cache genblk5[1] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+2953,"VX_cache genblk5[1] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+2961,"VX_cache genblk5[1] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+1617,"VX_cache genblk5[1] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[1] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+24993,"VX_cache genblk5[1] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[1] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[1] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10121,"VX_cache genblk5[1] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1625,"VX_cache genblk5[1] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1633,"VX_cache genblk5[1] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1641,"VX_cache genblk5[1] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1649,"VX_cache genblk5[1] bank dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+81,"VX_cache genblk5[1] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58521,"VX_cache genblk5[1] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[1] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[1] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[1] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19721,"VX_cache genblk5[1] bank snp_req_ready", false,-1); - vcdp->declBit(c+2993,"VX_cache genblk5[1] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+3001,"VX_cache genblk5[1] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+25001,"VX_cache genblk5[1] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[1] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[1] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[1] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10137,"VX_cache genblk5[1] bank snp_req_ready", false,-1); + vcdp->declBit(c+1681,"VX_cache genblk5[1] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1689,"VX_cache genblk5[1] bank snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+89,"VX_cache genblk5[1] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+6153,"VX_cache genblk5[1] bank snrq_pop", false,-1); - vcdp->declBit(c+25529,"VX_cache genblk5[1] bank snrq_empty", false,-1); - vcdp->declBit(c+25537,"VX_cache genblk5[1] bank snrq_full", false,-1); - vcdp->declBus(c+6161,"VX_cache genblk5[1] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+6169,"VX_cache genblk5[1] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+6177,"VX_cache genblk5[1] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+6185,"VX_cache genblk5[1] bank dfpq_pop", false,-1); - vcdp->declBit(c+25545,"VX_cache genblk5[1] bank dfpq_empty", false,-1); - vcdp->declBit(c+25553,"VX_cache genblk5[1] bank dfpq_full", false,-1); - vcdp->declBus(c+6193,"VX_cache genblk5[1] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+6201,"VX_cache genblk5[1] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+6233,"VX_cache genblk5[1] bank reqq_pop", false,-1); - vcdp->declBit(c+1889,"VX_cache genblk5[1] bank reqq_push", false,-1); - vcdp->declBit(c+6241,"VX_cache genblk5[1] bank reqq_empty", false,-1); - vcdp->declBit(c+25561,"VX_cache genblk5[1] bank reqq_full", false,-1); - vcdp->declBit(c+6249,"VX_cache genblk5[1] bank reqq_req_st0", false,-1); - vcdp->declBus(c+6257,"VX_cache genblk5[1] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+6265,"VX_cache genblk5[1] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+6273,"VX_cache genblk5[1] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+6281,"VX_cache genblk5[1] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+6289,"VX_cache genblk5[1] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+6297,"VX_cache genblk5[1] bank mrvq_pop", false,-1); - vcdp->declBit(c+25585,"VX_cache genblk5[1] bank mrvq_full", false,-1); - vcdp->declBit(c+25593,"VX_cache genblk5[1] bank mrvq_stop", false,-1); - vcdp->declBit(c+6305,"VX_cache genblk5[1] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+25601,"VX_cache genblk5[1] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+25609,"VX_cache genblk5[1] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+25617,"VX_cache genblk5[1] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+25625,"VX_cache genblk5[1] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+25633,"VX_cache genblk5[1] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+6313,"VX_cache genblk5[1] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+25649,"VX_cache genblk5[1] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+25657,"VX_cache genblk5[1] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+25665,"VX_cache genblk5[1] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+6321,"VX_cache genblk5[1] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+6329,"VX_cache genblk5[1] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+6337,"VX_cache genblk5[1] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+25673,"VX_cache genblk5[1] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+25681,"VX_cache genblk5[1] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+25697,"VX_cache genblk5[1] bank miss_add_rw", false,-1); - vcdp->declBus(c+25705,"VX_cache genblk5[1] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19713,"VX_cache genblk5[1] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+25713,"VX_cache genblk5[1] bank is_fill_st2", false,-1); - vcdp->declBit(c+6345,"VX_cache genblk5[1] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+6353,"VX_cache genblk5[1] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+6361,"VX_cache genblk5[1] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+6369,"VX_cache genblk5[1] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+6377,"VX_cache genblk5[1] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+6385,"VX_cache genblk5[1] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+6393,"VX_cache genblk5[1] bank is_fill_in_pipe", false,-1); + vcdp->declBit(c+4281,"VX_cache genblk5[1] bank snrq_pop", false,-1); + vcdp->declBit(c+14073,"VX_cache genblk5[1] bank snrq_empty", false,-1); + vcdp->declBit(c+14081,"VX_cache genblk5[1] bank snrq_full", false,-1); + vcdp->declBus(c+4289,"VX_cache genblk5[1] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+4297,"VX_cache genblk5[1] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+4305,"VX_cache genblk5[1] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+4313,"VX_cache genblk5[1] bank dfpq_pop", false,-1); + vcdp->declBit(c+14089,"VX_cache genblk5[1] bank dfpq_empty", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[1] bank dfpq_full", false,-1); + vcdp->declBus(c+4321,"VX_cache genblk5[1] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+4329,"VX_cache genblk5[1] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+4361,"VX_cache genblk5[1] bank reqq_pop", false,-1); + vcdp->declBit(c+993,"VX_cache genblk5[1] bank reqq_push", false,-1); + vcdp->declBit(c+4369,"VX_cache genblk5[1] bank reqq_empty", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank reqq_full", false,-1); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank reqq_req_st0", false,-1); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+4393,"VX_cache genblk5[1] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+4401,"VX_cache genblk5[1] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+4409,"VX_cache genblk5[1] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+4417,"VX_cache genblk5[1] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4425,"VX_cache genblk5[1] bank mrvq_pop", false,-1); + vcdp->declBit(c+14129,"VX_cache genblk5[1] bank mrvq_full", false,-1); + vcdp->declBit(c+14137,"VX_cache genblk5[1] bank mrvq_stop", false,-1); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+14145,"VX_cache genblk5[1] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+14153,"VX_cache genblk5[1] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+14161,"VX_cache genblk5[1] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+14169,"VX_cache genblk5[1] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+14177,"VX_cache genblk5[1] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4441,"VX_cache genblk5[1] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+14193,"VX_cache genblk5[1] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+14201,"VX_cache genblk5[1] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+14209,"VX_cache genblk5[1] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+4449,"VX_cache genblk5[1] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+4457,"VX_cache genblk5[1] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+4465,"VX_cache genblk5[1] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+14217,"VX_cache genblk5[1] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+14225,"VX_cache genblk5[1] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+14241,"VX_cache genblk5[1] bank miss_add_rw", false,-1); + vcdp->declBus(c+14249,"VX_cache genblk5[1] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+14257,"VX_cache genblk5[1] bank is_fill_st2", false,-1); + vcdp->declBit(c+4473,"VX_cache genblk5[1] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+4481,"VX_cache genblk5[1] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+4489,"VX_cache genblk5[1] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+4497,"VX_cache genblk5[1] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+4505,"VX_cache genblk5[1] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+4521,"VX_cache genblk5[1] bank is_fill_in_pipe", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+6401+i*1,"VX_cache genblk5[1] bank is_fill_st1", true,(i+0));}} + vcdp->declBit(c+4529+i*1,"VX_cache genblk5[1] bank is_fill_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+6409+i*1,"VX_cache genblk5[1] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[1] bank j", false,-1, 31,0); - vcdp->declBit(c+6305,"VX_cache genblk5[1] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+6417,"VX_cache genblk5[1] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+6425,"VX_cache genblk5[1] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+6433,"VX_cache genblk5[1] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+6417,"VX_cache genblk5[1] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+6441,"VX_cache genblk5[1] bank qual_valid_st0", false,-1); - vcdp->declBus(c+6449,"VX_cache genblk5[1] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+6457,"VX_cache genblk5[1] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+6305,"VX_cache genblk5[1] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+6465,"VX_cache genblk5[1] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+6473,"VX_cache genblk5[1] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+6505,"VX_cache genblk5[1] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+6521,"VX_cache genblk5[1] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+6529,"VX_cache genblk5[1] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+6537,"VX_cache genblk5[1] bank qual_snp_invalidate_st0", false,-1); + vcdp->declBit(c+4537+i*1,"VX_cache genblk5[1] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[1] bank j", false,-1, 31,0); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+4545,"VX_cache genblk5[1] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+4553,"VX_cache genblk5[1] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+4561,"VX_cache genblk5[1] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+4545,"VX_cache genblk5[1] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+4569,"VX_cache genblk5[1] bank qual_valid_st0", false,-1); + vcdp->declBus(c+4577,"VX_cache genblk5[1] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+4585,"VX_cache genblk5[1] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+4593,"VX_cache genblk5[1] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+4601,"VX_cache genblk5[1] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+4633,"VX_cache genblk5[1] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+4649,"VX_cache genblk5[1] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+4657,"VX_cache genblk5[1] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+4665,"VX_cache genblk5[1] bank qual_snp_invalidate_st0", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+6545+i*1,"VX_cache genblk5[1] bank valid_st1", true,(i+0));}} + vcdp->declBit(c+4673+i*1,"VX_cache genblk5[1] bank valid_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+6553+i*1,"VX_cache genblk5[1] bank addr_st1", true,(i+0), 24,0);}} + vcdp->declBus(c+4681+i*1,"VX_cache genblk5[1] bank addr_st1", true,(i+0), 25,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+6561+i*1,"VX_cache genblk5[1] bank wsel_st1", true,(i+0), 1,0);}} + vcdp->declBus(c+4689+i*1,"VX_cache genblk5[1] bank wsel_st1", true,(i+0), 1,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+6569+i*1,"VX_cache genblk5[1] bank writeword_st1", true,(i+0), 31,0);}} + vcdp->declBus(c+4697+i*1,"VX_cache genblk5[1] bank writeword_st1", true,(i+0), 31,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+6577+i*2,"VX_cache genblk5[1] bank inst_meta_st1", true,(i+0), 48,0);}} + vcdp->declQuad(c+4705+i*2,"VX_cache genblk5[1] bank inst_meta_st1", true,(i+0), 48,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+6593+i*4,"VX_cache genblk5[1] bank writedata_st1", true,(i+0), 127,0);}} + vcdp->declArray(c+4721+i*4,"VX_cache genblk5[1] bank writedata_st1", true,(i+0), 127,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+6625+i*1,"VX_cache genblk5[1] bank is_snp_st1", true,(i+0));}} + vcdp->declBit(c+4753+i*1,"VX_cache genblk5[1] bank is_snp_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+6633+i*1,"VX_cache genblk5[1] bank snp_invalidate_st1", true,(i+0));}} + vcdp->declBit(c+4761+i*1,"VX_cache genblk5[1] bank snp_invalidate_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+6641+i*1,"VX_cache genblk5[1] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+6649,"VX_cache genblk5[1] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+6657,"VX_cache genblk5[1] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+6689,"VX_cache genblk5[1] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+6697,"VX_cache genblk5[1] bank miss_st1e", false,-1); - vcdp->declBit(c+6705,"VX_cache genblk5[1] bank dirty_st1e", false,-1); - vcdp->declBus(c+6713,"VX_cache genblk5[1] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+6721,"VX_cache genblk5[1] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+6737,"VX_cache genblk5[1] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+6745,"VX_cache genblk5[1] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+6753,"VX_cache genblk5[1] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+6761,"VX_cache genblk5[1] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+6769,"VX_cache genblk5[1] bank is_snp_st1e", false,-1); - vcdp->declBit(c+6777,"VX_cache genblk5[1] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+6785,"VX_cache genblk5[1] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+6793,"VX_cache genblk5[1] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+6801,"VX_cache genblk5[1] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+6809,"VX_cache genblk5[1] bank valid_st1e", false,-1); - vcdp->declBit(c+6817,"VX_cache genblk5[1] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+6825,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+6833,"VX_cache genblk5[1] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+6841,"VX_cache genblk5[1] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+6817,"VX_cache genblk5[1] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+25721,"VX_cache genblk5[1] bank valid_st2", false,-1); - vcdp->declBus(c+25729,"VX_cache genblk5[1] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+25737,"VX_cache genblk5[1] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+25745,"VX_cache genblk5[1] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+25753,"VX_cache genblk5[1] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+25785,"VX_cache genblk5[1] bank miss_st2", false,-1); - vcdp->declBit(c+25793,"VX_cache genblk5[1] bank dirty_st2", false,-1); - vcdp->declBus(c+25801,"VX_cache genblk5[1] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+25809,"VX_cache genblk5[1] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+25825,"VX_cache genblk5[1] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+25833,"VX_cache genblk5[1] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+25841,"VX_cache genblk5[1] bank is_snp_st2", false,-1); - vcdp->declBit(c+25849,"VX_cache genblk5[1] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+25857,"VX_cache genblk5[1] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+25865,"VX_cache genblk5[1] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+6849,"VX_cache genblk5[1] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+25873,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+25881,"VX_cache genblk5[1] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+6857,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+6865,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+25857,"VX_cache genblk5[1] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+6873,"VX_cache genblk5[1] bank miss_add_unqual", false,-1); - vcdp->declBit(c+6881,"VX_cache genblk5[1] bank miss_add", false,-1); - vcdp->declBus(c+19713,"VX_cache genblk5[1] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+25729,"VX_cache genblk5[1] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+25737,"VX_cache genblk5[1] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+25841,"VX_cache genblk5[1] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+25849,"VX_cache genblk5[1] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+6889,"VX_cache genblk5[1] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+6897,"VX_cache genblk5[1] bank cwbq_push", false,-1); - vcdp->declBit(c+1897,"VX_cache genblk5[1] bank cwbq_pop", false,-1); - vcdp->declBit(c+25889,"VX_cache genblk5[1] bank cwbq_empty", false,-1); - vcdp->declBit(c+25897,"VX_cache genblk5[1] bank cwbq_full", false,-1); - vcdp->declBit(c+6905,"VX_cache genblk5[1] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+25745,"VX_cache genblk5[1] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+25673,"VX_cache genblk5[1] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+25681,"VX_cache genblk5[1] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+6873,"VX_cache genblk5[1] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+6913,"VX_cache genblk5[1] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+6921,"VX_cache genblk5[1] bank dwbq_push", false,-1); - vcdp->declBit(c+1905,"VX_cache genblk5[1] bank dwbq_pop", false,-1); - vcdp->declBit(c+25905,"VX_cache genblk5[1] bank dwbq_empty", false,-1); - vcdp->declBit(c+25913,"VX_cache genblk5[1] bank dwbq_full", false,-1); - vcdp->declBit(c+6929,"VX_cache genblk5[1] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+6937,"VX_cache genblk5[1] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+6945,"VX_cache genblk5[1] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+6953,"VX_cache genblk5[1] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+6961,"VX_cache genblk5[1] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+25921,"VX_cache genblk5[1] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+25929,"VX_cache genblk5[1] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+505,"VX_cache genblk5[1] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+513,"VX_cache genblk5[1] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+25937,"VX_cache genblk5[1] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[1] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58521,"VX_cache genblk5[1] bank snp_req_queue push", false,-1); - vcdp->declBit(c+6153,"VX_cache genblk5[1] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+521,"VX_cache genblk5[1] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+6969,"VX_cache genblk5[1] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+25529,"VX_cache genblk5[1] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+25537,"VX_cache genblk5[1] bank snp_req_queue full", false,-1); - vcdp->declBus(c+25945,"VX_cache genblk5[1] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+25945,"VX_cache genblk5[1] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+6985,"VX_cache genblk5[1] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+537,"VX_cache genblk5[1] bank snp_req_queue writing", false,-1); + vcdp->declBit(c+4769+i*1,"VX_cache genblk5[1] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+4777,"VX_cache genblk5[1] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+4785,"VX_cache genblk5[1] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+4817,"VX_cache genblk5[1] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank miss_st1e", false,-1); + vcdp->declBit(c+4833,"VX_cache genblk5[1] bank dirty_st1e", false,-1); + vcdp->declBus(c+4841,"VX_cache genblk5[1] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+4849,"VX_cache genblk5[1] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+4865,"VX_cache genblk5[1] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+4873,"VX_cache genblk5[1] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+4881,"VX_cache genblk5[1] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+4889,"VX_cache genblk5[1] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+4897,"VX_cache genblk5[1] bank is_snp_st1e", false,-1); + vcdp->declBit(c+4905,"VX_cache genblk5[1] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+4913,"VX_cache genblk5[1] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+4921,"VX_cache genblk5[1] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+4929,"VX_cache genblk5[1] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+4937,"VX_cache genblk5[1] bank valid_st1e", false,-1); + vcdp->declBit(c+4945,"VX_cache genblk5[1] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+4953,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+4961,"VX_cache genblk5[1] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+4969,"VX_cache genblk5[1] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+4945,"VX_cache genblk5[1] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+14265,"VX_cache genblk5[1] bank valid_st2", false,-1); + vcdp->declBus(c+14273,"VX_cache genblk5[1] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+14281,"VX_cache genblk5[1] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+14289,"VX_cache genblk5[1] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+14297,"VX_cache genblk5[1] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+14329,"VX_cache genblk5[1] bank miss_st2", false,-1); + vcdp->declBit(c+14337,"VX_cache genblk5[1] bank dirty_st2", false,-1); + vcdp->declBus(c+14345,"VX_cache genblk5[1] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+14353,"VX_cache genblk5[1] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+14369,"VX_cache genblk5[1] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+14377,"VX_cache genblk5[1] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+14385,"VX_cache genblk5[1] bank is_snp_st2", false,-1); + vcdp->declBit(c+14393,"VX_cache genblk5[1] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+14401,"VX_cache genblk5[1] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+14409,"VX_cache genblk5[1] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+4977,"VX_cache genblk5[1] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+14417,"VX_cache genblk5[1] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+14425,"VX_cache genblk5[1] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+4985,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+4993,"VX_cache genblk5[1] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+14401,"VX_cache genblk5[1] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+5001,"VX_cache genblk5[1] bank miss_add_unqual", false,-1); + vcdp->declBit(c+5009,"VX_cache genblk5[1] bank miss_add", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+14273,"VX_cache genblk5[1] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+14281,"VX_cache genblk5[1] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+14385,"VX_cache genblk5[1] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+14393,"VX_cache genblk5[1] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+5017,"VX_cache genblk5[1] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+5025,"VX_cache genblk5[1] bank cwbq_push", false,-1); + vcdp->declBit(c+1001,"VX_cache genblk5[1] bank cwbq_pop", false,-1); + vcdp->declBit(c+14433,"VX_cache genblk5[1] bank cwbq_empty", false,-1); + vcdp->declBit(c+14441,"VX_cache genblk5[1] bank cwbq_full", false,-1); + vcdp->declBit(c+5033,"VX_cache genblk5[1] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+14289,"VX_cache genblk5[1] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+14217,"VX_cache genblk5[1] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+14225,"VX_cache genblk5[1] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+5001,"VX_cache genblk5[1] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+5041,"VX_cache genblk5[1] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+5049,"VX_cache genblk5[1] bank dwbq_push", false,-1); + vcdp->declBit(c+1009,"VX_cache genblk5[1] bank dwbq_pop", false,-1); + vcdp->declBit(c+14449,"VX_cache genblk5[1] bank dwbq_empty", false,-1); + vcdp->declBit(c+14457,"VX_cache genblk5[1] bank dwbq_full", false,-1); + vcdp->declBit(c+5057,"VX_cache genblk5[1] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+5065,"VX_cache genblk5[1] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+5073,"VX_cache genblk5[1] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+5081,"VX_cache genblk5[1] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+5089,"VX_cache genblk5[1] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+14465,"VX_cache genblk5[1] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+14473,"VX_cache genblk5[1] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+377,"VX_cache genblk5[1] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+385,"VX_cache genblk5[1] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+14481,"VX_cache genblk5[1] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[1] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+25001,"VX_cache genblk5[1] bank snp_req_queue push", false,-1); + vcdp->declBit(c+4281,"VX_cache genblk5[1] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+393,"VX_cache genblk5[1] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+5097,"VX_cache genblk5[1] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+14073,"VX_cache genblk5[1] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+14081,"VX_cache genblk5[1] bank snp_req_queue full", false,-1); + vcdp->declBus(c+14489,"VX_cache genblk5[1] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+14489,"VX_cache genblk5[1] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+5113,"VX_cache genblk5[1] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+409,"VX_cache genblk5[1] bank snp_req_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+25953+i*2,"VX_cache genblk5[1] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+26209,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+26225,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+26241,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+26249,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+26257,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+25529,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+25537,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+26265,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[1] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58513,"VX_cache genblk5[1] bank dfp_queue push", false,-1); - vcdp->declBit(c+6185,"VX_cache genblk5[1] bank dfp_queue pop", false,-1); - vcdp->declArray(c+545,"VX_cache genblk5[1] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+6993,"VX_cache genblk5[1] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+25545,"VX_cache genblk5[1] bank dfp_queue empty", false,-1); - vcdp->declBit(c+25553,"VX_cache genblk5[1] bank dfp_queue full", false,-1); - vcdp->declBus(c+26273,"VX_cache genblk5[1] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+26273,"VX_cache genblk5[1] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+7033,"VX_cache genblk5[1] bank dfp_queue reading", false,-1); - vcdp->declBit(c+585,"VX_cache genblk5[1] bank dfp_queue writing", false,-1); + vcdp->declQuad(c+14497+i*2,"VX_cache genblk5[1] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+14753,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+14769,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+14785,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+14793,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+14801,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+14073,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14081,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+14809,"VX_cache genblk5[1] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[1] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank dfp_queue reset", false,-1); + vcdp->declBit(c+24993,"VX_cache genblk5[1] bank dfp_queue push", false,-1); + vcdp->declBit(c+4313,"VX_cache genblk5[1] bank dfp_queue pop", false,-1); + vcdp->declArray(c+417,"VX_cache genblk5[1] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+5121,"VX_cache genblk5[1] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+14089,"VX_cache genblk5[1] bank dfp_queue empty", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[1] bank dfp_queue full", false,-1); + vcdp->declBus(c+14817,"VX_cache genblk5[1] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+14817,"VX_cache genblk5[1] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+5161,"VX_cache genblk5[1] bank dfp_queue reading", false,-1); + vcdp->declBit(c+457,"VX_cache genblk5[1] bank dfp_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+26281+i*5,"VX_cache genblk5[1] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+26921,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+26961,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+27001,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+27009,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+27017,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+25545,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+25553,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+27025,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank core_req_arb reset", false,-1); - vcdp->declBit(c+1889,"VX_cache genblk5[1] bank core_req_arb reqq_push", false,-1); + vcdp->declArray(c+14825+i*5,"VX_cache genblk5[1] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+15465,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+15505,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+15545,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+15553,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+15561,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+14089,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14097,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+15569,"VX_cache genblk5[1] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[1] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank core_req_arb reset", false,-1); + vcdp->declBit(c+993,"VX_cache genblk5[1] bank core_req_arb reqq_push", false,-1); vcdp->declBus(c+65,"VX_cache genblk5[1] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[1] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[1] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[1] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[1] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[1] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+6233,"VX_cache genblk5[1] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+6265,"VX_cache genblk5[1] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+6273,"VX_cache genblk5[1] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+6281,"VX_cache genblk5[1] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+6289,"VX_cache genblk5[1] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+6241,"VX_cache genblk5[1] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+25561,"VX_cache genblk5[1] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+7041,"VX_cache genblk5[1] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+7049,"VX_cache genblk5[1] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+7057,"VX_cache genblk5[1] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+7065,"VX_cache genblk5[1] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+7097,"VX_cache genblk5[1] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+7129,"VX_cache genblk5[1] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+27041,"VX_cache genblk5[1] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+27049,"VX_cache genblk5[1] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+27057,"VX_cache genblk5[1] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+27089,"VX_cache genblk5[1] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+27041,"VX_cache genblk5[1] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+27049,"VX_cache genblk5[1] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+27057,"VX_cache genblk5[1] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+27089,"VX_cache genblk5[1] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+25569,"VX_cache genblk5[1] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+27121,"VX_cache genblk5[1] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+27129,"VX_cache genblk5[1] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+7145,"VX_cache genblk5[1] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+1913,"VX_cache genblk5[1] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+7153,"VX_cache genblk5[1] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+7161,"VX_cache genblk5[1] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[1] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+1913,"VX_cache genblk5[1] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+7153,"VX_cache genblk5[1] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+593,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+7169,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+27121,"VX_cache genblk5[1] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+25561,"VX_cache genblk5[1] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+27137,"VX_cache genblk5[1] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+27137,"VX_cache genblk5[1] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+7249,"VX_cache genblk5[1] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+673,"VX_cache genblk5[1] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+27145+i*10,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+27785,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+27865,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+27945,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+27953,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+27961,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+27121,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+25561,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+27969,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+7257,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+7257,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+27033,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+6257,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+6249,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+7265,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[1] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[1] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+6385,"VX_cache genblk5[1] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[1] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+7273,"VX_cache genblk5[1] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+27977,"VX_cache genblk5[1] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+27977,"VX_cache genblk5[1] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[1] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank tag_data_access reset", false,-1); - vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access stall", false,-1); - vcdp->declBit(c+6769,"VX_cache genblk5[1] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+6777,"VX_cache genblk5[1] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+6337,"VX_cache genblk5[1] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+6833,"VX_cache genblk5[1] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+6809,"VX_cache genblk5[1] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+7345,"VX_cache genblk5[1] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+7353,"VX_cache genblk5[1] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+7361,"VX_cache genblk5[1] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+6745,"VX_cache genblk5[1] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+6753,"VX_cache genblk5[1] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+7393,"VX_cache genblk5[1] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+6649,"VX_cache genblk5[1] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+6657,"VX_cache genblk5[1] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+6689,"VX_cache genblk5[1] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+6697,"VX_cache genblk5[1] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+6705,"VX_cache genblk5[1] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+6713,"VX_cache genblk5[1] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+6761,"VX_cache genblk5[1] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+6785,"VX_cache genblk5[1] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+6793,"VX_cache genblk5[1] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+7401+i*1,"VX_cache genblk5[1] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+7409+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+7417+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+7425+i*1,"VX_cache genblk5[1] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+7433+i*4,"VX_cache genblk5[1] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+7465,"VX_cache genblk5[1] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+7473,"VX_cache genblk5[1] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+7481,"VX_cache genblk5[1] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+7489,"VX_cache genblk5[1] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+7497,"VX_cache genblk5[1] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+7529,"VX_cache genblk5[1] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+7537,"VX_cache genblk5[1] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+6713,"VX_cache genblk5[1] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+6689,"VX_cache genblk5[1] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+6657,"VX_cache genblk5[1] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+7545,"VX_cache genblk5[1] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+7553,"VX_cache genblk5[1] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+6697,"VX_cache genblk5[1] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+7585,"VX_cache genblk5[1] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+7593,"VX_cache genblk5[1] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+7601,"VX_cache genblk5[1] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+7609,"VX_cache genblk5[1] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+7617,"VX_cache genblk5[1] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+7553,"VX_cache genblk5[1] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+7625,"VX_cache genblk5[1] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+7585,"VX_cache genblk5[1] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+7633,"VX_cache genblk5[1] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+7641,"VX_cache genblk5[1] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+7649,"VX_cache genblk5[1] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+7657,"VX_cache genblk5[1] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+7665,"VX_cache genblk5[1] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+7673,"VX_cache genblk5[1] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+7681,"VX_cache genblk5[1] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+7689,"VX_cache genblk5[1] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[1] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+7465,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+7473,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+7481,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+7489,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+7497,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+7585,"VX_cache genblk5[1] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+7545,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+7601,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+7337,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+7609,"VX_cache genblk5[1] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+7553,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+6697,"VX_cache genblk5[1] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+28041,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+28073,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+28105,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+28137,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+28169,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+28201,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+28233,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+28265,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+28297,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+28329,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+28361,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+28393,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+28425,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+28457,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+28489,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+28521,"VX_cache genblk5[1] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+28553+i*1,"VX_cache genblk5[1] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+28681,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+28689,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+28697,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+28705,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+28713,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+28721,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+28729,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+28737,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+28745,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+28753,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+28761,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+28769,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+28777,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+28785,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+28793,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+28801,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+28809,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+28817,"VX_cache genblk5[1] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+7697,"VX_cache genblk5[1] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+28825,"VX_cache genblk5[1] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+28833,"VX_cache genblk5[1] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+6385,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+7705,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+7705,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+28841,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[1] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[1] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+6385,"VX_cache genblk5[1] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[1] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+7753,"VX_cache genblk5[1] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+28889,"VX_cache genblk5[1] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+28889,"VX_cache genblk5[1] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[1] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58753,"VX_cache genblk5[1] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[1] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[1] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[1] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+6881,"VX_cache genblk5[1] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+6889,"VX_cache genblk5[1] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19713,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+25729,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+25737,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+25673,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+25681,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+25697,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+25705,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+6849,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+25841,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+25849,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+25585,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+25593,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+7345,"VX_cache genblk5[1] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+6833,"VX_cache genblk5[1] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+6321,"VX_cache genblk5[1] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+6297,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+6305,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+25609,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+25617,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+25625,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+25601,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+25633,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+6313,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+25649,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+25657,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+25665,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+28969+i*3,"VX_cache genblk5[1] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+29353,"VX_cache genblk5[1] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+29457,"VX_cache genblk5[1] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+29465,"VX_cache genblk5[1] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+29473,"VX_cache genblk5[1] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+29481,"VX_cache genblk5[1] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+29489,"VX_cache genblk5[1] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+29497,"VX_cache genblk5[1] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+29505,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+29489,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+7833,"VX_cache genblk5[1] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+7841,"VX_cache genblk5[1] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+7849,"VX_cache genblk5[1] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+6305,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+29473,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+7857,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+7865,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+7873,"VX_cache genblk5[1] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+7881,"VX_cache genblk5[1] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+7889,"VX_cache genblk5[1] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+7897,"VX_cache genblk5[1] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[1] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[1] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank cwb_queue reset", false,-1); - vcdp->declBit(c+6897,"VX_cache genblk5[1] bank cwb_queue push", false,-1); - vcdp->declBit(c+1897,"VX_cache genblk5[1] bank cwb_queue pop", false,-1); - vcdp->declArray(c+7905,"VX_cache genblk5[1] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+7929,"VX_cache genblk5[1] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+25889,"VX_cache genblk5[1] bank cwb_queue empty", false,-1); - vcdp->declBit(c+25897,"VX_cache genblk5[1] bank cwb_queue full", false,-1); - vcdp->declBus(c+29513,"VX_cache genblk5[1] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+29513,"VX_cache genblk5[1] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+681,"VX_cache genblk5[1] bank cwb_queue reading", false,-1); - vcdp->declBit(c+7953,"VX_cache genblk5[1] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+29521+i*3,"VX_cache genblk5[1] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+29713,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+29737,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+29761,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+29769,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+29777,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+25889,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+25897,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+29785,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[1] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[1] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[1] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[1] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[1] bank dwb_queue reset", false,-1); - vcdp->declBit(c+6921,"VX_cache genblk5[1] bank dwb_queue push", false,-1); - vcdp->declBit(c+1905,"VX_cache genblk5[1] bank dwb_queue pop", false,-1); - vcdp->declArray(c+7961,"VX_cache genblk5[1] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+8017,"VX_cache genblk5[1] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+25905,"VX_cache genblk5[1] bank dwb_queue empty", false,-1); - vcdp->declBit(c+25913,"VX_cache genblk5[1] bank dwb_queue full", false,-1); - vcdp->declBus(c+29793,"VX_cache genblk5[1] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+29793,"VX_cache genblk5[1] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+689,"VX_cache genblk5[1] bank dwb_queue reading", false,-1); - vcdp->declBit(c+8073,"VX_cache genblk5[1] bank dwb_queue writing", false,-1); + vcdp->declBus(c+24513,"VX_cache genblk5[1] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[1] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[1] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[1] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[1] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+4361,"VX_cache genblk5[1] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+4393,"VX_cache genblk5[1] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+4401,"VX_cache genblk5[1] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+4409,"VX_cache genblk5[1] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+4417,"VX_cache genblk5[1] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4369,"VX_cache genblk5[1] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+5169,"VX_cache genblk5[1] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+5177,"VX_cache genblk5[1] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+5185,"VX_cache genblk5[1] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+5193,"VX_cache genblk5[1] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+5225,"VX_cache genblk5[1] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+5257,"VX_cache genblk5[1] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+15585,"VX_cache genblk5[1] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+15593,"VX_cache genblk5[1] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+15601,"VX_cache genblk5[1] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+15633,"VX_cache genblk5[1] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+15585,"VX_cache genblk5[1] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+15593,"VX_cache genblk5[1] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+15601,"VX_cache genblk5[1] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+15633,"VX_cache genblk5[1] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+14113,"VX_cache genblk5[1] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+15665,"VX_cache genblk5[1] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+15673,"VX_cache genblk5[1] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+5273,"VX_cache genblk5[1] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1017,"VX_cache genblk5[1] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+5281,"VX_cache genblk5[1] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+5289,"VX_cache genblk5[1] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[1] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1017,"VX_cache genblk5[1] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+5281,"VX_cache genblk5[1] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+465,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+5297,"VX_cache genblk5[1] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+15665,"VX_cache genblk5[1] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+15681,"VX_cache genblk5[1] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+15681,"VX_cache genblk5[1] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+5377,"VX_cache genblk5[1] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+545,"VX_cache genblk5[1] bank core_req_arb reqq_queue writing", false,-1); {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+29801+i*7,"VX_cache genblk5[1] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+30025,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+30081,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+30137,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+30145,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+30153,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+25905,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+25913,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+30161,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58641,"VX_cache genblk5[2] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58825,"VX_cache genblk5[2] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[2] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[2] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[2] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[2] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank reset", false,-1); + vcdp->declArray(c+15689+i*10,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+16009,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+16089,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+16169,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+16177,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+16185,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+15665,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14105,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+16193,"VX_cache genblk5[1] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+5385,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+5385,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+15577,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+4385,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+4377,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+5393,"VX_cache genblk5[1] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[1] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[1] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+5401,"VX_cache genblk5[1] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+16201,"VX_cache genblk5[1] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+16201,"VX_cache genblk5[1] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[1] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank tag_data_access reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access stall", false,-1); + vcdp->declBit(c+4897,"VX_cache genblk5[1] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+4905,"VX_cache genblk5[1] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+4465,"VX_cache genblk5[1] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+4961,"VX_cache genblk5[1] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+4937,"VX_cache genblk5[1] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+5473,"VX_cache genblk5[1] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+5481,"VX_cache genblk5[1] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+5489,"VX_cache genblk5[1] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+4873,"VX_cache genblk5[1] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+4881,"VX_cache genblk5[1] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+5521,"VX_cache genblk5[1] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+4777,"VX_cache genblk5[1] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+4785,"VX_cache genblk5[1] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+4817,"VX_cache genblk5[1] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+4833,"VX_cache genblk5[1] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+4841,"VX_cache genblk5[1] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+4889,"VX_cache genblk5[1] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+4913,"VX_cache genblk5[1] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+4921,"VX_cache genblk5[1] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+5529+i*1,"VX_cache genblk5[1] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+5537+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+5545+i*1,"VX_cache genblk5[1] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+5553+i*1,"VX_cache genblk5[1] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+5561+i*4,"VX_cache genblk5[1] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+5593,"VX_cache genblk5[1] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+5601,"VX_cache genblk5[1] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+5609,"VX_cache genblk5[1] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+5617,"VX_cache genblk5[1] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+5625,"VX_cache genblk5[1] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+5657,"VX_cache genblk5[1] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+5665,"VX_cache genblk5[1] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+4841,"VX_cache genblk5[1] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+4817,"VX_cache genblk5[1] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+4785,"VX_cache genblk5[1] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+5673,"VX_cache genblk5[1] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+5681,"VX_cache genblk5[1] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+5713,"VX_cache genblk5[1] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+5721,"VX_cache genblk5[1] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+5729,"VX_cache genblk5[1] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+5737,"VX_cache genblk5[1] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+5745,"VX_cache genblk5[1] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+5681,"VX_cache genblk5[1] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+5753,"VX_cache genblk5[1] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+5713,"VX_cache genblk5[1] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+5761,"VX_cache genblk5[1] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+5769,"VX_cache genblk5[1] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+5777,"VX_cache genblk5[1] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+5785,"VX_cache genblk5[1] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+5793,"VX_cache genblk5[1] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+5801,"VX_cache genblk5[1] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+5809,"VX_cache genblk5[1] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+5817,"VX_cache genblk5[1] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[1] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+5593,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+5601,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+5609,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+5617,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+5625,"VX_cache genblk5[1] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+5713,"VX_cache genblk5[1] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+5673,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+5729,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+5465,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+5737,"VX_cache genblk5[1] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+5681,"VX_cache genblk5[1] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+4825,"VX_cache genblk5[1] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+16265,"VX_cache genblk5[1] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+16281,"VX_cache genblk5[1] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+5825,"VX_cache genblk5[1] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+16297,"VX_cache genblk5[1] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+16305,"VX_cache genblk5[1] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+5833,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+5833,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+16313,"VX_cache genblk5[1] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[1] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+4513,"VX_cache genblk5[1] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[1] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+5881,"VX_cache genblk5[1] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+16361,"VX_cache genblk5[1] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+16361,"VX_cache genblk5[1] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[1] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25161,"VX_cache genblk5[1] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[1] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[1] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[1] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+5009,"VX_cache genblk5[1] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+5017,"VX_cache genblk5[1] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10129,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+14273,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+14281,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+14217,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+14225,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+14241,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+14249,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+4977,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+14385,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+14393,"VX_cache genblk5[1] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+14129,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+14137,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+5473,"VX_cache genblk5[1] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+4961,"VX_cache genblk5[1] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+4449,"VX_cache genblk5[1] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+4425,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+14153,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+14161,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+14169,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+14145,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+14177,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+4441,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+14193,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+14201,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+14209,"VX_cache genblk5[1] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+16441+i*3,"VX_cache genblk5[1] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+16825,"VX_cache genblk5[1] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+16929,"VX_cache genblk5[1] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+16937,"VX_cache genblk5[1] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+16945,"VX_cache genblk5[1] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+16953,"VX_cache genblk5[1] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+16961,"VX_cache genblk5[1] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+16969,"VX_cache genblk5[1] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+16977,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+16961,"VX_cache genblk5[1] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+5961,"VX_cache genblk5[1] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+5969,"VX_cache genblk5[1] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+5977,"VX_cache genblk5[1] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+4433,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+16945,"VX_cache genblk5[1] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+5985,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+5993,"VX_cache genblk5[1] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+6001,"VX_cache genblk5[1] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+6009,"VX_cache genblk5[1] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+6017,"VX_cache genblk5[1] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+6025,"VX_cache genblk5[1] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[1] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank cwb_queue reset", false,-1); + vcdp->declBit(c+5025,"VX_cache genblk5[1] bank cwb_queue push", false,-1); + vcdp->declBit(c+1001,"VX_cache genblk5[1] bank cwb_queue pop", false,-1); + vcdp->declArray(c+6033,"VX_cache genblk5[1] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+6057,"VX_cache genblk5[1] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+14433,"VX_cache genblk5[1] bank cwb_queue empty", false,-1); + vcdp->declBit(c+14441,"VX_cache genblk5[1] bank cwb_queue full", false,-1); + vcdp->declBus(c+16985,"VX_cache genblk5[1] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+16985,"VX_cache genblk5[1] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+553,"VX_cache genblk5[1] bank cwb_queue reading", false,-1); + vcdp->declBit(c+6081,"VX_cache genblk5[1] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+16993+i*3,"VX_cache genblk5[1] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+17089,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+17113,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+17137,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17145,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17153,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+14433,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14441,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+17161,"VX_cache genblk5[1] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[1] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[1] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[1] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[1] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[1] bank dwb_queue reset", false,-1); + vcdp->declBit(c+5049,"VX_cache genblk5[1] bank dwb_queue push", false,-1); + vcdp->declBit(c+1009,"VX_cache genblk5[1] bank dwb_queue pop", false,-1); + vcdp->declArray(c+6089,"VX_cache genblk5[1] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+6145,"VX_cache genblk5[1] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+14449,"VX_cache genblk5[1] bank dwb_queue empty", false,-1); + vcdp->declBit(c+14457,"VX_cache genblk5[1] bank dwb_queue full", false,-1); + vcdp->declBus(c+17169,"VX_cache genblk5[1] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+17169,"VX_cache genblk5[1] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+561,"VX_cache genblk5[1] bank dwb_queue reading", false,-1); + vcdp->declBit(c+6201,"VX_cache genblk5[1] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+17177+i*7,"VX_cache genblk5[1] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+17401,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+17457,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+17513,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17521,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+17529,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+14449,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+14457,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+17537,"VX_cache genblk5[1] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25233,"VX_cache genblk5[2] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[2] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[2] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[2] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[2] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank reset", false,-1); vcdp->declBus(c+97,"VX_cache genblk5[2] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[2] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[2] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[2] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[2] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[2] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19769,"VX_cache genblk5[2] bank core_req_ready", false,-1); - vcdp->declBit(c+19737,"VX_cache genblk5[2] bank core_rsp_valid", false,-1); - vcdp->declBus(c+3009,"VX_cache genblk5[2] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3017,"VX_cache genblk5[2] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3025,"VX_cache genblk5[2] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[2] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[2] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[2] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[2] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[2] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10185,"VX_cache genblk5[2] bank core_req_ready", false,-1); + vcdp->declBit(c+10153,"VX_cache genblk5[2] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1697,"VX_cache genblk5[2] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1705,"VX_cache genblk5[2] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1713,"VX_cache genblk5[2] bank core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+105,"VX_cache genblk5[2] bank core_rsp_ready", false,-1); - vcdp->declBit(c+3041,"VX_cache genblk5[2] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19753,"VX_cache genblk5[2] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[2] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58529,"VX_cache genblk5[2] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[2] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[2] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19745,"VX_cache genblk5[2] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3049,"VX_cache genblk5[2] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+3057,"VX_cache genblk5[2] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3065,"VX_cache genblk5[2] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3073,"VX_cache genblk5[2] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+1729,"VX_cache genblk5[2] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[2] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+25009,"VX_cache genblk5[2] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[2] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[2] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10161,"VX_cache genblk5[2] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1737,"VX_cache genblk5[2] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1745,"VX_cache genblk5[2] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1753,"VX_cache genblk5[2] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1761,"VX_cache genblk5[2] bank dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+113,"VX_cache genblk5[2] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58537,"VX_cache genblk5[2] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[2] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[2] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[2] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19761,"VX_cache genblk5[2] bank snp_req_ready", false,-1); - vcdp->declBit(c+3105,"VX_cache genblk5[2] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+3113,"VX_cache genblk5[2] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+25017,"VX_cache genblk5[2] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[2] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[2] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[2] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10177,"VX_cache genblk5[2] bank snp_req_ready", false,-1); + vcdp->declBit(c+1793,"VX_cache genblk5[2] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1801,"VX_cache genblk5[2] bank snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+121,"VX_cache genblk5[2] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+8081,"VX_cache genblk5[2] bank snrq_pop", false,-1); - vcdp->declBit(c+30169,"VX_cache genblk5[2] bank snrq_empty", false,-1); - vcdp->declBit(c+30177,"VX_cache genblk5[2] bank snrq_full", false,-1); - vcdp->declBus(c+8089,"VX_cache genblk5[2] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+8097,"VX_cache genblk5[2] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+8105,"VX_cache genblk5[2] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+8113,"VX_cache genblk5[2] bank dfpq_pop", false,-1); - vcdp->declBit(c+30185,"VX_cache genblk5[2] bank dfpq_empty", false,-1); - vcdp->declBit(c+30193,"VX_cache genblk5[2] bank dfpq_full", false,-1); - vcdp->declBus(c+8121,"VX_cache genblk5[2] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+8129,"VX_cache genblk5[2] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+8161,"VX_cache genblk5[2] bank reqq_pop", false,-1); - vcdp->declBit(c+1921,"VX_cache genblk5[2] bank reqq_push", false,-1); - vcdp->declBit(c+8169,"VX_cache genblk5[2] bank reqq_empty", false,-1); - vcdp->declBit(c+30201,"VX_cache genblk5[2] bank reqq_full", false,-1); - vcdp->declBit(c+8177,"VX_cache genblk5[2] bank reqq_req_st0", false,-1); - vcdp->declBus(c+8185,"VX_cache genblk5[2] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+8193,"VX_cache genblk5[2] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+8201,"VX_cache genblk5[2] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+8209,"VX_cache genblk5[2] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+8217,"VX_cache genblk5[2] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+8225,"VX_cache genblk5[2] bank mrvq_pop", false,-1); - vcdp->declBit(c+30225,"VX_cache genblk5[2] bank mrvq_full", false,-1); - vcdp->declBit(c+30233,"VX_cache genblk5[2] bank mrvq_stop", false,-1); - vcdp->declBit(c+8233,"VX_cache genblk5[2] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+30241,"VX_cache genblk5[2] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+30249,"VX_cache genblk5[2] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+30257,"VX_cache genblk5[2] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+30265,"VX_cache genblk5[2] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+30273,"VX_cache genblk5[2] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+8241,"VX_cache genblk5[2] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+30289,"VX_cache genblk5[2] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+30297,"VX_cache genblk5[2] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+30305,"VX_cache genblk5[2] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+8249,"VX_cache genblk5[2] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+8257,"VX_cache genblk5[2] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+8265,"VX_cache genblk5[2] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+30313,"VX_cache genblk5[2] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+30321,"VX_cache genblk5[2] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+30337,"VX_cache genblk5[2] bank miss_add_rw", false,-1); - vcdp->declBus(c+30345,"VX_cache genblk5[2] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19753,"VX_cache genblk5[2] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+30353,"VX_cache genblk5[2] bank is_fill_st2", false,-1); - vcdp->declBit(c+8273,"VX_cache genblk5[2] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+8281,"VX_cache genblk5[2] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+8289,"VX_cache genblk5[2] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+8297,"VX_cache genblk5[2] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+8305,"VX_cache genblk5[2] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+8313,"VX_cache genblk5[2] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+8321,"VX_cache genblk5[2] bank is_fill_in_pipe", false,-1); + vcdp->declBit(c+6209,"VX_cache genblk5[2] bank snrq_pop", false,-1); + vcdp->declBit(c+17545,"VX_cache genblk5[2] bank snrq_empty", false,-1); + vcdp->declBit(c+17553,"VX_cache genblk5[2] bank snrq_full", false,-1); + vcdp->declBus(c+6217,"VX_cache genblk5[2] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+6225,"VX_cache genblk5[2] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+6233,"VX_cache genblk5[2] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+6241,"VX_cache genblk5[2] bank dfpq_pop", false,-1); + vcdp->declBit(c+17561,"VX_cache genblk5[2] bank dfpq_empty", false,-1); + vcdp->declBit(c+17569,"VX_cache genblk5[2] bank dfpq_full", false,-1); + vcdp->declBus(c+6249,"VX_cache genblk5[2] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+6257,"VX_cache genblk5[2] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+6289,"VX_cache genblk5[2] bank reqq_pop", false,-1); + vcdp->declBit(c+1025,"VX_cache genblk5[2] bank reqq_push", false,-1); + vcdp->declBit(c+6297,"VX_cache genblk5[2] bank reqq_empty", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank reqq_full", false,-1); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank reqq_req_st0", false,-1); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+6321,"VX_cache genblk5[2] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+6329,"VX_cache genblk5[2] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+6337,"VX_cache genblk5[2] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+6345,"VX_cache genblk5[2] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6353,"VX_cache genblk5[2] bank mrvq_pop", false,-1); + vcdp->declBit(c+17601,"VX_cache genblk5[2] bank mrvq_full", false,-1); + vcdp->declBit(c+17609,"VX_cache genblk5[2] bank mrvq_stop", false,-1); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+17617,"VX_cache genblk5[2] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+17625,"VX_cache genblk5[2] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+17633,"VX_cache genblk5[2] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+17641,"VX_cache genblk5[2] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+17649,"VX_cache genblk5[2] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6369,"VX_cache genblk5[2] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+17665,"VX_cache genblk5[2] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+17673,"VX_cache genblk5[2] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+17681,"VX_cache genblk5[2] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+6377,"VX_cache genblk5[2] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+6385,"VX_cache genblk5[2] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+6393,"VX_cache genblk5[2] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+17689,"VX_cache genblk5[2] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+17697,"VX_cache genblk5[2] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+17713,"VX_cache genblk5[2] bank miss_add_rw", false,-1); + vcdp->declBus(c+17721,"VX_cache genblk5[2] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+17729,"VX_cache genblk5[2] bank is_fill_st2", false,-1); + vcdp->declBit(c+6401,"VX_cache genblk5[2] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+6409,"VX_cache genblk5[2] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+6417,"VX_cache genblk5[2] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+6425,"VX_cache genblk5[2] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+6433,"VX_cache genblk5[2] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+6449,"VX_cache genblk5[2] bank is_fill_in_pipe", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+8329+i*1,"VX_cache genblk5[2] bank is_fill_st1", true,(i+0));}} + vcdp->declBit(c+6457+i*1,"VX_cache genblk5[2] bank is_fill_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+8337+i*1,"VX_cache genblk5[2] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[2] bank j", false,-1, 31,0); - vcdp->declBit(c+8233,"VX_cache genblk5[2] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+8345,"VX_cache genblk5[2] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+8353,"VX_cache genblk5[2] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+8361,"VX_cache genblk5[2] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+8345,"VX_cache genblk5[2] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+8369,"VX_cache genblk5[2] bank qual_valid_st0", false,-1); - vcdp->declBus(c+8377,"VX_cache genblk5[2] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+8385,"VX_cache genblk5[2] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+8233,"VX_cache genblk5[2] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+8393,"VX_cache genblk5[2] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+8401,"VX_cache genblk5[2] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+8433,"VX_cache genblk5[2] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+8449,"VX_cache genblk5[2] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+8457,"VX_cache genblk5[2] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+8465,"VX_cache genblk5[2] bank qual_snp_invalidate_st0", false,-1); + vcdp->declBit(c+6465+i*1,"VX_cache genblk5[2] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[2] bank j", false,-1, 31,0); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+6473,"VX_cache genblk5[2] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+6481,"VX_cache genblk5[2] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+6489,"VX_cache genblk5[2] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+6473,"VX_cache genblk5[2] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+6497,"VX_cache genblk5[2] bank qual_valid_st0", false,-1); + vcdp->declBus(c+6505,"VX_cache genblk5[2] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+6513,"VX_cache genblk5[2] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+6521,"VX_cache genblk5[2] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+6529,"VX_cache genblk5[2] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+6561,"VX_cache genblk5[2] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+6577,"VX_cache genblk5[2] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+6585,"VX_cache genblk5[2] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+6593,"VX_cache genblk5[2] bank qual_snp_invalidate_st0", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+8473+i*1,"VX_cache genblk5[2] bank valid_st1", true,(i+0));}} + vcdp->declBit(c+6601+i*1,"VX_cache genblk5[2] bank valid_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+8481+i*1,"VX_cache genblk5[2] bank addr_st1", true,(i+0), 24,0);}} + vcdp->declBus(c+6609+i*1,"VX_cache genblk5[2] bank addr_st1", true,(i+0), 25,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+8489+i*1,"VX_cache genblk5[2] bank wsel_st1", true,(i+0), 1,0);}} + vcdp->declBus(c+6617+i*1,"VX_cache genblk5[2] bank wsel_st1", true,(i+0), 1,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+8497+i*1,"VX_cache genblk5[2] bank writeword_st1", true,(i+0), 31,0);}} + vcdp->declBus(c+6625+i*1,"VX_cache genblk5[2] bank writeword_st1", true,(i+0), 31,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+8505+i*2,"VX_cache genblk5[2] bank inst_meta_st1", true,(i+0), 48,0);}} + vcdp->declQuad(c+6633+i*2,"VX_cache genblk5[2] bank inst_meta_st1", true,(i+0), 48,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+8521+i*4,"VX_cache genblk5[2] bank writedata_st1", true,(i+0), 127,0);}} + vcdp->declArray(c+6649+i*4,"VX_cache genblk5[2] bank writedata_st1", true,(i+0), 127,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+8553+i*1,"VX_cache genblk5[2] bank is_snp_st1", true,(i+0));}} + vcdp->declBit(c+6681+i*1,"VX_cache genblk5[2] bank is_snp_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+8561+i*1,"VX_cache genblk5[2] bank snp_invalidate_st1", true,(i+0));}} + vcdp->declBit(c+6689+i*1,"VX_cache genblk5[2] bank snp_invalidate_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+8569+i*1,"VX_cache genblk5[2] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+8577,"VX_cache genblk5[2] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+8585,"VX_cache genblk5[2] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+8617,"VX_cache genblk5[2] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+8625,"VX_cache genblk5[2] bank miss_st1e", false,-1); - vcdp->declBit(c+8633,"VX_cache genblk5[2] bank dirty_st1e", false,-1); - vcdp->declBus(c+8641,"VX_cache genblk5[2] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+8649,"VX_cache genblk5[2] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+8665,"VX_cache genblk5[2] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+8673,"VX_cache genblk5[2] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+8681,"VX_cache genblk5[2] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+8689,"VX_cache genblk5[2] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+8697,"VX_cache genblk5[2] bank is_snp_st1e", false,-1); - vcdp->declBit(c+8705,"VX_cache genblk5[2] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+8713,"VX_cache genblk5[2] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+8721,"VX_cache genblk5[2] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+8729,"VX_cache genblk5[2] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+8737,"VX_cache genblk5[2] bank valid_st1e", false,-1); - vcdp->declBit(c+8745,"VX_cache genblk5[2] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+8753,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+8761,"VX_cache genblk5[2] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+8769,"VX_cache genblk5[2] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+8745,"VX_cache genblk5[2] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+30361,"VX_cache genblk5[2] bank valid_st2", false,-1); - vcdp->declBus(c+30369,"VX_cache genblk5[2] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+30377,"VX_cache genblk5[2] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+30385,"VX_cache genblk5[2] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+30393,"VX_cache genblk5[2] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+30425,"VX_cache genblk5[2] bank miss_st2", false,-1); - vcdp->declBit(c+30433,"VX_cache genblk5[2] bank dirty_st2", false,-1); - vcdp->declBus(c+30441,"VX_cache genblk5[2] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+30449,"VX_cache genblk5[2] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+30465,"VX_cache genblk5[2] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+30473,"VX_cache genblk5[2] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+30481,"VX_cache genblk5[2] bank is_snp_st2", false,-1); - vcdp->declBit(c+30489,"VX_cache genblk5[2] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+30497,"VX_cache genblk5[2] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+30505,"VX_cache genblk5[2] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+8777,"VX_cache genblk5[2] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+30513,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+30521,"VX_cache genblk5[2] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+8785,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+8793,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+30497,"VX_cache genblk5[2] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+8801,"VX_cache genblk5[2] bank miss_add_unqual", false,-1); - vcdp->declBit(c+8809,"VX_cache genblk5[2] bank miss_add", false,-1); - vcdp->declBus(c+19753,"VX_cache genblk5[2] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+30369,"VX_cache genblk5[2] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+30377,"VX_cache genblk5[2] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+30481,"VX_cache genblk5[2] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+30489,"VX_cache genblk5[2] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+8817,"VX_cache genblk5[2] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+8825,"VX_cache genblk5[2] bank cwbq_push", false,-1); - vcdp->declBit(c+1929,"VX_cache genblk5[2] bank cwbq_pop", false,-1); - vcdp->declBit(c+30529,"VX_cache genblk5[2] bank cwbq_empty", false,-1); - vcdp->declBit(c+30537,"VX_cache genblk5[2] bank cwbq_full", false,-1); - vcdp->declBit(c+8833,"VX_cache genblk5[2] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+30385,"VX_cache genblk5[2] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+30313,"VX_cache genblk5[2] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+30321,"VX_cache genblk5[2] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+8801,"VX_cache genblk5[2] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+8841,"VX_cache genblk5[2] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+8849,"VX_cache genblk5[2] bank dwbq_push", false,-1); - vcdp->declBit(c+1937,"VX_cache genblk5[2] bank dwbq_pop", false,-1); - vcdp->declBit(c+30545,"VX_cache genblk5[2] bank dwbq_empty", false,-1); - vcdp->declBit(c+30553,"VX_cache genblk5[2] bank dwbq_full", false,-1); - vcdp->declBit(c+8857,"VX_cache genblk5[2] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+8865,"VX_cache genblk5[2] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+8873,"VX_cache genblk5[2] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+8881,"VX_cache genblk5[2] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+8889,"VX_cache genblk5[2] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+30561,"VX_cache genblk5[2] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+30569,"VX_cache genblk5[2] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+697,"VX_cache genblk5[2] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+705,"VX_cache genblk5[2] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+30577,"VX_cache genblk5[2] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[2] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58537,"VX_cache genblk5[2] bank snp_req_queue push", false,-1); - vcdp->declBit(c+8081,"VX_cache genblk5[2] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+713,"VX_cache genblk5[2] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+8897,"VX_cache genblk5[2] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+30169,"VX_cache genblk5[2] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+30177,"VX_cache genblk5[2] bank snp_req_queue full", false,-1); - vcdp->declBus(c+30585,"VX_cache genblk5[2] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+30585,"VX_cache genblk5[2] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+8913,"VX_cache genblk5[2] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+729,"VX_cache genblk5[2] bank snp_req_queue writing", false,-1); + vcdp->declBit(c+6697+i*1,"VX_cache genblk5[2] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+6705,"VX_cache genblk5[2] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+6713,"VX_cache genblk5[2] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+6745,"VX_cache genblk5[2] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank miss_st1e", false,-1); + vcdp->declBit(c+6761,"VX_cache genblk5[2] bank dirty_st1e", false,-1); + vcdp->declBus(c+6769,"VX_cache genblk5[2] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+6777,"VX_cache genblk5[2] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+6793,"VX_cache genblk5[2] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+6801,"VX_cache genblk5[2] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+6809,"VX_cache genblk5[2] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+6817,"VX_cache genblk5[2] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+6825,"VX_cache genblk5[2] bank is_snp_st1e", false,-1); + vcdp->declBit(c+6833,"VX_cache genblk5[2] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+6841,"VX_cache genblk5[2] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+6849,"VX_cache genblk5[2] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+6857,"VX_cache genblk5[2] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+6865,"VX_cache genblk5[2] bank valid_st1e", false,-1); + vcdp->declBit(c+6873,"VX_cache genblk5[2] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+6881,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+6889,"VX_cache genblk5[2] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+6897,"VX_cache genblk5[2] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+6873,"VX_cache genblk5[2] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+17737,"VX_cache genblk5[2] bank valid_st2", false,-1); + vcdp->declBus(c+17745,"VX_cache genblk5[2] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+17753,"VX_cache genblk5[2] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+17761,"VX_cache genblk5[2] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+17769,"VX_cache genblk5[2] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+17801,"VX_cache genblk5[2] bank miss_st2", false,-1); + vcdp->declBit(c+17809,"VX_cache genblk5[2] bank dirty_st2", false,-1); + vcdp->declBus(c+17817,"VX_cache genblk5[2] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+17825,"VX_cache genblk5[2] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+17841,"VX_cache genblk5[2] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+17849,"VX_cache genblk5[2] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+17857,"VX_cache genblk5[2] bank is_snp_st2", false,-1); + vcdp->declBit(c+17865,"VX_cache genblk5[2] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+17873,"VX_cache genblk5[2] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+17881,"VX_cache genblk5[2] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+6905,"VX_cache genblk5[2] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+17889,"VX_cache genblk5[2] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+17897,"VX_cache genblk5[2] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+6913,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+6921,"VX_cache genblk5[2] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+17873,"VX_cache genblk5[2] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+6929,"VX_cache genblk5[2] bank miss_add_unqual", false,-1); + vcdp->declBit(c+6937,"VX_cache genblk5[2] bank miss_add", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+17745,"VX_cache genblk5[2] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+17753,"VX_cache genblk5[2] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+17857,"VX_cache genblk5[2] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+17865,"VX_cache genblk5[2] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+6945,"VX_cache genblk5[2] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+6953,"VX_cache genblk5[2] bank cwbq_push", false,-1); + vcdp->declBit(c+1033,"VX_cache genblk5[2] bank cwbq_pop", false,-1); + vcdp->declBit(c+17905,"VX_cache genblk5[2] bank cwbq_empty", false,-1); + vcdp->declBit(c+17913,"VX_cache genblk5[2] bank cwbq_full", false,-1); + vcdp->declBit(c+6961,"VX_cache genblk5[2] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+17761,"VX_cache genblk5[2] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+17689,"VX_cache genblk5[2] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+17697,"VX_cache genblk5[2] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+6929,"VX_cache genblk5[2] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+6969,"VX_cache genblk5[2] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+6977,"VX_cache genblk5[2] bank dwbq_push", false,-1); + vcdp->declBit(c+1041,"VX_cache genblk5[2] bank dwbq_pop", false,-1); + vcdp->declBit(c+17921,"VX_cache genblk5[2] bank dwbq_empty", false,-1); + vcdp->declBit(c+17929,"VX_cache genblk5[2] bank dwbq_full", false,-1); + vcdp->declBit(c+6985,"VX_cache genblk5[2] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+6993,"VX_cache genblk5[2] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+7001,"VX_cache genblk5[2] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+7009,"VX_cache genblk5[2] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+7017,"VX_cache genblk5[2] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+17937,"VX_cache genblk5[2] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+17945,"VX_cache genblk5[2] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+569,"VX_cache genblk5[2] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+577,"VX_cache genblk5[2] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+17953,"VX_cache genblk5[2] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[2] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+25017,"VX_cache genblk5[2] bank snp_req_queue push", false,-1); + vcdp->declBit(c+6209,"VX_cache genblk5[2] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+585,"VX_cache genblk5[2] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+7025,"VX_cache genblk5[2] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+17545,"VX_cache genblk5[2] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+17553,"VX_cache genblk5[2] bank snp_req_queue full", false,-1); + vcdp->declBus(c+17961,"VX_cache genblk5[2] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+17961,"VX_cache genblk5[2] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+7041,"VX_cache genblk5[2] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+601,"VX_cache genblk5[2] bank snp_req_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+30593+i*2,"VX_cache genblk5[2] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+30849,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+30865,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+30881,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+30889,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+30897,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+30169,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+30177,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+30905,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[2] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58529,"VX_cache genblk5[2] bank dfp_queue push", false,-1); - vcdp->declBit(c+8113,"VX_cache genblk5[2] bank dfp_queue pop", false,-1); - vcdp->declArray(c+737,"VX_cache genblk5[2] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+8921,"VX_cache genblk5[2] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+30185,"VX_cache genblk5[2] bank dfp_queue empty", false,-1); - vcdp->declBit(c+30193,"VX_cache genblk5[2] bank dfp_queue full", false,-1); - vcdp->declBus(c+30913,"VX_cache genblk5[2] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+30913,"VX_cache genblk5[2] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+8961,"VX_cache genblk5[2] bank dfp_queue reading", false,-1); - vcdp->declBit(c+777,"VX_cache genblk5[2] bank dfp_queue writing", false,-1); + vcdp->declQuad(c+17969+i*2,"VX_cache genblk5[2] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+18225,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+18241,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+18257,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+18265,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+18273,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+17545,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17553,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+18281,"VX_cache genblk5[2] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[2] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank dfp_queue reset", false,-1); + vcdp->declBit(c+25009,"VX_cache genblk5[2] bank dfp_queue push", false,-1); + vcdp->declBit(c+6241,"VX_cache genblk5[2] bank dfp_queue pop", false,-1); + vcdp->declArray(c+609,"VX_cache genblk5[2] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+7049,"VX_cache genblk5[2] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+17561,"VX_cache genblk5[2] bank dfp_queue empty", false,-1); + vcdp->declBit(c+17569,"VX_cache genblk5[2] bank dfp_queue full", false,-1); + vcdp->declBus(c+18289,"VX_cache genblk5[2] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+18289,"VX_cache genblk5[2] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+7089,"VX_cache genblk5[2] bank dfp_queue reading", false,-1); + vcdp->declBit(c+649,"VX_cache genblk5[2] bank dfp_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+30921+i*5,"VX_cache genblk5[2] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+31561,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+31601,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+31641,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+31649,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+31657,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+30185,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+30193,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+31665,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank core_req_arb reset", false,-1); - vcdp->declBit(c+1921,"VX_cache genblk5[2] bank core_req_arb reqq_push", false,-1); + vcdp->declArray(c+18297+i*5,"VX_cache genblk5[2] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+18937,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+18977,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+19017,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+19025,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+19033,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+17561,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17569,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+19041,"VX_cache genblk5[2] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[2] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1025,"VX_cache genblk5[2] bank core_req_arb reqq_push", false,-1); vcdp->declBus(c+97,"VX_cache genblk5[2] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[2] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[2] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[2] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[2] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[2] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+8161,"VX_cache genblk5[2] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+8193,"VX_cache genblk5[2] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+8201,"VX_cache genblk5[2] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+8209,"VX_cache genblk5[2] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+8217,"VX_cache genblk5[2] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+8169,"VX_cache genblk5[2] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+30201,"VX_cache genblk5[2] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+8969,"VX_cache genblk5[2] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+8977,"VX_cache genblk5[2] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+8985,"VX_cache genblk5[2] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+8993,"VX_cache genblk5[2] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+9025,"VX_cache genblk5[2] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+9057,"VX_cache genblk5[2] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+31681,"VX_cache genblk5[2] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+31689,"VX_cache genblk5[2] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+31697,"VX_cache genblk5[2] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+31729,"VX_cache genblk5[2] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+31681,"VX_cache genblk5[2] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+31689,"VX_cache genblk5[2] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+31697,"VX_cache genblk5[2] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+31729,"VX_cache genblk5[2] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+30209,"VX_cache genblk5[2] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+31761,"VX_cache genblk5[2] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+31769,"VX_cache genblk5[2] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+9073,"VX_cache genblk5[2] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+1945,"VX_cache genblk5[2] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+9081,"VX_cache genblk5[2] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+9089,"VX_cache genblk5[2] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[2] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+1945,"VX_cache genblk5[2] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+9081,"VX_cache genblk5[2] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+785,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+9097,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+31761,"VX_cache genblk5[2] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+30201,"VX_cache genblk5[2] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+31777,"VX_cache genblk5[2] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+31777,"VX_cache genblk5[2] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+9177,"VX_cache genblk5[2] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+865,"VX_cache genblk5[2] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+31785+i*10,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+32425,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+32505,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+32585,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+32593,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+32601,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+31761,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+30201,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+32609,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+9185,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+9185,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+31673,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+8185,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+8177,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+9193,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[2] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[2] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+8313,"VX_cache genblk5[2] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[2] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+9201,"VX_cache genblk5[2] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+32617,"VX_cache genblk5[2] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+32617,"VX_cache genblk5[2] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[2] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank tag_data_access reset", false,-1); - vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access stall", false,-1); - vcdp->declBit(c+8697,"VX_cache genblk5[2] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+8705,"VX_cache genblk5[2] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+8265,"VX_cache genblk5[2] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+8761,"VX_cache genblk5[2] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+8737,"VX_cache genblk5[2] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+9273,"VX_cache genblk5[2] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+9281,"VX_cache genblk5[2] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+9289,"VX_cache genblk5[2] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+8673,"VX_cache genblk5[2] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+8681,"VX_cache genblk5[2] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+9321,"VX_cache genblk5[2] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+8577,"VX_cache genblk5[2] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+8585,"VX_cache genblk5[2] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+8617,"VX_cache genblk5[2] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+8625,"VX_cache genblk5[2] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+8633,"VX_cache genblk5[2] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+8641,"VX_cache genblk5[2] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+8689,"VX_cache genblk5[2] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+8713,"VX_cache genblk5[2] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+8721,"VX_cache genblk5[2] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+9329+i*1,"VX_cache genblk5[2] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+9337+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+9345+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+9353+i*1,"VX_cache genblk5[2] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+9361+i*4,"VX_cache genblk5[2] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+9393,"VX_cache genblk5[2] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+9401,"VX_cache genblk5[2] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+9409,"VX_cache genblk5[2] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+9417,"VX_cache genblk5[2] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+9425,"VX_cache genblk5[2] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+9457,"VX_cache genblk5[2] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+9465,"VX_cache genblk5[2] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+8641,"VX_cache genblk5[2] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+8617,"VX_cache genblk5[2] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+8585,"VX_cache genblk5[2] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+9473,"VX_cache genblk5[2] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+9481,"VX_cache genblk5[2] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+8625,"VX_cache genblk5[2] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+9513,"VX_cache genblk5[2] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+9521,"VX_cache genblk5[2] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+9529,"VX_cache genblk5[2] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+9537,"VX_cache genblk5[2] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+9545,"VX_cache genblk5[2] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+9481,"VX_cache genblk5[2] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+9553,"VX_cache genblk5[2] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+9513,"VX_cache genblk5[2] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+9561,"VX_cache genblk5[2] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+9569,"VX_cache genblk5[2] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+9577,"VX_cache genblk5[2] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+9585,"VX_cache genblk5[2] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+9593,"VX_cache genblk5[2] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+9601,"VX_cache genblk5[2] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+9609,"VX_cache genblk5[2] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+9617,"VX_cache genblk5[2] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[2] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+9393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+9401,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+9409,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+9417,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+9425,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+9513,"VX_cache genblk5[2] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+9473,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+9529,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+9265,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+9537,"VX_cache genblk5[2] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+9481,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+8625,"VX_cache genblk5[2] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+32681,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+32713,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+32745,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+32777,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+32809,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+32841,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+32873,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+32905,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+32937,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+32969,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+33001,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+33033,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+33065,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+33097,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+33129,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+33161,"VX_cache genblk5[2] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+33193+i*1,"VX_cache genblk5[2] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+33321,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+33329,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+33337,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+33345,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+33353,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+33361,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+33369,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+33377,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+33385,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+33393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+33401,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+33409,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+33417,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+33425,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+33433,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+33441,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+33449,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+33457,"VX_cache genblk5[2] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+9625,"VX_cache genblk5[2] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+33465,"VX_cache genblk5[2] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+33473,"VX_cache genblk5[2] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+8313,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+9633,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+9633,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+33481,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[2] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[2] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+8313,"VX_cache genblk5[2] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[2] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+9681,"VX_cache genblk5[2] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+33529,"VX_cache genblk5[2] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+33529,"VX_cache genblk5[2] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[2] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58825,"VX_cache genblk5[2] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[2] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[2] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[2] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+8809,"VX_cache genblk5[2] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+8817,"VX_cache genblk5[2] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19753,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+30369,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+30377,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+30313,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+30321,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+30337,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+30345,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+8777,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+30481,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+30489,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+30225,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+30233,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+9273,"VX_cache genblk5[2] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+8761,"VX_cache genblk5[2] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+8249,"VX_cache genblk5[2] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+8225,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+8233,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+30249,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+30257,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+30265,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+30241,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+30273,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+8241,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+30289,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+30297,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+30305,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+33609+i*3,"VX_cache genblk5[2] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+33993,"VX_cache genblk5[2] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+34097,"VX_cache genblk5[2] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+34105,"VX_cache genblk5[2] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+34113,"VX_cache genblk5[2] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+34121,"VX_cache genblk5[2] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+34129,"VX_cache genblk5[2] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+34137,"VX_cache genblk5[2] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+34145,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+34129,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+9761,"VX_cache genblk5[2] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+9769,"VX_cache genblk5[2] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+9777,"VX_cache genblk5[2] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+8233,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+34113,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+9785,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+9793,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+9801,"VX_cache genblk5[2] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+9809,"VX_cache genblk5[2] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+9817,"VX_cache genblk5[2] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+9825,"VX_cache genblk5[2] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[2] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[2] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank cwb_queue reset", false,-1); - vcdp->declBit(c+8825,"VX_cache genblk5[2] bank cwb_queue push", false,-1); - vcdp->declBit(c+1929,"VX_cache genblk5[2] bank cwb_queue pop", false,-1); - vcdp->declArray(c+9833,"VX_cache genblk5[2] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+9857,"VX_cache genblk5[2] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+30529,"VX_cache genblk5[2] bank cwb_queue empty", false,-1); - vcdp->declBit(c+30537,"VX_cache genblk5[2] bank cwb_queue full", false,-1); - vcdp->declBus(c+34153,"VX_cache genblk5[2] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+34153,"VX_cache genblk5[2] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+873,"VX_cache genblk5[2] bank cwb_queue reading", false,-1); - vcdp->declBit(c+9881,"VX_cache genblk5[2] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+34161+i*3,"VX_cache genblk5[2] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+34353,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+34377,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+34401,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+34409,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+34417,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+30529,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+30537,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+34425,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[2] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[2] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[2] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[2] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[2] bank dwb_queue reset", false,-1); - vcdp->declBit(c+8849,"VX_cache genblk5[2] bank dwb_queue push", false,-1); - vcdp->declBit(c+1937,"VX_cache genblk5[2] bank dwb_queue pop", false,-1); - vcdp->declArray(c+9889,"VX_cache genblk5[2] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+9945,"VX_cache genblk5[2] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+30545,"VX_cache genblk5[2] bank dwb_queue empty", false,-1); - vcdp->declBit(c+30553,"VX_cache genblk5[2] bank dwb_queue full", false,-1); - vcdp->declBus(c+34433,"VX_cache genblk5[2] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+34433,"VX_cache genblk5[2] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+881,"VX_cache genblk5[2] bank dwb_queue reading", false,-1); - vcdp->declBit(c+10001,"VX_cache genblk5[2] bank dwb_queue writing", false,-1); + vcdp->declBus(c+24513,"VX_cache genblk5[2] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[2] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[2] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[2] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[2] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+6289,"VX_cache genblk5[2] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+6321,"VX_cache genblk5[2] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+6329,"VX_cache genblk5[2] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+6337,"VX_cache genblk5[2] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+6345,"VX_cache genblk5[2] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6297,"VX_cache genblk5[2] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+7097,"VX_cache genblk5[2] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+7105,"VX_cache genblk5[2] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+7113,"VX_cache genblk5[2] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+7121,"VX_cache genblk5[2] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+7153,"VX_cache genblk5[2] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+7185,"VX_cache genblk5[2] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+19057,"VX_cache genblk5[2] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+19065,"VX_cache genblk5[2] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+19073,"VX_cache genblk5[2] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+19105,"VX_cache genblk5[2] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+19057,"VX_cache genblk5[2] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+19065,"VX_cache genblk5[2] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+19073,"VX_cache genblk5[2] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+19105,"VX_cache genblk5[2] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+17585,"VX_cache genblk5[2] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+19137,"VX_cache genblk5[2] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+19145,"VX_cache genblk5[2] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+7201,"VX_cache genblk5[2] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1049,"VX_cache genblk5[2] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+7209,"VX_cache genblk5[2] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+7217,"VX_cache genblk5[2] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[2] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1049,"VX_cache genblk5[2] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+7209,"VX_cache genblk5[2] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+657,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+7225,"VX_cache genblk5[2] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+19137,"VX_cache genblk5[2] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+19153,"VX_cache genblk5[2] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+19153,"VX_cache genblk5[2] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+7305,"VX_cache genblk5[2] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+737,"VX_cache genblk5[2] bank core_req_arb reqq_queue writing", false,-1); {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+34441+i*7,"VX_cache genblk5[2] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+34665,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+34721,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+34777,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+34785,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+34793,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+30545,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+30553,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+34801,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58641,"VX_cache genblk5[3] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58833,"VX_cache genblk5[3] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[3] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[3] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[3] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[3] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank reset", false,-1); + vcdp->declArray(c+19161+i*10,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+19481,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+19561,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+19641,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+19649,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+19657,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+19137,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17577,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+19665,"VX_cache genblk5[2] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+7313,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+7313,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+19049,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+6313,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+6305,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+7321,"VX_cache genblk5[2] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[2] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[2] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+7329,"VX_cache genblk5[2] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+19673,"VX_cache genblk5[2] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+19673,"VX_cache genblk5[2] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[2] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank tag_data_access reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access stall", false,-1); + vcdp->declBit(c+6825,"VX_cache genblk5[2] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+6833,"VX_cache genblk5[2] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+6393,"VX_cache genblk5[2] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+6889,"VX_cache genblk5[2] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+6865,"VX_cache genblk5[2] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+7401,"VX_cache genblk5[2] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+7409,"VX_cache genblk5[2] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+7417,"VX_cache genblk5[2] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+6801,"VX_cache genblk5[2] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+6809,"VX_cache genblk5[2] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+7449,"VX_cache genblk5[2] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+6705,"VX_cache genblk5[2] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+6713,"VX_cache genblk5[2] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+6745,"VX_cache genblk5[2] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+6761,"VX_cache genblk5[2] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+6769,"VX_cache genblk5[2] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+6817,"VX_cache genblk5[2] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+6841,"VX_cache genblk5[2] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+6849,"VX_cache genblk5[2] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+7457+i*1,"VX_cache genblk5[2] bank tag_data_access read_valid_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBit(c+7465+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirty_st1c", true,(i+0));}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+7473+i*1,"VX_cache genblk5[2] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declBus(c+7481+i*1,"VX_cache genblk5[2] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} + {int i; for (i=0; i<1; i++) { + vcdp->declArray(c+7489+i*4,"VX_cache genblk5[2] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+7521,"VX_cache genblk5[2] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+7529,"VX_cache genblk5[2] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+7537,"VX_cache genblk5[2] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+7545,"VX_cache genblk5[2] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+7553,"VX_cache genblk5[2] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+7585,"VX_cache genblk5[2] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+7593,"VX_cache genblk5[2] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+6769,"VX_cache genblk5[2] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+6745,"VX_cache genblk5[2] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+6713,"VX_cache genblk5[2] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+7601,"VX_cache genblk5[2] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+7609,"VX_cache genblk5[2] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+7641,"VX_cache genblk5[2] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+7649,"VX_cache genblk5[2] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+7657,"VX_cache genblk5[2] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+7665,"VX_cache genblk5[2] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+7673,"VX_cache genblk5[2] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+7609,"VX_cache genblk5[2] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+7681,"VX_cache genblk5[2] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+7641,"VX_cache genblk5[2] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+7689,"VX_cache genblk5[2] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+7697,"VX_cache genblk5[2] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+7705,"VX_cache genblk5[2] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+7713,"VX_cache genblk5[2] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+7721,"VX_cache genblk5[2] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+7729,"VX_cache genblk5[2] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+7737,"VX_cache genblk5[2] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+7745,"VX_cache genblk5[2] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[2] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+7521,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+7529,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+7537,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+7545,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+7553,"VX_cache genblk5[2] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+7641,"VX_cache genblk5[2] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+7601,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+7657,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+7393,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+7665,"VX_cache genblk5[2] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+7609,"VX_cache genblk5[2] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+6753,"VX_cache genblk5[2] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+19737,"VX_cache genblk5[2] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+19753,"VX_cache genblk5[2] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+7753,"VX_cache genblk5[2] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+19769,"VX_cache genblk5[2] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+19777,"VX_cache genblk5[2] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+7761,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+7761,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+19785,"VX_cache genblk5[2] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[2] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+6441,"VX_cache genblk5[2] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[2] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+7809,"VX_cache genblk5[2] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+19833,"VX_cache genblk5[2] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+19833,"VX_cache genblk5[2] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[2] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25233,"VX_cache genblk5[2] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[2] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[2] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[2] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+6937,"VX_cache genblk5[2] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+6945,"VX_cache genblk5[2] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10169,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+17745,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+17753,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+17689,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+17697,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+17713,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+17721,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+6905,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+17857,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+17865,"VX_cache genblk5[2] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+17601,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+17609,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+7401,"VX_cache genblk5[2] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+6889,"VX_cache genblk5[2] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+6377,"VX_cache genblk5[2] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+6353,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+17625,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+17633,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+17641,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+17617,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+17649,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+6369,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+17665,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+17673,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+17681,"VX_cache genblk5[2] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); + {int i; for (i=0; i<16; i++) { + vcdp->declArray(c+19913+i*3,"VX_cache genblk5[2] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+20297,"VX_cache genblk5[2] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+20401,"VX_cache genblk5[2] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+20409,"VX_cache genblk5[2] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+20417,"VX_cache genblk5[2] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+20425,"VX_cache genblk5[2] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+20433,"VX_cache genblk5[2] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+20441,"VX_cache genblk5[2] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+20449,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+20433,"VX_cache genblk5[2] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+7889,"VX_cache genblk5[2] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+7897,"VX_cache genblk5[2] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+7905,"VX_cache genblk5[2] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+6361,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+20417,"VX_cache genblk5[2] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+7913,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+7921,"VX_cache genblk5[2] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+7929,"VX_cache genblk5[2] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+7937,"VX_cache genblk5[2] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+7945,"VX_cache genblk5[2] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+7953,"VX_cache genblk5[2] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[2] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank cwb_queue reset", false,-1); + vcdp->declBit(c+6953,"VX_cache genblk5[2] bank cwb_queue push", false,-1); + vcdp->declBit(c+1033,"VX_cache genblk5[2] bank cwb_queue pop", false,-1); + vcdp->declArray(c+7961,"VX_cache genblk5[2] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+7985,"VX_cache genblk5[2] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+17905,"VX_cache genblk5[2] bank cwb_queue empty", false,-1); + vcdp->declBit(c+17913,"VX_cache genblk5[2] bank cwb_queue full", false,-1); + vcdp->declBus(c+20457,"VX_cache genblk5[2] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+20457,"VX_cache genblk5[2] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+745,"VX_cache genblk5[2] bank cwb_queue reading", false,-1); + vcdp->declBit(c+8009,"VX_cache genblk5[2] bank cwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+20465+i*3,"VX_cache genblk5[2] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+20561,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+20585,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+20609,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+20617,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+20625,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+17905,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17913,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+20633,"VX_cache genblk5[2] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[2] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[2] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[2] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[2] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[2] bank dwb_queue reset", false,-1); + vcdp->declBit(c+6977,"VX_cache genblk5[2] bank dwb_queue push", false,-1); + vcdp->declBit(c+1041,"VX_cache genblk5[2] bank dwb_queue pop", false,-1); + vcdp->declArray(c+8017,"VX_cache genblk5[2] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+8073,"VX_cache genblk5[2] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+17921,"VX_cache genblk5[2] bank dwb_queue empty", false,-1); + vcdp->declBit(c+17929,"VX_cache genblk5[2] bank dwb_queue full", false,-1); + vcdp->declBus(c+20641,"VX_cache genblk5[2] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+20641,"VX_cache genblk5[2] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+753,"VX_cache genblk5[2] bank dwb_queue reading", false,-1); + vcdp->declBit(c+8129,"VX_cache genblk5[2] bank dwb_queue writing", false,-1); + {int i; for (i=0; i<4; i++) { + vcdp->declArray(c+20649+i*7,"VX_cache genblk5[2] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+20873,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+20929,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+20985,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+20993,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+21001,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+17921,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+17929,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+21009,"VX_cache genblk5[2] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25241,"VX_cache genblk5[3] bank BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25065,"VX_cache genblk5[3] bank CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank DFPQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank SNRQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank CWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank DWBQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank DFQQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank DRAM_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank SNOOP_FORWARDING", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[3] bank CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[3] bank CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[3] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank reset", false,-1); vcdp->declBus(c+129,"VX_cache genblk5[3] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[3] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[3] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[3] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[3] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[3] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19809,"VX_cache genblk5[3] bank core_req_ready", false,-1); - vcdp->declBit(c+19777,"VX_cache genblk5[3] bank core_rsp_valid", false,-1); - vcdp->declBus(c+3121,"VX_cache genblk5[3] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3129,"VX_cache genblk5[3] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3137,"VX_cache genblk5[3] bank core_rsp_tag", false,-1, 41,0); + vcdp->declBus(c+24513,"VX_cache genblk5[3] bank core_req_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[3] bank core_req_byteen", false,-1, 15,0); + vcdp->declArray(c+24529,"VX_cache genblk5[3] bank core_req_addr", false,-1, 119,0); + vcdp->declArray(c+24561,"VX_cache genblk5[3] bank core_req_data", false,-1, 127,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[3] bank core_req_tag", false,-1, 41,0); + vcdp->declBit(c+10225,"VX_cache genblk5[3] bank core_req_ready", false,-1); + vcdp->declBit(c+10193,"VX_cache genblk5[3] bank core_rsp_valid", false,-1); + vcdp->declBus(c+1809,"VX_cache genblk5[3] bank core_rsp_tid", false,-1, 1,0); + vcdp->declBus(c+1817,"VX_cache genblk5[3] bank core_rsp_data", false,-1, 31,0); + vcdp->declQuad(c+1825,"VX_cache genblk5[3] bank core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+137,"VX_cache genblk5[3] bank core_rsp_ready", false,-1); - vcdp->declBit(c+3153,"VX_cache genblk5[3] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19793,"VX_cache genblk5[3] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[3] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58545,"VX_cache genblk5[3] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[3] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[3] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19785,"VX_cache genblk5[3] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3161,"VX_cache genblk5[3] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+3169,"VX_cache genblk5[3] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3177,"VX_cache genblk5[3] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3185,"VX_cache genblk5[3] bank dram_wb_req_data", false,-1, 127,0); + vcdp->declBit(c+1841,"VX_cache genblk5[3] bank dram_fill_req_valid", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank dram_fill_req_addr", false,-1, 25,0); + vcdp->declBit(c+10065,"VX_cache genblk5[3] bank dram_fill_req_ready", false,-1); + vcdp->declBit(c+25025,"VX_cache genblk5[3] bank dram_fill_rsp_valid", false,-1); + vcdp->declArray(c+24769,"VX_cache genblk5[3] bank dram_fill_rsp_data", false,-1, 127,0); + vcdp->declBus(c+24969,"VX_cache genblk5[3] bank dram_fill_rsp_addr", false,-1, 25,0); + vcdp->declBit(c+10201,"VX_cache genblk5[3] bank dram_fill_rsp_ready", false,-1); + vcdp->declBit(c+1849,"VX_cache genblk5[3] bank dram_wb_req_valid", false,-1); + vcdp->declBus(c+1857,"VX_cache genblk5[3] bank dram_wb_req_byteen", false,-1, 15,0); + vcdp->declBus(c+1865,"VX_cache genblk5[3] bank dram_wb_req_addr", false,-1, 25,0); + vcdp->declArray(c+1873,"VX_cache genblk5[3] bank dram_wb_req_data", false,-1, 127,0); vcdp->declBit(c+145,"VX_cache genblk5[3] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58553,"VX_cache genblk5[3] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[3] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[3] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[3] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19801,"VX_cache genblk5[3] bank snp_req_ready", false,-1); - vcdp->declBit(c+3217,"VX_cache genblk5[3] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+3225,"VX_cache genblk5[3] bank snp_rsp_tag", false,-1, 27,0); + vcdp->declBit(c+25033,"VX_cache genblk5[3] bank snp_req_valid", false,-1); + vcdp->declBus(c+24985,"VX_cache genblk5[3] bank snp_req_addr", false,-1, 25,0); + vcdp->declBit(c+24833,"VX_cache genblk5[3] bank snp_req_invalidate", false,-1); + vcdp->declBus(c+24841,"VX_cache genblk5[3] bank snp_req_tag", false,-1, 27,0); + vcdp->declBit(c+10217,"VX_cache genblk5[3] bank snp_req_ready", false,-1); + vcdp->declBit(c+1905,"VX_cache genblk5[3] bank snp_rsp_valid", false,-1); + vcdp->declBus(c+1913,"VX_cache genblk5[3] bank snp_rsp_tag", false,-1, 27,0); vcdp->declBit(c+153,"VX_cache genblk5[3] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+10009,"VX_cache genblk5[3] bank snrq_pop", false,-1); - vcdp->declBit(c+34809,"VX_cache genblk5[3] bank snrq_empty", false,-1); - vcdp->declBit(c+34817,"VX_cache genblk5[3] bank snrq_full", false,-1); - vcdp->declBus(c+10017,"VX_cache genblk5[3] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+10025,"VX_cache genblk5[3] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+10033,"VX_cache genblk5[3] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+10041,"VX_cache genblk5[3] bank dfpq_pop", false,-1); - vcdp->declBit(c+34825,"VX_cache genblk5[3] bank dfpq_empty", false,-1); - vcdp->declBit(c+34833,"VX_cache genblk5[3] bank dfpq_full", false,-1); - vcdp->declBus(c+10049,"VX_cache genblk5[3] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+10057,"VX_cache genblk5[3] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+10089,"VX_cache genblk5[3] bank reqq_pop", false,-1); - vcdp->declBit(c+1953,"VX_cache genblk5[3] bank reqq_push", false,-1); - vcdp->declBit(c+10097,"VX_cache genblk5[3] bank reqq_empty", false,-1); - vcdp->declBit(c+34841,"VX_cache genblk5[3] bank reqq_full", false,-1); - vcdp->declBit(c+10105,"VX_cache genblk5[3] bank reqq_req_st0", false,-1); - vcdp->declBus(c+10113,"VX_cache genblk5[3] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+10121,"VX_cache genblk5[3] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+10129,"VX_cache genblk5[3] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+10137,"VX_cache genblk5[3] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+10145,"VX_cache genblk5[3] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+10153,"VX_cache genblk5[3] bank mrvq_pop", false,-1); - vcdp->declBit(c+34865,"VX_cache genblk5[3] bank mrvq_full", false,-1); - vcdp->declBit(c+34873,"VX_cache genblk5[3] bank mrvq_stop", false,-1); - vcdp->declBit(c+10161,"VX_cache genblk5[3] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+34881,"VX_cache genblk5[3] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+34889,"VX_cache genblk5[3] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+34897,"VX_cache genblk5[3] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+34905,"VX_cache genblk5[3] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+34913,"VX_cache genblk5[3] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+10169,"VX_cache genblk5[3] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+34929,"VX_cache genblk5[3] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+34937,"VX_cache genblk5[3] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+34945,"VX_cache genblk5[3] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+10177,"VX_cache genblk5[3] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+10185,"VX_cache genblk5[3] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+10193,"VX_cache genblk5[3] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+34953,"VX_cache genblk5[3] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+34961,"VX_cache genblk5[3] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+34977,"VX_cache genblk5[3] bank miss_add_rw", false,-1); - vcdp->declBus(c+34985,"VX_cache genblk5[3] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19793,"VX_cache genblk5[3] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+34993,"VX_cache genblk5[3] bank is_fill_st2", false,-1); - vcdp->declBit(c+10201,"VX_cache genblk5[3] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+10209,"VX_cache genblk5[3] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+10217,"VX_cache genblk5[3] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+10225,"VX_cache genblk5[3] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+10233,"VX_cache genblk5[3] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+10241,"VX_cache genblk5[3] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+10249,"VX_cache genblk5[3] bank is_fill_in_pipe", false,-1); + vcdp->declBit(c+8137,"VX_cache genblk5[3] bank snrq_pop", false,-1); + vcdp->declBit(c+21017,"VX_cache genblk5[3] bank snrq_empty", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[3] bank snrq_full", false,-1); + vcdp->declBus(c+8145,"VX_cache genblk5[3] bank snrq_addr_st0", false,-1, 25,0); + vcdp->declBit(c+8153,"VX_cache genblk5[3] bank snrq_invalidate_st0", false,-1); + vcdp->declBus(c+8161,"VX_cache genblk5[3] bank snrq_tag_st0", false,-1, 27,0); + vcdp->declBit(c+8169,"VX_cache genblk5[3] bank dfpq_pop", false,-1); + vcdp->declBit(c+21033,"VX_cache genblk5[3] bank dfpq_empty", false,-1); + vcdp->declBit(c+21041,"VX_cache genblk5[3] bank dfpq_full", false,-1); + vcdp->declBus(c+8177,"VX_cache genblk5[3] bank dfpq_addr_st0", false,-1, 25,0); + vcdp->declArray(c+8185,"VX_cache genblk5[3] bank dfpq_filldata_st0", false,-1, 127,0); + vcdp->declBit(c+8217,"VX_cache genblk5[3] bank reqq_pop", false,-1); + vcdp->declBit(c+1057,"VX_cache genblk5[3] bank reqq_push", false,-1); + vcdp->declBit(c+8225,"VX_cache genblk5[3] bank reqq_empty", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank reqq_full", false,-1); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank reqq_req_st0", false,-1); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+8249,"VX_cache genblk5[3] bank reqq_req_rw_st0", false,-1); + vcdp->declBus(c+8257,"VX_cache genblk5[3] bank reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+8265,"VX_cache genblk5[3] bank reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+8273,"VX_cache genblk5[3] bank reqq_req_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8281,"VX_cache genblk5[3] bank mrvq_pop", false,-1); + vcdp->declBit(c+21073,"VX_cache genblk5[3] bank mrvq_full", false,-1); + vcdp->declBit(c+21081,"VX_cache genblk5[3] bank mrvq_stop", false,-1); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank mrvq_valid_st0", false,-1); + vcdp->declBus(c+21089,"VX_cache genblk5[3] bank mrvq_tid_st0", false,-1, 1,0); + vcdp->declBus(c+21097,"VX_cache genblk5[3] bank mrvq_addr_st0", false,-1, 25,0); + vcdp->declBus(c+21105,"VX_cache genblk5[3] bank mrvq_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+21113,"VX_cache genblk5[3] bank mrvq_writeword_st0", false,-1, 31,0); + vcdp->declQuad(c+21121,"VX_cache genblk5[3] bank mrvq_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8297,"VX_cache genblk5[3] bank mrvq_rw_st0", false,-1); + vcdp->declBus(c+21137,"VX_cache genblk5[3] bank mrvq_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+21145,"VX_cache genblk5[3] bank mrvq_is_snp_st0", false,-1); + vcdp->declBit(c+21153,"VX_cache genblk5[3] bank mrvq_snp_invalidate_st0", false,-1); + vcdp->declBit(c+8305,"VX_cache genblk5[3] bank mrvq_pending_hazard_st1e", false,-1); + vcdp->declBit(c+8313,"VX_cache genblk5[3] bank st2_pending_hazard_st1e", false,-1); + vcdp->declBit(c+8321,"VX_cache genblk5[3] bank force_request_miss_st1e", false,-1); + vcdp->declBus(c+21161,"VX_cache genblk5[3] bank miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+21169,"VX_cache genblk5[3] bank miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+21185,"VX_cache genblk5[3] bank miss_add_rw", false,-1); + vcdp->declBus(c+21193,"VX_cache genblk5[3] bank miss_add_byteen", false,-1, 3,0); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank addr_st2", false,-1, 25,0); + vcdp->declBit(c+21201,"VX_cache genblk5[3] bank is_fill_st2", false,-1); + vcdp->declBit(c+8329,"VX_cache genblk5[3] bank recover_mrvq_state_st2", false,-1); + vcdp->declBit(c+8337,"VX_cache genblk5[3] bank mrvq_push_stall", false,-1); + vcdp->declBit(c+8345,"VX_cache genblk5[3] bank cwbq_push_stall", false,-1); + vcdp->declBit(c+8353,"VX_cache genblk5[3] bank dwbq_push_stall", false,-1); + vcdp->declBit(c+8361,"VX_cache genblk5[3] bank dram_fill_req_stall", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank stall_bank_pipe", false,-1); + vcdp->declBit(c+8377,"VX_cache genblk5[3] bank is_fill_in_pipe", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+10257+i*1,"VX_cache genblk5[3] bank is_fill_st1", true,(i+0));}} + vcdp->declBit(c+8385+i*1,"VX_cache genblk5[3] bank is_fill_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+10265+i*1,"VX_cache genblk5[3] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[3] bank j", false,-1, 31,0); - vcdp->declBit(c+10161,"VX_cache genblk5[3] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+10273,"VX_cache genblk5[3] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+10281,"VX_cache genblk5[3] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+10289,"VX_cache genblk5[3] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+10273,"VX_cache genblk5[3] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+10297,"VX_cache genblk5[3] bank qual_valid_st0", false,-1); - vcdp->declBus(c+10305,"VX_cache genblk5[3] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+10313,"VX_cache genblk5[3] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+10161,"VX_cache genblk5[3] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+10321,"VX_cache genblk5[3] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+10329,"VX_cache genblk5[3] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+10361,"VX_cache genblk5[3] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+10377,"VX_cache genblk5[3] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+10385,"VX_cache genblk5[3] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+10393,"VX_cache genblk5[3] bank qual_snp_invalidate_st0", false,-1); + vcdp->declBit(c+8393+i*1,"VX_cache genblk5[3] bank going_to_write_st1", true,(i+0));}} + vcdp->declBus(c+25161,"VX_cache genblk5[3] bank j", false,-1, 31,0); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank mrvq_pop_unqual", false,-1); + vcdp->declBit(c+8401,"VX_cache genblk5[3] bank dfpq_pop_unqual", false,-1); + vcdp->declBit(c+8409,"VX_cache genblk5[3] bank reqq_pop_unqual", false,-1); + vcdp->declBit(c+8417,"VX_cache genblk5[3] bank snrq_pop_unqual", false,-1); + vcdp->declBit(c+8401,"VX_cache genblk5[3] bank qual_is_fill_st0", false,-1); + vcdp->declBit(c+8425,"VX_cache genblk5[3] bank qual_valid_st0", false,-1); + vcdp->declBus(c+8433,"VX_cache genblk5[3] bank qual_addr_st0", false,-1, 25,0); + vcdp->declBus(c+8441,"VX_cache genblk5[3] bank qual_wsel_st0", false,-1, 1,0); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank qual_is_mrvq_st0", false,-1); + vcdp->declBus(c+8449,"VX_cache genblk5[3] bank qual_writeword_st0", false,-1, 31,0); + vcdp->declArray(c+8457,"VX_cache genblk5[3] bank qual_writedata_st0", false,-1, 127,0); + vcdp->declQuad(c+8489,"VX_cache genblk5[3] bank qual_inst_meta_st0", false,-1, 48,0); + vcdp->declBit(c+8505,"VX_cache genblk5[3] bank qual_going_to_write_st0", false,-1); + vcdp->declBit(c+8513,"VX_cache genblk5[3] bank qual_is_snp_st0", false,-1); + vcdp->declBit(c+8521,"VX_cache genblk5[3] bank qual_snp_invalidate_st0", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+10401+i*1,"VX_cache genblk5[3] bank valid_st1", true,(i+0));}} + vcdp->declBit(c+8529+i*1,"VX_cache genblk5[3] bank valid_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+10409+i*1,"VX_cache genblk5[3] bank addr_st1", true,(i+0), 24,0);}} + vcdp->declBus(c+8537+i*1,"VX_cache genblk5[3] bank addr_st1", true,(i+0), 25,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+10417+i*1,"VX_cache genblk5[3] bank wsel_st1", true,(i+0), 1,0);}} + vcdp->declBus(c+8545+i*1,"VX_cache genblk5[3] bank wsel_st1", true,(i+0), 1,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+10425+i*1,"VX_cache genblk5[3] bank writeword_st1", true,(i+0), 31,0);}} + vcdp->declBus(c+8553+i*1,"VX_cache genblk5[3] bank writeword_st1", true,(i+0), 31,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+10433+i*2,"VX_cache genblk5[3] bank inst_meta_st1", true,(i+0), 48,0);}} + vcdp->declQuad(c+8561+i*2,"VX_cache genblk5[3] bank inst_meta_st1", true,(i+0), 48,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+10449+i*4,"VX_cache genblk5[3] bank writedata_st1", true,(i+0), 127,0);}} + vcdp->declArray(c+8577+i*4,"VX_cache genblk5[3] bank writedata_st1", true,(i+0), 127,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+10481+i*1,"VX_cache genblk5[3] bank is_snp_st1", true,(i+0));}} + vcdp->declBit(c+8609+i*1,"VX_cache genblk5[3] bank is_snp_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+10489+i*1,"VX_cache genblk5[3] bank snp_invalidate_st1", true,(i+0));}} + vcdp->declBit(c+8617+i*1,"VX_cache genblk5[3] bank snp_invalidate_st1", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+10497+i*1,"VX_cache genblk5[3] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+10505,"VX_cache genblk5[3] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+10513,"VX_cache genblk5[3] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+10545,"VX_cache genblk5[3] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+10553,"VX_cache genblk5[3] bank miss_st1e", false,-1); - vcdp->declBit(c+10561,"VX_cache genblk5[3] bank dirty_st1e", false,-1); - vcdp->declBus(c+10569,"VX_cache genblk5[3] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+10577,"VX_cache genblk5[3] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+10593,"VX_cache genblk5[3] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+10601,"VX_cache genblk5[3] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+10609,"VX_cache genblk5[3] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+10617,"VX_cache genblk5[3] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+10625,"VX_cache genblk5[3] bank is_snp_st1e", false,-1); - vcdp->declBit(c+10633,"VX_cache genblk5[3] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+10641,"VX_cache genblk5[3] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+10649,"VX_cache genblk5[3] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+10657,"VX_cache genblk5[3] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+10665,"VX_cache genblk5[3] bank valid_st1e", false,-1); - vcdp->declBit(c+10673,"VX_cache genblk5[3] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+10681,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+10689,"VX_cache genblk5[3] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+10697,"VX_cache genblk5[3] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+10673,"VX_cache genblk5[3] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+35001,"VX_cache genblk5[3] bank valid_st2", false,-1); - vcdp->declBus(c+35009,"VX_cache genblk5[3] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+35017,"VX_cache genblk5[3] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+35025,"VX_cache genblk5[3] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+35033,"VX_cache genblk5[3] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+35065,"VX_cache genblk5[3] bank miss_st2", false,-1); - vcdp->declBit(c+35073,"VX_cache genblk5[3] bank dirty_st2", false,-1); - vcdp->declBus(c+35081,"VX_cache genblk5[3] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+35089,"VX_cache genblk5[3] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+35105,"VX_cache genblk5[3] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+35113,"VX_cache genblk5[3] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+35121,"VX_cache genblk5[3] bank is_snp_st2", false,-1); - vcdp->declBit(c+35129,"VX_cache genblk5[3] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+35137,"VX_cache genblk5[3] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+35145,"VX_cache genblk5[3] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+10705,"VX_cache genblk5[3] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+35153,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+35161,"VX_cache genblk5[3] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+10713,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+10721,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+35137,"VX_cache genblk5[3] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+10729,"VX_cache genblk5[3] bank miss_add_unqual", false,-1); - vcdp->declBit(c+10737,"VX_cache genblk5[3] bank miss_add", false,-1); - vcdp->declBus(c+19793,"VX_cache genblk5[3] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+35009,"VX_cache genblk5[3] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+35017,"VX_cache genblk5[3] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+35121,"VX_cache genblk5[3] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+35129,"VX_cache genblk5[3] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+10745,"VX_cache genblk5[3] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+10753,"VX_cache genblk5[3] bank cwbq_push", false,-1); - vcdp->declBit(c+1961,"VX_cache genblk5[3] bank cwbq_pop", false,-1); - vcdp->declBit(c+35169,"VX_cache genblk5[3] bank cwbq_empty", false,-1); - vcdp->declBit(c+35177,"VX_cache genblk5[3] bank cwbq_full", false,-1); - vcdp->declBit(c+10761,"VX_cache genblk5[3] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+35025,"VX_cache genblk5[3] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+34953,"VX_cache genblk5[3] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+34961,"VX_cache genblk5[3] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+10729,"VX_cache genblk5[3] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+10769,"VX_cache genblk5[3] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+10777,"VX_cache genblk5[3] bank dwbq_push", false,-1); - vcdp->declBit(c+1969,"VX_cache genblk5[3] bank dwbq_pop", false,-1); - vcdp->declBit(c+35185,"VX_cache genblk5[3] bank dwbq_empty", false,-1); - vcdp->declBit(c+35193,"VX_cache genblk5[3] bank dwbq_full", false,-1); - vcdp->declBit(c+10785,"VX_cache genblk5[3] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+10793,"VX_cache genblk5[3] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+10801,"VX_cache genblk5[3] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+10809,"VX_cache genblk5[3] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+10817,"VX_cache genblk5[3] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+35201,"VX_cache genblk5[3] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+35209,"VX_cache genblk5[3] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+889,"VX_cache genblk5[3] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+897,"VX_cache genblk5[3] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+35217,"VX_cache genblk5[3] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[3] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58553,"VX_cache genblk5[3] bank snp_req_queue push", false,-1); - vcdp->declBit(c+10009,"VX_cache genblk5[3] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+905,"VX_cache genblk5[3] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+10825,"VX_cache genblk5[3] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+34809,"VX_cache genblk5[3] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+34817,"VX_cache genblk5[3] bank snp_req_queue full", false,-1); - vcdp->declBus(c+35225,"VX_cache genblk5[3] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+35225,"VX_cache genblk5[3] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+10841,"VX_cache genblk5[3] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+921,"VX_cache genblk5[3] bank snp_req_queue writing", false,-1); + vcdp->declBit(c+8625+i*1,"VX_cache genblk5[3] bank is_mrvq_st1", true,(i+0));}} + vcdp->declBus(c+8633,"VX_cache genblk5[3] bank readword_st1e", false,-1, 31,0); + vcdp->declArray(c+8641,"VX_cache genblk5[3] bank readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+8673,"VX_cache genblk5[3] bank readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank miss_st1e", false,-1); + vcdp->declBit(c+8689,"VX_cache genblk5[3] bank dirty_st1e", false,-1); + vcdp->declBus(c+8697,"VX_cache genblk5[3] bank dirtyb_st1e", false,-1, 15,0); + vcdp->declQuad(c+8705,"VX_cache genblk5[3] bank tag_st1e", false,-1, 41,0); + vcdp->declBus(c+8721,"VX_cache genblk5[3] bank tid_st1e", false,-1, 1,0); + vcdp->declBit(c+8729,"VX_cache genblk5[3] bank mem_rw_st1e", false,-1); + vcdp->declBus(c+8737,"VX_cache genblk5[3] bank mem_byteen_st1e", false,-1, 3,0); + vcdp->declBit(c+8745,"VX_cache genblk5[3] bank fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+8753,"VX_cache genblk5[3] bank is_snp_st1e", false,-1); + vcdp->declBit(c+8761,"VX_cache genblk5[3] bank snp_invalidate_st1e", false,-1); + vcdp->declBit(c+8769,"VX_cache genblk5[3] bank snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+8777,"VX_cache genblk5[3] bank mrvq_init_ready_state_st1e", false,-1); + vcdp->declBit(c+8785,"VX_cache genblk5[3] bank miss_add_because_miss", false,-1); + vcdp->declBit(c+8793,"VX_cache genblk5[3] bank valid_st1e", false,-1); + vcdp->declBit(c+8801,"VX_cache genblk5[3] bank is_mrvq_st1e", false,-1); + vcdp->declBit(c+8809,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st1e", false,-1); + vcdp->declBus(c+8817,"VX_cache genblk5[3] bank addr_st1e", false,-1, 25,0); + vcdp->declBit(c+8825,"VX_cache genblk5[3] bank qual_valid_st1e_2", false,-1); + vcdp->declBit(c+8801,"VX_cache genblk5[3] bank is_mrvq_st1e_st2", false,-1); + vcdp->declBit(c+21209,"VX_cache genblk5[3] bank valid_st2", false,-1); + vcdp->declBus(c+21217,"VX_cache genblk5[3] bank wsel_st2", false,-1, 1,0); + vcdp->declBus(c+21225,"VX_cache genblk5[3] bank writeword_st2", false,-1, 31,0); + vcdp->declBus(c+21233,"VX_cache genblk5[3] bank readword_st2", false,-1, 31,0); + vcdp->declArray(c+21241,"VX_cache genblk5[3] bank readdata_st2", false,-1, 127,0); + vcdp->declBit(c+21273,"VX_cache genblk5[3] bank miss_st2", false,-1); + vcdp->declBit(c+21281,"VX_cache genblk5[3] bank dirty_st2", false,-1); + vcdp->declBus(c+21289,"VX_cache genblk5[3] bank dirtyb_st2", false,-1, 15,0); + vcdp->declQuad(c+21297,"VX_cache genblk5[3] bank inst_meta_st2", false,-1, 48,0); + vcdp->declBus(c+21313,"VX_cache genblk5[3] bank readtag_st2", false,-1, 19,0); + vcdp->declBit(c+21321,"VX_cache genblk5[3] bank fill_saw_dirty_st2", false,-1); + vcdp->declBit(c+21329,"VX_cache genblk5[3] bank is_snp_st2", false,-1); + vcdp->declBit(c+21337,"VX_cache genblk5[3] bank snp_invalidate_st2", false,-1); + vcdp->declBit(c+21345,"VX_cache genblk5[3] bank snp_to_mrvq_st2", false,-1); + vcdp->declBit(c+21353,"VX_cache genblk5[3] bank is_mrvq_st2", false,-1); + vcdp->declBit(c+8833,"VX_cache genblk5[3] bank mrvq_init_ready_state_st2", false,-1); + vcdp->declBit(c+21361,"VX_cache genblk5[3] bank mrvq_recover_ready_state_st2", false,-1); + vcdp->declBit(c+21369,"VX_cache genblk5[3] bank mrvq_init_ready_state_unqual_st2", false,-1); + vcdp->declBit(c+8841,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); + vcdp->declBit(c+8849,"VX_cache genblk5[3] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); + vcdp->declBit(c+21345,"VX_cache genblk5[3] bank miss_add_because_pending", false,-1); + vcdp->declBit(c+8857,"VX_cache genblk5[3] bank miss_add_unqual", false,-1); + vcdp->declBit(c+8865,"VX_cache genblk5[3] bank miss_add", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+21217,"VX_cache genblk5[3] bank miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+21225,"VX_cache genblk5[3] bank miss_add_data", false,-1, 31,0); + vcdp->declBit(c+21329,"VX_cache genblk5[3] bank miss_add_is_snp", false,-1); + vcdp->declBit(c+21337,"VX_cache genblk5[3] bank miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+8873,"VX_cache genblk5[3] bank miss_add_is_mrvq", false,-1); + vcdp->declBit(c+8881,"VX_cache genblk5[3] bank cwbq_push", false,-1); + vcdp->declBit(c+1065,"VX_cache genblk5[3] bank cwbq_pop", false,-1); + vcdp->declBit(c+21377,"VX_cache genblk5[3] bank cwbq_empty", false,-1); + vcdp->declBit(c+21385,"VX_cache genblk5[3] bank cwbq_full", false,-1); + vcdp->declBit(c+8889,"VX_cache genblk5[3] bank cwbq_push_unqual", false,-1); + vcdp->declBus(c+21233,"VX_cache genblk5[3] bank cwbq_data", false,-1, 31,0); + vcdp->declBus(c+21161,"VX_cache genblk5[3] bank cwbq_tid", false,-1, 1,0); + vcdp->declQuad(c+21169,"VX_cache genblk5[3] bank cwbq_tag", false,-1, 41,0); + vcdp->declBit(c+8857,"VX_cache genblk5[3] bank dram_fill_req_fast", false,-1); + vcdp->declBit(c+8897,"VX_cache genblk5[3] bank dram_fill_req_unqual", false,-1); + vcdp->declBit(c+8905,"VX_cache genblk5[3] bank dwbq_push", false,-1); + vcdp->declBit(c+1073,"VX_cache genblk5[3] bank dwbq_pop", false,-1); + vcdp->declBit(c+21393,"VX_cache genblk5[3] bank dwbq_empty", false,-1); + vcdp->declBit(c+21401,"VX_cache genblk5[3] bank dwbq_full", false,-1); + vcdp->declBit(c+8913,"VX_cache genblk5[3] bank dwbq_is_dwb_in", false,-1); + vcdp->declBit(c+8921,"VX_cache genblk5[3] bank dwbq_is_snp_in", false,-1); + vcdp->declBit(c+8929,"VX_cache genblk5[3] bank dwbq_is_dwb_out", false,-1); + vcdp->declBit(c+8937,"VX_cache genblk5[3] bank dwbq_is_snp_out", false,-1); + vcdp->declBit(c+8945,"VX_cache genblk5[3] bank dwbq_push_unqual", false,-1); + vcdp->declBus(c+21409,"VX_cache genblk5[3] bank dwbq_req_addr", false,-1, 25,0); + vcdp->declBus(c+21417,"VX_cache genblk5[3] bank snrq_tag_st2", false,-1, 27,0); + vcdp->declBit(c+761,"VX_cache genblk5[3] bank dram_wb_req_fire", false,-1); + vcdp->declBit(c+769,"VX_cache genblk5[3] bank snp_rsp_fire", false,-1); + vcdp->declBit(c+21425,"VX_cache genblk5[3] bank dwbq_dual_valid_sel", false,-1); + vcdp->declBus(c+25169,"VX_cache genblk5[3] bank snp_req_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank snp_req_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank snp_req_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank snp_req_queue reset", false,-1); + vcdp->declBit(c+25033,"VX_cache genblk5[3] bank snp_req_queue push", false,-1); + vcdp->declBit(c+8137,"VX_cache genblk5[3] bank snp_req_queue pop", false,-1); + vcdp->declQuad(c+777,"VX_cache genblk5[3] bank snp_req_queue data_in", false,-1, 54,0); + vcdp->declQuad(c+8953,"VX_cache genblk5[3] bank snp_req_queue data_out", false,-1, 54,0); + vcdp->declBit(c+21017,"VX_cache genblk5[3] bank snp_req_queue empty", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[3] bank snp_req_queue full", false,-1); + vcdp->declBus(c+21433,"VX_cache genblk5[3] bank snp_req_queue size", false,-1, 4,0); + vcdp->declBus(c+21433,"VX_cache genblk5[3] bank snp_req_queue size_r", false,-1, 4,0); + vcdp->declBit(c+8969,"VX_cache genblk5[3] bank snp_req_queue reading", false,-1); + vcdp->declBit(c+793,"VX_cache genblk5[3] bank snp_req_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+35233+i*2,"VX_cache genblk5[3] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+35489,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+35505,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+35521,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+35529,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+35537,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+34809,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+34817,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+35545,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[3] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58545,"VX_cache genblk5[3] bank dfp_queue push", false,-1); - vcdp->declBit(c+10041,"VX_cache genblk5[3] bank dfp_queue pop", false,-1); - vcdp->declArray(c+929,"VX_cache genblk5[3] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+10849,"VX_cache genblk5[3] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+34825,"VX_cache genblk5[3] bank dfp_queue empty", false,-1); - vcdp->declBit(c+34833,"VX_cache genblk5[3] bank dfp_queue full", false,-1); - vcdp->declBus(c+35553,"VX_cache genblk5[3] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+35553,"VX_cache genblk5[3] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+10889,"VX_cache genblk5[3] bank dfp_queue reading", false,-1); - vcdp->declBit(c+969,"VX_cache genblk5[3] bank dfp_queue writing", false,-1); + vcdp->declQuad(c+21441+i*2,"VX_cache genblk5[3] bank snp_req_queue genblk3 data", true,(i+0), 54,0);}} + vcdp->declQuad(c+21697,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 54,0); + vcdp->declQuad(c+21713,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 54,0); + vcdp->declBus(c+21729,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+21737,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+21745,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+21017,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21025,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+21753,"VX_cache genblk5[3] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25177,"VX_cache genblk5[3] bank dfp_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank dfp_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank dfp_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank dfp_queue reset", false,-1); + vcdp->declBit(c+25025,"VX_cache genblk5[3] bank dfp_queue push", false,-1); + vcdp->declBit(c+8169,"VX_cache genblk5[3] bank dfp_queue pop", false,-1); + vcdp->declArray(c+801,"VX_cache genblk5[3] bank dfp_queue data_in", false,-1, 153,0); + vcdp->declArray(c+8977,"VX_cache genblk5[3] bank dfp_queue data_out", false,-1, 153,0); + vcdp->declBit(c+21033,"VX_cache genblk5[3] bank dfp_queue empty", false,-1); + vcdp->declBit(c+21041,"VX_cache genblk5[3] bank dfp_queue full", false,-1); + vcdp->declBus(c+21761,"VX_cache genblk5[3] bank dfp_queue size", false,-1, 4,0); + vcdp->declBus(c+21761,"VX_cache genblk5[3] bank dfp_queue size_r", false,-1, 4,0); + vcdp->declBit(c+9017,"VX_cache genblk5[3] bank dfp_queue reading", false,-1); + vcdp->declBit(c+841,"VX_cache genblk5[3] bank dfp_queue writing", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+35561+i*5,"VX_cache genblk5[3] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+36201,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+36241,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+36281,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+36289,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+36297,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+34825,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+34833,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+36305,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank core_req_arb reset", false,-1); - vcdp->declBit(c+1953,"VX_cache genblk5[3] bank core_req_arb reqq_push", false,-1); + vcdp->declArray(c+21769+i*5,"VX_cache genblk5[3] bank dfp_queue genblk3 data", true,(i+0), 153,0);}} + vcdp->declArray(c+22409,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 head_r", false,-1, 153,0); + vcdp->declArray(c+22449,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 153,0); + vcdp->declBus(c+22489,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); + vcdp->declBus(c+22497,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); + vcdp->declBus(c+22505,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); + vcdp->declBit(c+21033,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21041,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+22513,"VX_cache genblk5[3] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb CREQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25105,"VX_cache genblk5[3] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank core_req_arb clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank core_req_arb reset", false,-1); + vcdp->declBit(c+1057,"VX_cache genblk5[3] bank core_req_arb reqq_push", false,-1); vcdp->declBus(c+129,"VX_cache genblk5[3] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[3] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[3] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[3] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[3] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[3] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+10089,"VX_cache genblk5[3] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+10121,"VX_cache genblk5[3] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+10129,"VX_cache genblk5[3] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+10137,"VX_cache genblk5[3] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+10145,"VX_cache genblk5[3] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+10097,"VX_cache genblk5[3] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+34841,"VX_cache genblk5[3] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+10897,"VX_cache genblk5[3] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+10905,"VX_cache genblk5[3] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+10913,"VX_cache genblk5[3] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+10921,"VX_cache genblk5[3] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+10953,"VX_cache genblk5[3] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+10985,"VX_cache genblk5[3] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+36321,"VX_cache genblk5[3] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+36329,"VX_cache genblk5[3] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+36337,"VX_cache genblk5[3] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+36369,"VX_cache genblk5[3] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+36321,"VX_cache genblk5[3] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+36329,"VX_cache genblk5[3] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+36337,"VX_cache genblk5[3] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+36369,"VX_cache genblk5[3] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+34849,"VX_cache genblk5[3] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+36401,"VX_cache genblk5[3] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+36409,"VX_cache genblk5[3] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+11001,"VX_cache genblk5[3] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+1977,"VX_cache genblk5[3] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+11009,"VX_cache genblk5[3] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+11017,"VX_cache genblk5[3] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[3] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+1977,"VX_cache genblk5[3] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+11009,"VX_cache genblk5[3] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+977,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+11025,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+36401,"VX_cache genblk5[3] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+34841,"VX_cache genblk5[3] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+36417,"VX_cache genblk5[3] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+36417,"VX_cache genblk5[3] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+11105,"VX_cache genblk5[3] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+1057,"VX_cache genblk5[3] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+36425+i*10,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+37065,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+37145,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+37225,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+37233,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+37241,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+36401,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+34841,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+37249,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+11113,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+11113,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+36313,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+10113,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+10105,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+11121,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[3] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[3] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+10241,"VX_cache genblk5[3] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[3] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+11129,"VX_cache genblk5[3] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+37257,"VX_cache genblk5[3] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+37257,"VX_cache genblk5[3] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[3] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank tag_data_access reset", false,-1); - vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access stall", false,-1); - vcdp->declBit(c+10625,"VX_cache genblk5[3] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+10633,"VX_cache genblk5[3] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+10193,"VX_cache genblk5[3] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+10689,"VX_cache genblk5[3] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+10665,"VX_cache genblk5[3] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+11201,"VX_cache genblk5[3] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+11209,"VX_cache genblk5[3] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+11217,"VX_cache genblk5[3] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+10601,"VX_cache genblk5[3] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+10609,"VX_cache genblk5[3] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+11249,"VX_cache genblk5[3] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+10505,"VX_cache genblk5[3] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+10513,"VX_cache genblk5[3] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+10545,"VX_cache genblk5[3] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+10553,"VX_cache genblk5[3] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+10561,"VX_cache genblk5[3] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+10569,"VX_cache genblk5[3] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+10617,"VX_cache genblk5[3] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+10641,"VX_cache genblk5[3] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+10649,"VX_cache genblk5[3] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+11257+i*1,"VX_cache genblk5[3] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+11265+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+11273+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+11281+i*1,"VX_cache genblk5[3] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+11289+i*4,"VX_cache genblk5[3] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+11321,"VX_cache genblk5[3] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+11329,"VX_cache genblk5[3] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+11337,"VX_cache genblk5[3] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+11345,"VX_cache genblk5[3] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+11353,"VX_cache genblk5[3] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+11385,"VX_cache genblk5[3] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+11393,"VX_cache genblk5[3] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+10569,"VX_cache genblk5[3] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+10545,"VX_cache genblk5[3] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+10513,"VX_cache genblk5[3] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+11401,"VX_cache genblk5[3] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+11409,"VX_cache genblk5[3] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+10553,"VX_cache genblk5[3] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+11441,"VX_cache genblk5[3] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+11449,"VX_cache genblk5[3] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+11457,"VX_cache genblk5[3] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+11465,"VX_cache genblk5[3] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+11473,"VX_cache genblk5[3] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+11409,"VX_cache genblk5[3] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+11481,"VX_cache genblk5[3] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+11441,"VX_cache genblk5[3] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+11489,"VX_cache genblk5[3] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+11497,"VX_cache genblk5[3] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+11505,"VX_cache genblk5[3] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+11513,"VX_cache genblk5[3] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+11521,"VX_cache genblk5[3] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+11529,"VX_cache genblk5[3] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+11537,"VX_cache genblk5[3] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+11545,"VX_cache genblk5[3] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[3] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+11321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+11329,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+11337,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+11345,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+11353,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+11441,"VX_cache genblk5[3] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+11401,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+11457,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+11193,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+11465,"VX_cache genblk5[3] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+11409,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+10553,"VX_cache genblk5[3] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+37321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+37353,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+37385,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+37417,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+37449,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+37481,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+37513,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+37545,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+37577,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+37609,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+37641,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+37673,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+37705,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+37737,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+37769,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+37801,"VX_cache genblk5[3] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+37833+i*1,"VX_cache genblk5[3] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+37961,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+37969,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+37977,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+37985,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+37993,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+38001,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+38009,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+38017,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+38025,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+38033,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+38041,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+38049,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+38057,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+38065,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+38073,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+38081,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+38089,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+38097,"VX_cache genblk5[3] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+11553,"VX_cache genblk5[3] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+38105,"VX_cache genblk5[3] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+38113,"VX_cache genblk5[3] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+10241,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+11561,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+11561,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+38121,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[3] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[3] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+10241,"VX_cache genblk5[3] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[3] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+11609,"VX_cache genblk5[3] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+38169,"VX_cache genblk5[3] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+38169,"VX_cache genblk5[3] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[3] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58833,"VX_cache genblk5[3] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[3] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[3] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[3] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+10737,"VX_cache genblk5[3] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+10745,"VX_cache genblk5[3] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19793,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+35009,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+35017,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+34953,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+34961,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+34977,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+34985,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+10705,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+35121,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+35129,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+34865,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+34873,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+11201,"VX_cache genblk5[3] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+10689,"VX_cache genblk5[3] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+10177,"VX_cache genblk5[3] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+10153,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+10161,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+34889,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+34897,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+34905,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+34881,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+34913,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+10169,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+34929,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+34937,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+34945,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+38249+i*3,"VX_cache genblk5[3] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+38633,"VX_cache genblk5[3] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+38737,"VX_cache genblk5[3] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+38745,"VX_cache genblk5[3] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+38753,"VX_cache genblk5[3] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+38761,"VX_cache genblk5[3] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+38769,"VX_cache genblk5[3] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+38777,"VX_cache genblk5[3] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+38785,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+38769,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+11689,"VX_cache genblk5[3] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+11697,"VX_cache genblk5[3] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+11705,"VX_cache genblk5[3] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+10161,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+38753,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+11713,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+11721,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+11729,"VX_cache genblk5[3] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+11737,"VX_cache genblk5[3] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+11745,"VX_cache genblk5[3] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+11753,"VX_cache genblk5[3] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[3] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[3] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank cwb_queue reset", false,-1); - vcdp->declBit(c+10753,"VX_cache genblk5[3] bank cwb_queue push", false,-1); - vcdp->declBit(c+1961,"VX_cache genblk5[3] bank cwb_queue pop", false,-1); - vcdp->declArray(c+11761,"VX_cache genblk5[3] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+11785,"VX_cache genblk5[3] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+35169,"VX_cache genblk5[3] bank cwb_queue empty", false,-1); - vcdp->declBit(c+35177,"VX_cache genblk5[3] bank cwb_queue full", false,-1); - vcdp->declBus(c+38793,"VX_cache genblk5[3] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+38793,"VX_cache genblk5[3] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+1065,"VX_cache genblk5[3] bank cwb_queue reading", false,-1); - vcdp->declBit(c+11809,"VX_cache genblk5[3] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+38801+i*3,"VX_cache genblk5[3] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+38993,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+39017,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+39041,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+39049,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+39057,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+35169,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+35177,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+39065,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[3] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[3] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[3] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[3] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[3] bank dwb_queue reset", false,-1); - vcdp->declBit(c+10777,"VX_cache genblk5[3] bank dwb_queue push", false,-1); - vcdp->declBit(c+1969,"VX_cache genblk5[3] bank dwb_queue pop", false,-1); - vcdp->declArray(c+11817,"VX_cache genblk5[3] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+11873,"VX_cache genblk5[3] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+35185,"VX_cache genblk5[3] bank dwb_queue empty", false,-1); - vcdp->declBit(c+35193,"VX_cache genblk5[3] bank dwb_queue full", false,-1); - vcdp->declBus(c+39073,"VX_cache genblk5[3] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+39073,"VX_cache genblk5[3] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+1073,"VX_cache genblk5[3] bank dwb_queue reading", false,-1); - vcdp->declBit(c+11929,"VX_cache genblk5[3] bank dwb_queue writing", false,-1); + vcdp->declBus(c+24513,"VX_cache genblk5[3] bank core_req_arb bank_rw", false,-1, 3,0); + vcdp->declBus(c+24521,"VX_cache genblk5[3] bank core_req_arb bank_byteen", false,-1, 15,0); + vcdp->declArray(c+24561,"VX_cache genblk5[3] bank core_req_arb bank_writedata", false,-1, 127,0); + vcdp->declArray(c+24529,"VX_cache genblk5[3] bank core_req_arb bank_addr", false,-1, 119,0); + vcdp->declQuad(c+24593,"VX_cache genblk5[3] bank core_req_arb bank_tag", false,-1, 41,0); + vcdp->declBit(c+8217,"VX_cache genblk5[3] bank core_req_arb reqq_pop", false,-1); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb reqq_req_st0", false,-1); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); + vcdp->declBit(c+8249,"VX_cache genblk5[3] bank core_req_arb reqq_req_rw_st0", false,-1); + vcdp->declBus(c+8257,"VX_cache genblk5[3] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); + vcdp->declBus(c+8265,"VX_cache genblk5[3] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); + vcdp->declBus(c+8273,"VX_cache genblk5[3] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8225,"VX_cache genblk5[3] bank core_req_arb reqq_empty", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank core_req_arb reqq_full", false,-1); + vcdp->declBus(c+9025,"VX_cache genblk5[3] bank core_req_arb out_per_valids", false,-1, 3,0); + vcdp->declBus(c+9033,"VX_cache genblk5[3] bank core_req_arb out_per_rw", false,-1, 3,0); + vcdp->declBus(c+9041,"VX_cache genblk5[3] bank core_req_arb out_per_byteen", false,-1, 15,0); + vcdp->declArray(c+9049,"VX_cache genblk5[3] bank core_req_arb out_per_addr", false,-1, 119,0); + vcdp->declArray(c+9081,"VX_cache genblk5[3] bank core_req_arb out_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+9113,"VX_cache genblk5[3] bank core_req_arb out_per_tag", false,-1, 41,0); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb use_per_valids", false,-1, 3,0); + vcdp->declBus(c+22529,"VX_cache genblk5[3] bank core_req_arb use_per_rw", false,-1, 3,0); + vcdp->declBus(c+22537,"VX_cache genblk5[3] bank core_req_arb use_per_byteen", false,-1, 15,0); + vcdp->declArray(c+22545,"VX_cache genblk5[3] bank core_req_arb use_per_addr", false,-1, 119,0); + vcdp->declArray(c+22577,"VX_cache genblk5[3] bank core_req_arb use_per_writedata", false,-1, 127,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank core_req_arb use_per_tag", false,-1, 41,0); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb qual_valids", false,-1, 3,0); + vcdp->declBus(c+22529,"VX_cache genblk5[3] bank core_req_arb qual_rw", false,-1, 3,0); + vcdp->declBus(c+22537,"VX_cache genblk5[3] bank core_req_arb qual_byteen", false,-1, 15,0); + vcdp->declArray(c+22545,"VX_cache genblk5[3] bank core_req_arb qual_addr", false,-1, 119,0); + vcdp->declArray(c+22577,"VX_cache genblk5[3] bank core_req_arb qual_writedata", false,-1, 127,0); + vcdp->declQuad(c+21057,"VX_cache genblk5[3] bank core_req_arb qual_tag", false,-1, 41,0); + vcdp->declBit(c+22609,"VX_cache genblk5[3] bank core_req_arb o_empty", false,-1); + vcdp->declBit(c+22617,"VX_cache genblk5[3] bank core_req_arb use_empty", false,-1); + vcdp->declBit(c+9129,"VX_cache genblk5[3] bank core_req_arb out_empty", false,-1); + vcdp->declBit(c+1081,"VX_cache genblk5[3] bank core_req_arb push_qual", false,-1); + vcdp->declBit(c+9137,"VX_cache genblk5[3] bank core_req_arb pop_qual", false,-1); + vcdp->declBus(c+9145,"VX_cache genblk5[3] bank core_req_arb real_out_per_valids", false,-1, 3,0); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb qual_request_index", false,-1, 1,0); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb qual_has_request", false,-1); + vcdp->declBus(c+25185,"VX_cache genblk5[3] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank core_req_arb reqq_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank core_req_arb reqq_queue reset", false,-1); + vcdp->declBit(c+1081,"VX_cache genblk5[3] bank core_req_arb reqq_queue push", false,-1); + vcdp->declBit(c+9137,"VX_cache genblk5[3] bank core_req_arb reqq_queue pop", false,-1); + vcdp->declArray(c+849,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_in", false,-1, 313,0); + vcdp->declArray(c+9153,"VX_cache genblk5[3] bank core_req_arb reqq_queue data_out", false,-1, 313,0); + vcdp->declBit(c+22609,"VX_cache genblk5[3] bank core_req_arb reqq_queue empty", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank core_req_arb reqq_queue full", false,-1); + vcdp->declBus(c+22625,"VX_cache genblk5[3] bank core_req_arb reqq_queue size", false,-1, 2,0); + vcdp->declBus(c+22625,"VX_cache genblk5[3] bank core_req_arb reqq_queue size_r", false,-1, 2,0); + vcdp->declBit(c+9233,"VX_cache genblk5[3] bank core_req_arb reqq_queue reading", false,-1); + vcdp->declBit(c+929,"VX_cache genblk5[3] bank core_req_arb reqq_queue writing", false,-1); {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+39081+i*7,"VX_cache genblk5[3] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+39305,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+39361,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+39417,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+39425,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+39433,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+35185,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+35193,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+39441,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58641,"VX_cache genblk5[4] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58713,"VX_cache genblk5[4] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[4] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[4] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[4] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[4] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank reset", false,-1); - vcdp->declBus(c+161,"VX_cache genblk5[4] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[4] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[4] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[4] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[4] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[4] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19849,"VX_cache genblk5[4] bank core_req_ready", false,-1); - vcdp->declBit(c+19817,"VX_cache genblk5[4] bank core_rsp_valid", false,-1); - vcdp->declBus(c+3233,"VX_cache genblk5[4] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3241,"VX_cache genblk5[4] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3249,"VX_cache genblk5[4] bank core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+169,"VX_cache genblk5[4] bank core_rsp_ready", false,-1); - vcdp->declBit(c+3265,"VX_cache genblk5[4] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19833,"VX_cache genblk5[4] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[4] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58561,"VX_cache genblk5[4] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[4] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[4] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19825,"VX_cache genblk5[4] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3273,"VX_cache genblk5[4] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+3281,"VX_cache genblk5[4] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3289,"VX_cache genblk5[4] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3297,"VX_cache genblk5[4] bank dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+177,"VX_cache genblk5[4] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58569,"VX_cache genblk5[4] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[4] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[4] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[4] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19841,"VX_cache genblk5[4] bank snp_req_ready", false,-1); - vcdp->declBit(c+3329,"VX_cache genblk5[4] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+3337,"VX_cache genblk5[4] bank snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+185,"VX_cache genblk5[4] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+11937,"VX_cache genblk5[4] bank snrq_pop", false,-1); - vcdp->declBit(c+39449,"VX_cache genblk5[4] bank snrq_empty", false,-1); - vcdp->declBit(c+39457,"VX_cache genblk5[4] bank snrq_full", false,-1); - vcdp->declBus(c+11945,"VX_cache genblk5[4] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+11953,"VX_cache genblk5[4] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+11961,"VX_cache genblk5[4] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+11969,"VX_cache genblk5[4] bank dfpq_pop", false,-1); - vcdp->declBit(c+39465,"VX_cache genblk5[4] bank dfpq_empty", false,-1); - vcdp->declBit(c+39473,"VX_cache genblk5[4] bank dfpq_full", false,-1); - vcdp->declBus(c+11977,"VX_cache genblk5[4] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+11985,"VX_cache genblk5[4] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+12017,"VX_cache genblk5[4] bank reqq_pop", false,-1); - vcdp->declBit(c+1985,"VX_cache genblk5[4] bank reqq_push", false,-1); - vcdp->declBit(c+12025,"VX_cache genblk5[4] bank reqq_empty", false,-1); - vcdp->declBit(c+39481,"VX_cache genblk5[4] bank reqq_full", false,-1); - vcdp->declBit(c+12033,"VX_cache genblk5[4] bank reqq_req_st0", false,-1); - vcdp->declBus(c+12041,"VX_cache genblk5[4] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+12049,"VX_cache genblk5[4] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+12057,"VX_cache genblk5[4] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+12065,"VX_cache genblk5[4] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+12073,"VX_cache genblk5[4] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+12081,"VX_cache genblk5[4] bank mrvq_pop", false,-1); - vcdp->declBit(c+39505,"VX_cache genblk5[4] bank mrvq_full", false,-1); - vcdp->declBit(c+39513,"VX_cache genblk5[4] bank mrvq_stop", false,-1); - vcdp->declBit(c+12089,"VX_cache genblk5[4] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+39521,"VX_cache genblk5[4] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+39529,"VX_cache genblk5[4] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+39537,"VX_cache genblk5[4] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+39545,"VX_cache genblk5[4] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+39553,"VX_cache genblk5[4] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+12097,"VX_cache genblk5[4] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+39569,"VX_cache genblk5[4] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+39577,"VX_cache genblk5[4] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+39585,"VX_cache genblk5[4] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+12105,"VX_cache genblk5[4] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+12113,"VX_cache genblk5[4] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+12121,"VX_cache genblk5[4] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+39593,"VX_cache genblk5[4] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+39601,"VX_cache genblk5[4] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+39617,"VX_cache genblk5[4] bank miss_add_rw", false,-1); - vcdp->declBus(c+39625,"VX_cache genblk5[4] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19833,"VX_cache genblk5[4] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+39633,"VX_cache genblk5[4] bank is_fill_st2", false,-1); - vcdp->declBit(c+12129,"VX_cache genblk5[4] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+12137,"VX_cache genblk5[4] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+12145,"VX_cache genblk5[4] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+12153,"VX_cache genblk5[4] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+12161,"VX_cache genblk5[4] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+12169,"VX_cache genblk5[4] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+12177,"VX_cache genblk5[4] bank is_fill_in_pipe", false,-1); + vcdp->declArray(c+22633+i*10,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} + vcdp->declArray(c+22953,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); + vcdp->declArray(c+23033,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); + vcdp->declBus(c+23113,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+23121,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+23129,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+22609,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21049,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+23137,"VX_cache genblk5[3] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb sel_bank N", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank core_req_arb sel_bank clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank core_req_arb sel_bank reset", false,-1); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb sel_bank requests", false,-1, 3,0); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+9241,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb sel_bank grant_valid", false,-1); + vcdp->declBus(c+9241,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); + vcdp->declBus(c+22521,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); + vcdp->declBus(c+8241,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+8233,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+9249,"VX_cache genblk5[3] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); + vcdp->declBus(c+25193,"VX_cache genblk5[3] bank s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank s0_1_c0 reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[3] bank s0_1_c0 flush", false,-1); + vcdp->declArray(c+9257,"VX_cache genblk5[3] bank s0_1_c0 in", false,-1, 242,0); + vcdp->declArray(c+23145,"VX_cache genblk5[3] bank s0_1_c0 out", false,-1, 242,0); + vcdp->declArray(c+23145,"VX_cache genblk5[3] bank s0_1_c0 value", false,-1, 242,0); + vcdp->declBus(c+25065,"VX_cache genblk5[3] bank tag_data_access CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank tag_data_access clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank tag_data_access reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access stall", false,-1); + vcdp->declBit(c+8753,"VX_cache genblk5[3] bank tag_data_access is_snp_st1e", false,-1); + vcdp->declBit(c+8761,"VX_cache genblk5[3] bank tag_data_access snp_invalidate_st1e", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access stall_bank_pipe", false,-1); + vcdp->declBit(c+8321,"VX_cache genblk5[3] bank tag_data_access force_request_miss_st1e", false,-1); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access readaddr_st10", false,-1, 5,0); + vcdp->declBus(c+8817,"VX_cache genblk5[3] bank tag_data_access writeaddr_st1e", false,-1, 25,0); + vcdp->declBit(c+8793,"VX_cache genblk5[3] bank tag_data_access valid_req_st1e", false,-1); + vcdp->declBit(c+9329,"VX_cache genblk5[3] bank tag_data_access writefill_st1e", false,-1); + vcdp->declBus(c+9337,"VX_cache genblk5[3] bank tag_data_access writeword_st1e", false,-1, 31,0); + vcdp->declArray(c+9345,"VX_cache genblk5[3] bank tag_data_access writedata_st1e", false,-1, 127,0); + vcdp->declBit(c+8729,"VX_cache genblk5[3] bank tag_data_access mem_rw_st1e", false,-1); + vcdp->declBus(c+8737,"VX_cache genblk5[3] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); + vcdp->declBus(c+9377,"VX_cache genblk5[3] bank tag_data_access wordsel_st1e", false,-1, 1,0); + vcdp->declBus(c+8633,"VX_cache genblk5[3] bank tag_data_access readword_st1e", false,-1, 31,0); + vcdp->declArray(c+8641,"VX_cache genblk5[3] bank tag_data_access readdata_st1e", false,-1, 127,0); + vcdp->declBus(c+8673,"VX_cache genblk5[3] bank tag_data_access readtag_st1e", false,-1, 19,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank tag_data_access miss_st1e", false,-1); + vcdp->declBit(c+8689,"VX_cache genblk5[3] bank tag_data_access dirty_st1e", false,-1); + vcdp->declBus(c+8697,"VX_cache genblk5[3] bank tag_data_access dirtyb_st1e", false,-1, 15,0); + vcdp->declBit(c+8745,"VX_cache genblk5[3] bank tag_data_access fill_saw_dirty_st1e", false,-1); + vcdp->declBit(c+8769,"VX_cache genblk5[3] bank tag_data_access snp_to_mrvq_st1e", false,-1); + vcdp->declBit(c+8777,"VX_cache genblk5[3] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+12185+i*1,"VX_cache genblk5[4] bank is_fill_st1", true,(i+0));}} + vcdp->declBit(c+9385+i*1,"VX_cache genblk5[3] bank tag_data_access read_valid_st1c", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+12193+i*1,"VX_cache genblk5[4] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[4] bank j", false,-1, 31,0); - vcdp->declBit(c+12089,"VX_cache genblk5[4] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+12201,"VX_cache genblk5[4] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+12209,"VX_cache genblk5[4] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+12217,"VX_cache genblk5[4] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+12201,"VX_cache genblk5[4] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+12225,"VX_cache genblk5[4] bank qual_valid_st0", false,-1); - vcdp->declBus(c+12233,"VX_cache genblk5[4] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+12241,"VX_cache genblk5[4] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+12089,"VX_cache genblk5[4] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+12249,"VX_cache genblk5[4] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+12257,"VX_cache genblk5[4] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+12289,"VX_cache genblk5[4] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+12305,"VX_cache genblk5[4] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+12313,"VX_cache genblk5[4] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+12321,"VX_cache genblk5[4] bank qual_snp_invalidate_st0", false,-1); + vcdp->declBit(c+9393+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirty_st1c", true,(i+0));}} {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+12329+i*1,"VX_cache genblk5[4] bank valid_st1", true,(i+0));}} + vcdp->declBus(c+9401+i*1,"VX_cache genblk5[3] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+12337+i*1,"VX_cache genblk5[4] bank addr_st1", true,(i+0), 24,0);}} + vcdp->declBus(c+9409+i*1,"VX_cache genblk5[3] bank tag_data_access read_tag_st1c", true,(i+0), 19,0);}} {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+12345+i*1,"VX_cache genblk5[4] bank wsel_st1", true,(i+0), 1,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+12353+i*1,"VX_cache genblk5[4] bank writeword_st1", true,(i+0), 31,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+12361+i*2,"VX_cache genblk5[4] bank inst_meta_st1", true,(i+0), 48,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+12377+i*4,"VX_cache genblk5[4] bank writedata_st1", true,(i+0), 127,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+12409+i*1,"VX_cache genblk5[4] bank is_snp_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+12417+i*1,"VX_cache genblk5[4] bank snp_invalidate_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+12425+i*1,"VX_cache genblk5[4] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+12433,"VX_cache genblk5[4] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+12441,"VX_cache genblk5[4] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+12473,"VX_cache genblk5[4] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+12481,"VX_cache genblk5[4] bank miss_st1e", false,-1); - vcdp->declBit(c+12489,"VX_cache genblk5[4] bank dirty_st1e", false,-1); - vcdp->declBus(c+12497,"VX_cache genblk5[4] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+12505,"VX_cache genblk5[4] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+12521,"VX_cache genblk5[4] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+12529,"VX_cache genblk5[4] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+12537,"VX_cache genblk5[4] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+12545,"VX_cache genblk5[4] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+12553,"VX_cache genblk5[4] bank is_snp_st1e", false,-1); - vcdp->declBit(c+12561,"VX_cache genblk5[4] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+12569,"VX_cache genblk5[4] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+12577,"VX_cache genblk5[4] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+12585,"VX_cache genblk5[4] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+12593,"VX_cache genblk5[4] bank valid_st1e", false,-1); - vcdp->declBit(c+12601,"VX_cache genblk5[4] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+12609,"VX_cache genblk5[4] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+12617,"VX_cache genblk5[4] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+12625,"VX_cache genblk5[4] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+12601,"VX_cache genblk5[4] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+39641,"VX_cache genblk5[4] bank valid_st2", false,-1); - vcdp->declBus(c+39649,"VX_cache genblk5[4] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+39657,"VX_cache genblk5[4] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+39665,"VX_cache genblk5[4] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+39673,"VX_cache genblk5[4] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+39705,"VX_cache genblk5[4] bank miss_st2", false,-1); - vcdp->declBit(c+39713,"VX_cache genblk5[4] bank dirty_st2", false,-1); - vcdp->declBus(c+39721,"VX_cache genblk5[4] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+39729,"VX_cache genblk5[4] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+39745,"VX_cache genblk5[4] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+39753,"VX_cache genblk5[4] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+39761,"VX_cache genblk5[4] bank is_snp_st2", false,-1); - vcdp->declBit(c+39769,"VX_cache genblk5[4] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+39777,"VX_cache genblk5[4] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+39785,"VX_cache genblk5[4] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+12633,"VX_cache genblk5[4] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+39793,"VX_cache genblk5[4] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+39801,"VX_cache genblk5[4] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+12641,"VX_cache genblk5[4] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+12649,"VX_cache genblk5[4] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+39777,"VX_cache genblk5[4] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+12657,"VX_cache genblk5[4] bank miss_add_unqual", false,-1); - vcdp->declBit(c+12665,"VX_cache genblk5[4] bank miss_add", false,-1); - vcdp->declBus(c+19833,"VX_cache genblk5[4] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+39649,"VX_cache genblk5[4] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+39657,"VX_cache genblk5[4] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+39761,"VX_cache genblk5[4] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+39769,"VX_cache genblk5[4] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+12673,"VX_cache genblk5[4] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+12681,"VX_cache genblk5[4] bank cwbq_push", false,-1); - vcdp->declBit(c+1993,"VX_cache genblk5[4] bank cwbq_pop", false,-1); - vcdp->declBit(c+39809,"VX_cache genblk5[4] bank cwbq_empty", false,-1); - vcdp->declBit(c+39817,"VX_cache genblk5[4] bank cwbq_full", false,-1); - vcdp->declBit(c+12689,"VX_cache genblk5[4] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+39665,"VX_cache genblk5[4] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+39593,"VX_cache genblk5[4] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+39601,"VX_cache genblk5[4] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+12657,"VX_cache genblk5[4] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+12697,"VX_cache genblk5[4] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+12705,"VX_cache genblk5[4] bank dwbq_push", false,-1); - vcdp->declBit(c+2001,"VX_cache genblk5[4] bank dwbq_pop", false,-1); - vcdp->declBit(c+39825,"VX_cache genblk5[4] bank dwbq_empty", false,-1); - vcdp->declBit(c+39833,"VX_cache genblk5[4] bank dwbq_full", false,-1); - vcdp->declBit(c+12713,"VX_cache genblk5[4] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+12721,"VX_cache genblk5[4] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+12729,"VX_cache genblk5[4] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+12737,"VX_cache genblk5[4] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+12745,"VX_cache genblk5[4] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+39841,"VX_cache genblk5[4] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+39849,"VX_cache genblk5[4] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+1081,"VX_cache genblk5[4] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+1089,"VX_cache genblk5[4] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+39857,"VX_cache genblk5[4] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[4] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58569,"VX_cache genblk5[4] bank snp_req_queue push", false,-1); - vcdp->declBit(c+11937,"VX_cache genblk5[4] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+1097,"VX_cache genblk5[4] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+12753,"VX_cache genblk5[4] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+39449,"VX_cache genblk5[4] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+39457,"VX_cache genblk5[4] bank snp_req_queue full", false,-1); - vcdp->declBus(c+39865,"VX_cache genblk5[4] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+39865,"VX_cache genblk5[4] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+12769,"VX_cache genblk5[4] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+1113,"VX_cache genblk5[4] bank snp_req_queue writing", false,-1); + vcdp->declArray(c+9417+i*4,"VX_cache genblk5[3] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} + vcdp->declBit(c+9449,"VX_cache genblk5[3] bank tag_data_access qual_read_valid_st1", false,-1); + vcdp->declBit(c+9457,"VX_cache genblk5[3] bank tag_data_access qual_read_dirty_st1", false,-1); + vcdp->declBus(c+9465,"VX_cache genblk5[3] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); + vcdp->declBus(c+9473,"VX_cache genblk5[3] bank tag_data_access qual_read_tag_st1", false,-1, 19,0); + vcdp->declArray(c+9481,"VX_cache genblk5[3] bank tag_data_access qual_read_data_st1", false,-1, 127,0); + vcdp->declBit(c+9513,"VX_cache genblk5[3] bank tag_data_access use_read_valid_st1e", false,-1); + vcdp->declBit(c+9521,"VX_cache genblk5[3] bank tag_data_access use_read_dirty_st1e", false,-1); + vcdp->declBus(c+8697,"VX_cache genblk5[3] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); + vcdp->declBus(c+8673,"VX_cache genblk5[3] bank tag_data_access use_read_tag_st1e", false,-1, 19,0); + vcdp->declArray(c+8641,"VX_cache genblk5[3] bank tag_data_access use_read_data_st1e", false,-1, 127,0); + vcdp->declBus(c+9529,"VX_cache genblk5[3] bank tag_data_access use_write_enable", false,-1, 15,0); + vcdp->declArray(c+9537,"VX_cache genblk5[3] bank tag_data_access use_write_data", false,-1, 127,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank tag_data_access fill_sent", false,-1); + vcdp->declBit(c+9569,"VX_cache genblk5[3] bank tag_data_access invalidate_line", false,-1); + vcdp->declBit(c+9577,"VX_cache genblk5[3] bank tag_data_access tags_match", false,-1); + vcdp->declBit(c+9585,"VX_cache genblk5[3] bank tag_data_access real_writefill", false,-1); + vcdp->declBus(c+9593,"VX_cache genblk5[3] bank tag_data_access writetag_st1e", false,-1, 19,0); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access writeladdr_st1e", false,-1, 5,0); + vcdp->declBus(c+9601,"VX_cache genblk5[3] bank tag_data_access we", false,-1, 15,0); + vcdp->declArray(c+9537,"VX_cache genblk5[3] bank tag_data_access data_write", false,-1, 127,0); + vcdp->declBit(c+9609,"VX_cache genblk5[3] bank tag_data_access should_write", false,-1); + vcdp->declBit(c+9569,"VX_cache genblk5[3] bank tag_data_access snoop_hit_no_pending", false,-1); + vcdp->declBit(c+9617,"VX_cache genblk5[3] bank tag_data_access req_invalid", false,-1); + vcdp->declBit(c+9625,"VX_cache genblk5[3] bank tag_data_access req_miss", false,-1); + vcdp->declBit(c+9633,"VX_cache genblk5[3] bank tag_data_access real_miss", false,-1); + vcdp->declBit(c+9641,"VX_cache genblk5[3] bank tag_data_access force_core_miss", false,-1); + vcdp->declBit(c+9649,"VX_cache genblk5[3] bank tag_data_access genblk4[0] normal_write", false,-1); + vcdp->declBit(c+9657,"VX_cache genblk5[3] bank tag_data_access genblk4[1] normal_write", false,-1); + vcdp->declBit(c+9665,"VX_cache genblk5[3] bank tag_data_access genblk4[2] normal_write", false,-1); + vcdp->declBit(c+9673,"VX_cache genblk5[3] bank tag_data_access genblk4[3] normal_write", false,-1); + vcdp->declBus(c+25065,"VX_cache genblk5[3] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank tag_data_access tag_data_structure clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank tag_data_access tag_data_structure reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_addr", false,-1, 5,0); + vcdp->declBit(c+9449,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_valid", false,-1); + vcdp->declBit(c+9457,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirty", false,-1); + vcdp->declBus(c+9465,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); + vcdp->declBus(c+9473,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_tag", false,-1, 19,0); + vcdp->declArray(c+9481,"VX_cache genblk5[3] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); + vcdp->declBit(c+9569,"VX_cache genblk5[3] bank tag_data_access tag_data_structure invalidate", false,-1); + vcdp->declBus(c+9529,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); + vcdp->declBit(c+9585,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_fill", false,-1); + vcdp->declBus(c+9321,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_addr", false,-1, 5,0); + vcdp->declBus(c+9593,"VX_cache genblk5[3] bank tag_data_access tag_data_structure tag_index", false,-1, 19,0); + vcdp->declArray(c+9537,"VX_cache genblk5[3] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); + vcdp->declBit(c+8681,"VX_cache genblk5[3] bank tag_data_access tag_data_structure fill_sent", false,-1); + vcdp->declQuad(c+23209,"VX_cache genblk5[3] bank tag_data_access tag_data_structure dirty", false,-1, 63,0); + vcdp->declQuad(c+23225,"VX_cache genblk5[3] bank tag_data_access tag_data_structure valid", false,-1, 63,0); + vcdp->declBit(c+9681,"VX_cache genblk5[3] bank tag_data_access tag_data_structure do_write", false,-1); + vcdp->declBus(c+23241,"VX_cache genblk5[3] bank tag_data_access tag_data_structure i", false,-1, 31,0); + vcdp->declBus(c+23249,"VX_cache genblk5[3] bank tag_data_access tag_data_structure j", false,-1, 31,0); + vcdp->declBus(c+25201,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 N", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 flush", false,-1); + vcdp->declArray(c+9689,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 in", false,-1, 165,0); + vcdp->declArray(c+9689,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 out", false,-1, 165,0); + vcdp->declArray(c+23257,"VX_cache genblk5[3] bank tag_data_access s0_1_c0 value", false,-1, 165,0); + vcdp->declBus(c+25209,"VX_cache genblk5[3] bank st_1e_2 N", false,-1, 31,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank st_1e_2 PASSTHRU", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank st_1e_2 clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank st_1e_2 reset", false,-1); + vcdp->declBit(c+8369,"VX_cache genblk5[3] bank st_1e_2 stall", false,-1); + vcdp->declBit(c+25137,"VX_cache genblk5[3] bank st_1e_2 flush", false,-1); + vcdp->declArray(c+9737,"VX_cache genblk5[3] bank st_1e_2 in", false,-1, 315,0); + vcdp->declArray(c+23305,"VX_cache genblk5[3] bank st_1e_2 out", false,-1, 315,0); + vcdp->declArray(c+23305,"VX_cache genblk5[3] bank st_1e_2 value", false,-1, 315,0); + vcdp->declBus(c+25057,"VX_cache genblk5[3] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); + vcdp->declBus(c+25241,"VX_cache genblk5[3] bank cache_miss_resrv BANK_ID", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); + vcdp->declBus(c+25073,"VX_cache genblk5[3] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); + vcdp->declBus(c+25097,"VX_cache genblk5[3] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); + vcdp->declBus(c+25113,"VX_cache genblk5[3] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank cache_miss_resrv clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank cache_miss_resrv reset", false,-1); + vcdp->declBit(c+8865,"VX_cache genblk5[3] bank cache_miss_resrv miss_add", false,-1); + vcdp->declBit(c+8873,"VX_cache genblk5[3] bank cache_miss_resrv is_mrvq", false,-1); + vcdp->declBus(c+10209,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_addr", false,-1, 25,0); + vcdp->declBus(c+21217,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); + vcdp->declBus(c+21225,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_data", false,-1, 31,0); + vcdp->declBus(c+21161,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); + vcdp->declQuad(c+21169,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); + vcdp->declBit(c+21185,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_rw", false,-1); + vcdp->declBus(c+21193,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); + vcdp->declBit(c+8833,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_init_ready_state", false,-1); + vcdp->declBit(c+21329,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_is_snp", false,-1); + vcdp->declBit(c+21337,"VX_cache genblk5[3] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); + vcdp->declBit(c+21073,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_full", false,-1); + vcdp->declBit(c+21081,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_stop", false,-1); + vcdp->declBit(c+9329,"VX_cache genblk5[3] bank cache_miss_resrv is_fill_st1", false,-1); + vcdp->declBus(c+8817,"VX_cache genblk5[3] bank cache_miss_resrv fill_addr_st1", false,-1, 25,0); + vcdp->declBit(c+8305,"VX_cache genblk5[3] bank cache_miss_resrv pending_hazard", false,-1); + vcdp->declBit(c+8281,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_pop", false,-1); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); + vcdp->declBus(c+21097,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 25,0); + vcdp->declBus(c+21105,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); + vcdp->declBus(c+21113,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); + vcdp->declBus(c+21089,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); + vcdp->declQuad(c+21121,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); + vcdp->declBit(c+8297,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); + vcdp->declBus(c+21137,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); + vcdp->declBit(c+21145,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); + vcdp->declBit(c+21153,"VX_cache genblk5[3] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+39873+i*2,"VX_cache genblk5[4] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+40129,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+40145,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+40161,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+40169,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+40177,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+39449,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+39457,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+40185,"VX_cache genblk5[4] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[4] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58561,"VX_cache genblk5[4] bank dfp_queue push", false,-1); - vcdp->declBit(c+11969,"VX_cache genblk5[4] bank dfp_queue pop", false,-1); - vcdp->declArray(c+1121,"VX_cache genblk5[4] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+12777,"VX_cache genblk5[4] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+39465,"VX_cache genblk5[4] bank dfp_queue empty", false,-1); - vcdp->declBit(c+39473,"VX_cache genblk5[4] bank dfp_queue full", false,-1); - vcdp->declBus(c+40193,"VX_cache genblk5[4] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+40193,"VX_cache genblk5[4] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+12817,"VX_cache genblk5[4] bank dfp_queue reading", false,-1); - vcdp->declBit(c+1161,"VX_cache genblk5[4] bank dfp_queue writing", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+40201+i*5,"VX_cache genblk5[4] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+40841,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+40881,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+40921,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+40929,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+40937,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+39465,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+39473,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+40945,"VX_cache genblk5[4] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[4] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank core_req_arb reset", false,-1); - vcdp->declBit(c+1985,"VX_cache genblk5[4] bank core_req_arb reqq_push", false,-1); - vcdp->declBus(c+161,"VX_cache genblk5[4] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[4] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[4] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[4] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[4] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[4] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+12017,"VX_cache genblk5[4] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+12049,"VX_cache genblk5[4] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+12057,"VX_cache genblk5[4] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+12065,"VX_cache genblk5[4] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+12073,"VX_cache genblk5[4] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+12025,"VX_cache genblk5[4] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+39481,"VX_cache genblk5[4] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+12825,"VX_cache genblk5[4] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+12833,"VX_cache genblk5[4] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+12841,"VX_cache genblk5[4] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+12849,"VX_cache genblk5[4] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+12881,"VX_cache genblk5[4] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+12913,"VX_cache genblk5[4] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+40961,"VX_cache genblk5[4] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+40969,"VX_cache genblk5[4] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+40977,"VX_cache genblk5[4] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+41009,"VX_cache genblk5[4] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+40961,"VX_cache genblk5[4] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+40969,"VX_cache genblk5[4] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+40977,"VX_cache genblk5[4] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+41009,"VX_cache genblk5[4] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+39489,"VX_cache genblk5[4] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+41041,"VX_cache genblk5[4] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+41049,"VX_cache genblk5[4] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+12929,"VX_cache genblk5[4] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+2009,"VX_cache genblk5[4] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+12937,"VX_cache genblk5[4] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+12945,"VX_cache genblk5[4] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[4] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+2009,"VX_cache genblk5[4] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+12937,"VX_cache genblk5[4] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+1169,"VX_cache genblk5[4] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+12953,"VX_cache genblk5[4] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+41041,"VX_cache genblk5[4] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+39481,"VX_cache genblk5[4] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+41057,"VX_cache genblk5[4] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+41057,"VX_cache genblk5[4] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+13033,"VX_cache genblk5[4] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+1249,"VX_cache genblk5[4] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+41065+i*10,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+41705,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+41785,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+41865,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+41873,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+41881,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+41041,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+39481,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+41889,"VX_cache genblk5[4] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+13041,"VX_cache genblk5[4] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+13041,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+40953,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+12041,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+12033,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+13049,"VX_cache genblk5[4] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[4] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[4] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+12169,"VX_cache genblk5[4] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[4] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+13057,"VX_cache genblk5[4] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+41897,"VX_cache genblk5[4] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+41897,"VX_cache genblk5[4] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[4] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank tag_data_access reset", false,-1); - vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access stall", false,-1); - vcdp->declBit(c+12553,"VX_cache genblk5[4] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+12561,"VX_cache genblk5[4] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+12121,"VX_cache genblk5[4] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+12617,"VX_cache genblk5[4] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+12593,"VX_cache genblk5[4] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+13129,"VX_cache genblk5[4] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+13137,"VX_cache genblk5[4] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+13145,"VX_cache genblk5[4] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+12529,"VX_cache genblk5[4] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+12537,"VX_cache genblk5[4] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+13177,"VX_cache genblk5[4] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+12433,"VX_cache genblk5[4] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+12441,"VX_cache genblk5[4] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+12473,"VX_cache genblk5[4] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+12481,"VX_cache genblk5[4] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+12489,"VX_cache genblk5[4] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+12497,"VX_cache genblk5[4] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+12545,"VX_cache genblk5[4] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+12569,"VX_cache genblk5[4] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+12577,"VX_cache genblk5[4] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+13185+i*1,"VX_cache genblk5[4] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+13193+i*1,"VX_cache genblk5[4] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+13201+i*1,"VX_cache genblk5[4] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+13209+i*1,"VX_cache genblk5[4] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+13217+i*4,"VX_cache genblk5[4] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+13249,"VX_cache genblk5[4] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+13257,"VX_cache genblk5[4] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+13265,"VX_cache genblk5[4] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+13273,"VX_cache genblk5[4] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+13281,"VX_cache genblk5[4] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+13313,"VX_cache genblk5[4] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+13321,"VX_cache genblk5[4] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+12497,"VX_cache genblk5[4] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+12473,"VX_cache genblk5[4] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+12441,"VX_cache genblk5[4] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+13329,"VX_cache genblk5[4] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+13337,"VX_cache genblk5[4] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+12481,"VX_cache genblk5[4] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+13369,"VX_cache genblk5[4] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+13377,"VX_cache genblk5[4] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+13385,"VX_cache genblk5[4] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+13393,"VX_cache genblk5[4] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+13401,"VX_cache genblk5[4] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+13337,"VX_cache genblk5[4] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+13409,"VX_cache genblk5[4] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+13369,"VX_cache genblk5[4] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+13417,"VX_cache genblk5[4] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+13425,"VX_cache genblk5[4] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+13433,"VX_cache genblk5[4] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+13441,"VX_cache genblk5[4] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+13449,"VX_cache genblk5[4] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+13457,"VX_cache genblk5[4] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+13465,"VX_cache genblk5[4] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+13473,"VX_cache genblk5[4] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[4] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+13249,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+13257,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+13265,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+13273,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+13281,"VX_cache genblk5[4] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+13369,"VX_cache genblk5[4] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+13329,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+13385,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+13121,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+13393,"VX_cache genblk5[4] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+13337,"VX_cache genblk5[4] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+12481,"VX_cache genblk5[4] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+41961,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+41993,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+42025,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+42057,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+42089,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+42121,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+42153,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+42185,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+42217,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+42249,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+42281,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+42313,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+42345,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+42377,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+42409,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+42441,"VX_cache genblk5[4] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+42473+i*1,"VX_cache genblk5[4] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+42601,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+42609,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+42617,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+42625,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+42633,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+42641,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+42649,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+42657,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+42665,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+42673,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+42681,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+42689,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+42697,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+42705,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+42713,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+42721,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+42729,"VX_cache genblk5[4] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+42737,"VX_cache genblk5[4] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+13481,"VX_cache genblk5[4] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+42745,"VX_cache genblk5[4] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+42753,"VX_cache genblk5[4] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+12169,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+13489,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+13489,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+42761,"VX_cache genblk5[4] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[4] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[4] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+12169,"VX_cache genblk5[4] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[4] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+13537,"VX_cache genblk5[4] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+42809,"VX_cache genblk5[4] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+42809,"VX_cache genblk5[4] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[4] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58713,"VX_cache genblk5[4] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[4] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[4] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[4] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+12665,"VX_cache genblk5[4] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+12673,"VX_cache genblk5[4] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19833,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+39649,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+39657,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+39593,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+39601,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+39617,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+39625,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+12633,"VX_cache genblk5[4] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+39761,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+39769,"VX_cache genblk5[4] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+39505,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+39513,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+13129,"VX_cache genblk5[4] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+12617,"VX_cache genblk5[4] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+12105,"VX_cache genblk5[4] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+12081,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+12089,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+39529,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+39537,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+39545,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+39521,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+39553,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+12097,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+39569,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+39577,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+39585,"VX_cache genblk5[4] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+42889+i*3,"VX_cache genblk5[4] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+43273,"VX_cache genblk5[4] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+43377,"VX_cache genblk5[4] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+43385,"VX_cache genblk5[4] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+43393,"VX_cache genblk5[4] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+43401,"VX_cache genblk5[4] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+43409,"VX_cache genblk5[4] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+43417,"VX_cache genblk5[4] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+43425,"VX_cache genblk5[4] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+43409,"VX_cache genblk5[4] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+13617,"VX_cache genblk5[4] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+13625,"VX_cache genblk5[4] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+13633,"VX_cache genblk5[4] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+12089,"VX_cache genblk5[4] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+43393,"VX_cache genblk5[4] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+13641,"VX_cache genblk5[4] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+13649,"VX_cache genblk5[4] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+13657,"VX_cache genblk5[4] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+13665,"VX_cache genblk5[4] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+13673,"VX_cache genblk5[4] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+13681,"VX_cache genblk5[4] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[4] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[4] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank cwb_queue reset", false,-1); - vcdp->declBit(c+12681,"VX_cache genblk5[4] bank cwb_queue push", false,-1); - vcdp->declBit(c+1993,"VX_cache genblk5[4] bank cwb_queue pop", false,-1); - vcdp->declArray(c+13689,"VX_cache genblk5[4] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+13713,"VX_cache genblk5[4] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+39809,"VX_cache genblk5[4] bank cwb_queue empty", false,-1); - vcdp->declBit(c+39817,"VX_cache genblk5[4] bank cwb_queue full", false,-1); - vcdp->declBus(c+43433,"VX_cache genblk5[4] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+43433,"VX_cache genblk5[4] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+1257,"VX_cache genblk5[4] bank cwb_queue reading", false,-1); - vcdp->declBit(c+13737,"VX_cache genblk5[4] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+43441+i*3,"VX_cache genblk5[4] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+43633,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+43657,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+43681,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+43689,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+43697,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+39809,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+39817,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+43705,"VX_cache genblk5[4] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[4] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[4] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[4] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[4] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[4] bank dwb_queue reset", false,-1); - vcdp->declBit(c+12705,"VX_cache genblk5[4] bank dwb_queue push", false,-1); - vcdp->declBit(c+2001,"VX_cache genblk5[4] bank dwb_queue pop", false,-1); - vcdp->declArray(c+13745,"VX_cache genblk5[4] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+13801,"VX_cache genblk5[4] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+39825,"VX_cache genblk5[4] bank dwb_queue empty", false,-1); - vcdp->declBit(c+39833,"VX_cache genblk5[4] bank dwb_queue full", false,-1); - vcdp->declBus(c+43713,"VX_cache genblk5[4] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+43713,"VX_cache genblk5[4] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+1265,"VX_cache genblk5[4] bank dwb_queue reading", false,-1); - vcdp->declBit(c+13857,"VX_cache genblk5[4] bank dwb_queue writing", false,-1); + vcdp->declArray(c+23385+i*3,"VX_cache genblk5[3] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} + vcdp->declArray(c+23769,"VX_cache genblk5[3] bank cache_miss_resrv addr_table", false,-1, 415,0); + vcdp->declBus(c+23873,"VX_cache genblk5[3] bank cache_miss_resrv valid_table", false,-1, 15,0); + vcdp->declBus(c+23881,"VX_cache genblk5[3] bank cache_miss_resrv ready_table", false,-1, 15,0); + vcdp->declBus(c+23889,"VX_cache genblk5[3] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); + vcdp->declBus(c+23897,"VX_cache genblk5[3] bank cache_miss_resrv head_ptr", false,-1, 3,0); + vcdp->declBus(c+23905,"VX_cache genblk5[3] bank cache_miss_resrv tail_ptr", false,-1, 3,0); + vcdp->declBus(c+23913,"VX_cache genblk5[3] bank cache_miss_resrv size", false,-1, 4,0); + vcdp->declBit(c+23921,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_possible", false,-1); + vcdp->declBus(c+23905,"VX_cache genblk5[3] bank cache_miss_resrv enqueue_index", false,-1, 3,0); + vcdp->declBus(c+9817,"VX_cache genblk5[3] bank cache_miss_resrv make_ready", false,-1, 15,0); + vcdp->declBus(c+9825,"VX_cache genblk5[3] bank cache_miss_resrv make_ready_push", false,-1, 15,0); + vcdp->declBus(c+9833,"VX_cache genblk5[3] bank cache_miss_resrv valid_address_match", false,-1, 15,0); + vcdp->declBit(c+8289,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_possible", false,-1); + vcdp->declBus(c+23889,"VX_cache genblk5[3] bank cache_miss_resrv dequeue_index", false,-1, 3,0); + vcdp->declBit(c+9841,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_push", false,-1); + vcdp->declBit(c+9849,"VX_cache genblk5[3] bank cache_miss_resrv mrvq_pop", false,-1); + vcdp->declBit(c+9857,"VX_cache genblk5[3] bank cache_miss_resrv recover_state", false,-1); + vcdp->declBit(c+9865,"VX_cache genblk5[3] bank cache_miss_resrv increment_head", false,-1); + vcdp->declBit(c+9873,"VX_cache genblk5[3] bank cache_miss_resrv update_ready", false,-1); + vcdp->declBit(c+9881,"VX_cache genblk5[3] bank cache_miss_resrv qual_mrvq_init", false,-1); + vcdp->declBus(c+25217,"VX_cache genblk5[3] bank cwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank cwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank cwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank cwb_queue reset", false,-1); + vcdp->declBit(c+8881,"VX_cache genblk5[3] bank cwb_queue push", false,-1); + vcdp->declBit(c+1065,"VX_cache genblk5[3] bank cwb_queue pop", false,-1); + vcdp->declArray(c+9889,"VX_cache genblk5[3] bank cwb_queue data_in", false,-1, 75,0); + vcdp->declArray(c+9913,"VX_cache genblk5[3] bank cwb_queue data_out", false,-1, 75,0); + vcdp->declBit(c+21377,"VX_cache genblk5[3] bank cwb_queue empty", false,-1); + vcdp->declBit(c+21385,"VX_cache genblk5[3] bank cwb_queue full", false,-1); + vcdp->declBus(c+23929,"VX_cache genblk5[3] bank cwb_queue size", false,-1, 2,0); + vcdp->declBus(c+23929,"VX_cache genblk5[3] bank cwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+937,"VX_cache genblk5[3] bank cwb_queue reading", false,-1); + vcdp->declBit(c+9937,"VX_cache genblk5[3] bank cwb_queue writing", false,-1); {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+43721+i*7,"VX_cache genblk5[4] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+43945,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+44001,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+44057,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+44065,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+44073,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+39825,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+39833,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+44081,"VX_cache genblk5[4] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58641,"VX_cache genblk5[5] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58841,"VX_cache genblk5[5] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[5] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[5] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[5] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[5] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank reset", false,-1); - vcdp->declBus(c+193,"VX_cache genblk5[5] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[5] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[5] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[5] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[5] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[5] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19889,"VX_cache genblk5[5] bank core_req_ready", false,-1); - vcdp->declBit(c+19857,"VX_cache genblk5[5] bank core_rsp_valid", false,-1); - vcdp->declBus(c+3345,"VX_cache genblk5[5] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3353,"VX_cache genblk5[5] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3361,"VX_cache genblk5[5] bank core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+201,"VX_cache genblk5[5] bank core_rsp_ready", false,-1); - vcdp->declBit(c+3377,"VX_cache genblk5[5] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19873,"VX_cache genblk5[5] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[5] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58577,"VX_cache genblk5[5] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[5] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[5] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19865,"VX_cache genblk5[5] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3385,"VX_cache genblk5[5] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+3393,"VX_cache genblk5[5] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3401,"VX_cache genblk5[5] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3409,"VX_cache genblk5[5] bank dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+209,"VX_cache genblk5[5] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58585,"VX_cache genblk5[5] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[5] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[5] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[5] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19881,"VX_cache genblk5[5] bank snp_req_ready", false,-1); - vcdp->declBit(c+3441,"VX_cache genblk5[5] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+3449,"VX_cache genblk5[5] bank snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+217,"VX_cache genblk5[5] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+13865,"VX_cache genblk5[5] bank snrq_pop", false,-1); - vcdp->declBit(c+44089,"VX_cache genblk5[5] bank snrq_empty", false,-1); - vcdp->declBit(c+44097,"VX_cache genblk5[5] bank snrq_full", false,-1); - vcdp->declBus(c+13873,"VX_cache genblk5[5] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+13881,"VX_cache genblk5[5] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+13889,"VX_cache genblk5[5] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+13897,"VX_cache genblk5[5] bank dfpq_pop", false,-1); - vcdp->declBit(c+44105,"VX_cache genblk5[5] bank dfpq_empty", false,-1); - vcdp->declBit(c+44113,"VX_cache genblk5[5] bank dfpq_full", false,-1); - vcdp->declBus(c+13905,"VX_cache genblk5[5] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+13913,"VX_cache genblk5[5] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+13945,"VX_cache genblk5[5] bank reqq_pop", false,-1); - vcdp->declBit(c+2017,"VX_cache genblk5[5] bank reqq_push", false,-1); - vcdp->declBit(c+13953,"VX_cache genblk5[5] bank reqq_empty", false,-1); - vcdp->declBit(c+44121,"VX_cache genblk5[5] bank reqq_full", false,-1); - vcdp->declBit(c+13961,"VX_cache genblk5[5] bank reqq_req_st0", false,-1); - vcdp->declBus(c+13969,"VX_cache genblk5[5] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+13977,"VX_cache genblk5[5] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+13985,"VX_cache genblk5[5] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+13993,"VX_cache genblk5[5] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+14001,"VX_cache genblk5[5] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+14009,"VX_cache genblk5[5] bank mrvq_pop", false,-1); - vcdp->declBit(c+44145,"VX_cache genblk5[5] bank mrvq_full", false,-1); - vcdp->declBit(c+44153,"VX_cache genblk5[5] bank mrvq_stop", false,-1); - vcdp->declBit(c+14017,"VX_cache genblk5[5] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+44161,"VX_cache genblk5[5] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+44169,"VX_cache genblk5[5] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+44177,"VX_cache genblk5[5] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+44185,"VX_cache genblk5[5] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+44193,"VX_cache genblk5[5] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+14025,"VX_cache genblk5[5] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+44209,"VX_cache genblk5[5] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+44217,"VX_cache genblk5[5] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+44225,"VX_cache genblk5[5] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+14033,"VX_cache genblk5[5] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+14041,"VX_cache genblk5[5] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+14049,"VX_cache genblk5[5] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+44233,"VX_cache genblk5[5] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+44241,"VX_cache genblk5[5] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+44257,"VX_cache genblk5[5] bank miss_add_rw", false,-1); - vcdp->declBus(c+44265,"VX_cache genblk5[5] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19873,"VX_cache genblk5[5] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+44273,"VX_cache genblk5[5] bank is_fill_st2", false,-1); - vcdp->declBit(c+14057,"VX_cache genblk5[5] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+14065,"VX_cache genblk5[5] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+14073,"VX_cache genblk5[5] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+14081,"VX_cache genblk5[5] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+14089,"VX_cache genblk5[5] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+14097,"VX_cache genblk5[5] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+14105,"VX_cache genblk5[5] bank is_fill_in_pipe", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+14113+i*1,"VX_cache genblk5[5] bank is_fill_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+14121+i*1,"VX_cache genblk5[5] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[5] bank j", false,-1, 31,0); - vcdp->declBit(c+14017,"VX_cache genblk5[5] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+14129,"VX_cache genblk5[5] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+14137,"VX_cache genblk5[5] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+14145,"VX_cache genblk5[5] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+14129,"VX_cache genblk5[5] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+14153,"VX_cache genblk5[5] bank qual_valid_st0", false,-1); - vcdp->declBus(c+14161,"VX_cache genblk5[5] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+14169,"VX_cache genblk5[5] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+14017,"VX_cache genblk5[5] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+14177,"VX_cache genblk5[5] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+14185,"VX_cache genblk5[5] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+14217,"VX_cache genblk5[5] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+14233,"VX_cache genblk5[5] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+14241,"VX_cache genblk5[5] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+14249,"VX_cache genblk5[5] bank qual_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+14257+i*1,"VX_cache genblk5[5] bank valid_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+14265+i*1,"VX_cache genblk5[5] bank addr_st1", true,(i+0), 24,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+14273+i*1,"VX_cache genblk5[5] bank wsel_st1", true,(i+0), 1,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+14281+i*1,"VX_cache genblk5[5] bank writeword_st1", true,(i+0), 31,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+14289+i*2,"VX_cache genblk5[5] bank inst_meta_st1", true,(i+0), 48,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+14305+i*4,"VX_cache genblk5[5] bank writedata_st1", true,(i+0), 127,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+14337+i*1,"VX_cache genblk5[5] bank is_snp_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+14345+i*1,"VX_cache genblk5[5] bank snp_invalidate_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+14353+i*1,"VX_cache genblk5[5] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+14361,"VX_cache genblk5[5] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+14369,"VX_cache genblk5[5] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+14401,"VX_cache genblk5[5] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+14409,"VX_cache genblk5[5] bank miss_st1e", false,-1); - vcdp->declBit(c+14417,"VX_cache genblk5[5] bank dirty_st1e", false,-1); - vcdp->declBus(c+14425,"VX_cache genblk5[5] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+14433,"VX_cache genblk5[5] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+14449,"VX_cache genblk5[5] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+14457,"VX_cache genblk5[5] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+14465,"VX_cache genblk5[5] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+14473,"VX_cache genblk5[5] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+14481,"VX_cache genblk5[5] bank is_snp_st1e", false,-1); - vcdp->declBit(c+14489,"VX_cache genblk5[5] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+14497,"VX_cache genblk5[5] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+14505,"VX_cache genblk5[5] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+14513,"VX_cache genblk5[5] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+14521,"VX_cache genblk5[5] bank valid_st1e", false,-1); - vcdp->declBit(c+14529,"VX_cache genblk5[5] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+14537,"VX_cache genblk5[5] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+14545,"VX_cache genblk5[5] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+14553,"VX_cache genblk5[5] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+14529,"VX_cache genblk5[5] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+44281,"VX_cache genblk5[5] bank valid_st2", false,-1); - vcdp->declBus(c+44289,"VX_cache genblk5[5] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+44297,"VX_cache genblk5[5] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+44305,"VX_cache genblk5[5] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+44313,"VX_cache genblk5[5] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+44345,"VX_cache genblk5[5] bank miss_st2", false,-1); - vcdp->declBit(c+44353,"VX_cache genblk5[5] bank dirty_st2", false,-1); - vcdp->declBus(c+44361,"VX_cache genblk5[5] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+44369,"VX_cache genblk5[5] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+44385,"VX_cache genblk5[5] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+44393,"VX_cache genblk5[5] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+44401,"VX_cache genblk5[5] bank is_snp_st2", false,-1); - vcdp->declBit(c+44409,"VX_cache genblk5[5] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+44417,"VX_cache genblk5[5] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+44425,"VX_cache genblk5[5] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+14561,"VX_cache genblk5[5] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+44433,"VX_cache genblk5[5] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+44441,"VX_cache genblk5[5] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+14569,"VX_cache genblk5[5] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+14577,"VX_cache genblk5[5] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+44417,"VX_cache genblk5[5] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+14585,"VX_cache genblk5[5] bank miss_add_unqual", false,-1); - vcdp->declBit(c+14593,"VX_cache genblk5[5] bank miss_add", false,-1); - vcdp->declBus(c+19873,"VX_cache genblk5[5] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+44289,"VX_cache genblk5[5] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+44297,"VX_cache genblk5[5] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+44401,"VX_cache genblk5[5] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+44409,"VX_cache genblk5[5] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+14601,"VX_cache genblk5[5] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+14609,"VX_cache genblk5[5] bank cwbq_push", false,-1); - vcdp->declBit(c+2025,"VX_cache genblk5[5] bank cwbq_pop", false,-1); - vcdp->declBit(c+44449,"VX_cache genblk5[5] bank cwbq_empty", false,-1); - vcdp->declBit(c+44457,"VX_cache genblk5[5] bank cwbq_full", false,-1); - vcdp->declBit(c+14617,"VX_cache genblk5[5] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+44305,"VX_cache genblk5[5] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+44233,"VX_cache genblk5[5] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+44241,"VX_cache genblk5[5] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+14585,"VX_cache genblk5[5] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+14625,"VX_cache genblk5[5] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+14633,"VX_cache genblk5[5] bank dwbq_push", false,-1); - vcdp->declBit(c+2033,"VX_cache genblk5[5] bank dwbq_pop", false,-1); - vcdp->declBit(c+44465,"VX_cache genblk5[5] bank dwbq_empty", false,-1); - vcdp->declBit(c+44473,"VX_cache genblk5[5] bank dwbq_full", false,-1); - vcdp->declBit(c+14641,"VX_cache genblk5[5] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+14649,"VX_cache genblk5[5] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+14657,"VX_cache genblk5[5] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+14665,"VX_cache genblk5[5] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+14673,"VX_cache genblk5[5] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+44481,"VX_cache genblk5[5] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+44489,"VX_cache genblk5[5] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+1273,"VX_cache genblk5[5] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+1281,"VX_cache genblk5[5] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+44497,"VX_cache genblk5[5] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[5] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58585,"VX_cache genblk5[5] bank snp_req_queue push", false,-1); - vcdp->declBit(c+13865,"VX_cache genblk5[5] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+1289,"VX_cache genblk5[5] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+14681,"VX_cache genblk5[5] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+44089,"VX_cache genblk5[5] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+44097,"VX_cache genblk5[5] bank snp_req_queue full", false,-1); - vcdp->declBus(c+44505,"VX_cache genblk5[5] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+44505,"VX_cache genblk5[5] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+14697,"VX_cache genblk5[5] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+1305,"VX_cache genblk5[5] bank snp_req_queue writing", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+44513+i*2,"VX_cache genblk5[5] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+44769,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+44785,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+44801,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+44809,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+44817,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+44089,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+44097,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+44825,"VX_cache genblk5[5] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[5] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58577,"VX_cache genblk5[5] bank dfp_queue push", false,-1); - vcdp->declBit(c+13897,"VX_cache genblk5[5] bank dfp_queue pop", false,-1); - vcdp->declArray(c+1313,"VX_cache genblk5[5] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+14705,"VX_cache genblk5[5] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+44105,"VX_cache genblk5[5] bank dfp_queue empty", false,-1); - vcdp->declBit(c+44113,"VX_cache genblk5[5] bank dfp_queue full", false,-1); - vcdp->declBus(c+44833,"VX_cache genblk5[5] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+44833,"VX_cache genblk5[5] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+14745,"VX_cache genblk5[5] bank dfp_queue reading", false,-1); - vcdp->declBit(c+1353,"VX_cache genblk5[5] bank dfp_queue writing", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+44841+i*5,"VX_cache genblk5[5] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+45481,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+45521,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+45561,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+45569,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+45577,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+44105,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+44113,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+45585,"VX_cache genblk5[5] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[5] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank core_req_arb reset", false,-1); - vcdp->declBit(c+2017,"VX_cache genblk5[5] bank core_req_arb reqq_push", false,-1); - vcdp->declBus(c+193,"VX_cache genblk5[5] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[5] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[5] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[5] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[5] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[5] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+13945,"VX_cache genblk5[5] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+13977,"VX_cache genblk5[5] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+13985,"VX_cache genblk5[5] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+13993,"VX_cache genblk5[5] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+14001,"VX_cache genblk5[5] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+13953,"VX_cache genblk5[5] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+44121,"VX_cache genblk5[5] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+14753,"VX_cache genblk5[5] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+14761,"VX_cache genblk5[5] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+14769,"VX_cache genblk5[5] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+14777,"VX_cache genblk5[5] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+14809,"VX_cache genblk5[5] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+14841,"VX_cache genblk5[5] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+45601,"VX_cache genblk5[5] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+45609,"VX_cache genblk5[5] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+45617,"VX_cache genblk5[5] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+45649,"VX_cache genblk5[5] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+45601,"VX_cache genblk5[5] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+45609,"VX_cache genblk5[5] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+45617,"VX_cache genblk5[5] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+45649,"VX_cache genblk5[5] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+44129,"VX_cache genblk5[5] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+45681,"VX_cache genblk5[5] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+45689,"VX_cache genblk5[5] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+14857,"VX_cache genblk5[5] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+2041,"VX_cache genblk5[5] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+14865,"VX_cache genblk5[5] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+14873,"VX_cache genblk5[5] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[5] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+2041,"VX_cache genblk5[5] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+14865,"VX_cache genblk5[5] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+1361,"VX_cache genblk5[5] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+14881,"VX_cache genblk5[5] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+45681,"VX_cache genblk5[5] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+44121,"VX_cache genblk5[5] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+45697,"VX_cache genblk5[5] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+45697,"VX_cache genblk5[5] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+14961,"VX_cache genblk5[5] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+1441,"VX_cache genblk5[5] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+45705+i*10,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+46345,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+46425,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+46505,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+46513,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+46521,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+45681,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+44121,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+46529,"VX_cache genblk5[5] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+14969,"VX_cache genblk5[5] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+14969,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+45593,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+13969,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+13961,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+14977,"VX_cache genblk5[5] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[5] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[5] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+14097,"VX_cache genblk5[5] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[5] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+14985,"VX_cache genblk5[5] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+46537,"VX_cache genblk5[5] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+46537,"VX_cache genblk5[5] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[5] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank tag_data_access reset", false,-1); - vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access stall", false,-1); - vcdp->declBit(c+14481,"VX_cache genblk5[5] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+14489,"VX_cache genblk5[5] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+14049,"VX_cache genblk5[5] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+14545,"VX_cache genblk5[5] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+14521,"VX_cache genblk5[5] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+15057,"VX_cache genblk5[5] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+15065,"VX_cache genblk5[5] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+15073,"VX_cache genblk5[5] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+14457,"VX_cache genblk5[5] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+14465,"VX_cache genblk5[5] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+15105,"VX_cache genblk5[5] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+14361,"VX_cache genblk5[5] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+14369,"VX_cache genblk5[5] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+14401,"VX_cache genblk5[5] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+14409,"VX_cache genblk5[5] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+14417,"VX_cache genblk5[5] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+14425,"VX_cache genblk5[5] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+14473,"VX_cache genblk5[5] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+14497,"VX_cache genblk5[5] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+14505,"VX_cache genblk5[5] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+15113+i*1,"VX_cache genblk5[5] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+15121+i*1,"VX_cache genblk5[5] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+15129+i*1,"VX_cache genblk5[5] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+15137+i*1,"VX_cache genblk5[5] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+15145+i*4,"VX_cache genblk5[5] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+15177,"VX_cache genblk5[5] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+15185,"VX_cache genblk5[5] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+15193,"VX_cache genblk5[5] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+15201,"VX_cache genblk5[5] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+15209,"VX_cache genblk5[5] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+15241,"VX_cache genblk5[5] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+15249,"VX_cache genblk5[5] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+14425,"VX_cache genblk5[5] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+14401,"VX_cache genblk5[5] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+14369,"VX_cache genblk5[5] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+15257,"VX_cache genblk5[5] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+15265,"VX_cache genblk5[5] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+14409,"VX_cache genblk5[5] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+15297,"VX_cache genblk5[5] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+15305,"VX_cache genblk5[5] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+15313,"VX_cache genblk5[5] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+15321,"VX_cache genblk5[5] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+15329,"VX_cache genblk5[5] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+15265,"VX_cache genblk5[5] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+15337,"VX_cache genblk5[5] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+15297,"VX_cache genblk5[5] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+15345,"VX_cache genblk5[5] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+15353,"VX_cache genblk5[5] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+15361,"VX_cache genblk5[5] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+15369,"VX_cache genblk5[5] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+15377,"VX_cache genblk5[5] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+15385,"VX_cache genblk5[5] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+15393,"VX_cache genblk5[5] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+15401,"VX_cache genblk5[5] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[5] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+15177,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+15185,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+15193,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+15201,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+15209,"VX_cache genblk5[5] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+15297,"VX_cache genblk5[5] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+15257,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+15313,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+15049,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+15321,"VX_cache genblk5[5] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+15265,"VX_cache genblk5[5] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+14409,"VX_cache genblk5[5] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+46601,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+46633,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+46665,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+46697,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+46729,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+46761,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+46793,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+46825,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+46857,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+46889,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+46921,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+46953,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+46985,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+47017,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+47049,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+47081,"VX_cache genblk5[5] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+47113+i*1,"VX_cache genblk5[5] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+47241,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+47249,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+47257,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+47265,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+47273,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+47281,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+47289,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+47297,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+47305,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+47313,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+47321,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+47329,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+47337,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+47345,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+47353,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+47361,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+47369,"VX_cache genblk5[5] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+47377,"VX_cache genblk5[5] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+15409,"VX_cache genblk5[5] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+47385,"VX_cache genblk5[5] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+47393,"VX_cache genblk5[5] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+14097,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+15417,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+15417,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+47401,"VX_cache genblk5[5] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[5] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[5] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+14097,"VX_cache genblk5[5] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[5] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+15465,"VX_cache genblk5[5] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+47449,"VX_cache genblk5[5] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+47449,"VX_cache genblk5[5] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[5] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58841,"VX_cache genblk5[5] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[5] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[5] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[5] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+14593,"VX_cache genblk5[5] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+14601,"VX_cache genblk5[5] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19873,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+44289,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+44297,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+44233,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+44241,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+44257,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+44265,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+14561,"VX_cache genblk5[5] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+44401,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+44409,"VX_cache genblk5[5] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+44145,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+44153,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+15057,"VX_cache genblk5[5] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+14545,"VX_cache genblk5[5] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+14033,"VX_cache genblk5[5] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+14009,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+14017,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+44169,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+44177,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+44185,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+44161,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+44193,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+14025,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+44209,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+44217,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+44225,"VX_cache genblk5[5] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+47529+i*3,"VX_cache genblk5[5] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+47913,"VX_cache genblk5[5] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+48017,"VX_cache genblk5[5] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+48025,"VX_cache genblk5[5] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+48033,"VX_cache genblk5[5] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+48041,"VX_cache genblk5[5] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+48049,"VX_cache genblk5[5] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+48057,"VX_cache genblk5[5] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+48065,"VX_cache genblk5[5] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+48049,"VX_cache genblk5[5] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+15545,"VX_cache genblk5[5] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+15553,"VX_cache genblk5[5] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+15561,"VX_cache genblk5[5] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+14017,"VX_cache genblk5[5] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+48033,"VX_cache genblk5[5] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+15569,"VX_cache genblk5[5] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+15577,"VX_cache genblk5[5] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+15585,"VX_cache genblk5[5] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+15593,"VX_cache genblk5[5] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+15601,"VX_cache genblk5[5] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+15609,"VX_cache genblk5[5] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[5] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[5] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank cwb_queue reset", false,-1); - vcdp->declBit(c+14609,"VX_cache genblk5[5] bank cwb_queue push", false,-1); - vcdp->declBit(c+2025,"VX_cache genblk5[5] bank cwb_queue pop", false,-1); - vcdp->declArray(c+15617,"VX_cache genblk5[5] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+15641,"VX_cache genblk5[5] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+44449,"VX_cache genblk5[5] bank cwb_queue empty", false,-1); - vcdp->declBit(c+44457,"VX_cache genblk5[5] bank cwb_queue full", false,-1); - vcdp->declBus(c+48073,"VX_cache genblk5[5] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+48073,"VX_cache genblk5[5] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+1449,"VX_cache genblk5[5] bank cwb_queue reading", false,-1); - vcdp->declBit(c+15665,"VX_cache genblk5[5] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+48081+i*3,"VX_cache genblk5[5] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+48273,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+48297,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+48321,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+48329,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+48337,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+44449,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+44457,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+48345,"VX_cache genblk5[5] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[5] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[5] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[5] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[5] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[5] bank dwb_queue reset", false,-1); - vcdp->declBit(c+14633,"VX_cache genblk5[5] bank dwb_queue push", false,-1); - vcdp->declBit(c+2033,"VX_cache genblk5[5] bank dwb_queue pop", false,-1); - vcdp->declArray(c+15673,"VX_cache genblk5[5] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+15729,"VX_cache genblk5[5] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+44465,"VX_cache genblk5[5] bank dwb_queue empty", false,-1); - vcdp->declBit(c+44473,"VX_cache genblk5[5] bank dwb_queue full", false,-1); - vcdp->declBus(c+48353,"VX_cache genblk5[5] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+48353,"VX_cache genblk5[5] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+1457,"VX_cache genblk5[5] bank dwb_queue reading", false,-1); - vcdp->declBit(c+15785,"VX_cache genblk5[5] bank dwb_queue writing", false,-1); + vcdp->declArray(c+23937+i*3,"VX_cache genblk5[3] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} + vcdp->declArray(c+24033,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); + vcdp->declArray(c+24057,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); + vcdp->declBus(c+24081,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24089,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24097,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+21377,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21385,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+24105,"VX_cache genblk5[3] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declBus(c+25225,"VX_cache genblk5[3] bank dwb_queue DATAW", false,-1, 31,0); + vcdp->declBus(c+25081,"VX_cache genblk5[3] bank dwb_queue SIZE", false,-1, 31,0); + vcdp->declBus(c+25089,"VX_cache genblk5[3] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); + vcdp->declBit(c+24489,"VX_cache genblk5[3] bank dwb_queue clk", false,-1); + vcdp->declBit(c+24497,"VX_cache genblk5[3] bank dwb_queue reset", false,-1); + vcdp->declBit(c+8905,"VX_cache genblk5[3] bank dwb_queue push", false,-1); + vcdp->declBit(c+1073,"VX_cache genblk5[3] bank dwb_queue pop", false,-1); + vcdp->declArray(c+9945,"VX_cache genblk5[3] bank dwb_queue data_in", false,-1, 199,0); + vcdp->declArray(c+10001,"VX_cache genblk5[3] bank dwb_queue data_out", false,-1, 199,0); + vcdp->declBit(c+21393,"VX_cache genblk5[3] bank dwb_queue empty", false,-1); + vcdp->declBit(c+21401,"VX_cache genblk5[3] bank dwb_queue full", false,-1); + vcdp->declBus(c+24113,"VX_cache genblk5[3] bank dwb_queue size", false,-1, 2,0); + vcdp->declBus(c+24113,"VX_cache genblk5[3] bank dwb_queue size_r", false,-1, 2,0); + vcdp->declBit(c+945,"VX_cache genblk5[3] bank dwb_queue reading", false,-1); + vcdp->declBit(c+10057,"VX_cache genblk5[3] bank dwb_queue writing", false,-1); {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+48361+i*7,"VX_cache genblk5[5] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+48585,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+48641,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+48697,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+48705,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+48713,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+44465,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+44473,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+48721,"VX_cache genblk5[5] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58641,"VX_cache genblk5[6] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58849,"VX_cache genblk5[6] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[6] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[6] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[6] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[6] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank reset", false,-1); - vcdp->declBus(c+225,"VX_cache genblk5[6] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[6] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[6] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[6] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[6] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[6] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19929,"VX_cache genblk5[6] bank core_req_ready", false,-1); - vcdp->declBit(c+19897,"VX_cache genblk5[6] bank core_rsp_valid", false,-1); - vcdp->declBus(c+3457,"VX_cache genblk5[6] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3465,"VX_cache genblk5[6] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3473,"VX_cache genblk5[6] bank core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+233,"VX_cache genblk5[6] bank core_rsp_ready", false,-1); - vcdp->declBit(c+3489,"VX_cache genblk5[6] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19913,"VX_cache genblk5[6] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[6] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58593,"VX_cache genblk5[6] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[6] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[6] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19905,"VX_cache genblk5[6] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3497,"VX_cache genblk5[6] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+3505,"VX_cache genblk5[6] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3513,"VX_cache genblk5[6] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3521,"VX_cache genblk5[6] bank dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+241,"VX_cache genblk5[6] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58601,"VX_cache genblk5[6] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[6] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[6] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[6] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19921,"VX_cache genblk5[6] bank snp_req_ready", false,-1); - vcdp->declBit(c+3553,"VX_cache genblk5[6] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+3561,"VX_cache genblk5[6] bank snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+249,"VX_cache genblk5[6] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+15793,"VX_cache genblk5[6] bank snrq_pop", false,-1); - vcdp->declBit(c+48729,"VX_cache genblk5[6] bank snrq_empty", false,-1); - vcdp->declBit(c+48737,"VX_cache genblk5[6] bank snrq_full", false,-1); - vcdp->declBus(c+15801,"VX_cache genblk5[6] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+15809,"VX_cache genblk5[6] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+15817,"VX_cache genblk5[6] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+15825,"VX_cache genblk5[6] bank dfpq_pop", false,-1); - vcdp->declBit(c+48745,"VX_cache genblk5[6] bank dfpq_empty", false,-1); - vcdp->declBit(c+48753,"VX_cache genblk5[6] bank dfpq_full", false,-1); - vcdp->declBus(c+15833,"VX_cache genblk5[6] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+15841,"VX_cache genblk5[6] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+15873,"VX_cache genblk5[6] bank reqq_pop", false,-1); - vcdp->declBit(c+2049,"VX_cache genblk5[6] bank reqq_push", false,-1); - vcdp->declBit(c+15881,"VX_cache genblk5[6] bank reqq_empty", false,-1); - vcdp->declBit(c+48761,"VX_cache genblk5[6] bank reqq_full", false,-1); - vcdp->declBit(c+15889,"VX_cache genblk5[6] bank reqq_req_st0", false,-1); - vcdp->declBus(c+15897,"VX_cache genblk5[6] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+15905,"VX_cache genblk5[6] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+15913,"VX_cache genblk5[6] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+15921,"VX_cache genblk5[6] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+15929,"VX_cache genblk5[6] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+15937,"VX_cache genblk5[6] bank mrvq_pop", false,-1); - vcdp->declBit(c+48785,"VX_cache genblk5[6] bank mrvq_full", false,-1); - vcdp->declBit(c+48793,"VX_cache genblk5[6] bank mrvq_stop", false,-1); - vcdp->declBit(c+15945,"VX_cache genblk5[6] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+48801,"VX_cache genblk5[6] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+48809,"VX_cache genblk5[6] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+48817,"VX_cache genblk5[6] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+48825,"VX_cache genblk5[6] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+48833,"VX_cache genblk5[6] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+15953,"VX_cache genblk5[6] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+48849,"VX_cache genblk5[6] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+48857,"VX_cache genblk5[6] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+48865,"VX_cache genblk5[6] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+15961,"VX_cache genblk5[6] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+15969,"VX_cache genblk5[6] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+15977,"VX_cache genblk5[6] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+48873,"VX_cache genblk5[6] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+48881,"VX_cache genblk5[6] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+48897,"VX_cache genblk5[6] bank miss_add_rw", false,-1); - vcdp->declBus(c+48905,"VX_cache genblk5[6] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19913,"VX_cache genblk5[6] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+48913,"VX_cache genblk5[6] bank is_fill_st2", false,-1); - vcdp->declBit(c+15985,"VX_cache genblk5[6] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+15993,"VX_cache genblk5[6] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+16001,"VX_cache genblk5[6] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+16009,"VX_cache genblk5[6] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+16017,"VX_cache genblk5[6] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+16025,"VX_cache genblk5[6] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+16033,"VX_cache genblk5[6] bank is_fill_in_pipe", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+16041+i*1,"VX_cache genblk5[6] bank is_fill_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+16049+i*1,"VX_cache genblk5[6] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[6] bank j", false,-1, 31,0); - vcdp->declBit(c+15945,"VX_cache genblk5[6] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+16057,"VX_cache genblk5[6] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+16065,"VX_cache genblk5[6] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+16073,"VX_cache genblk5[6] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+16057,"VX_cache genblk5[6] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+16081,"VX_cache genblk5[6] bank qual_valid_st0", false,-1); - vcdp->declBus(c+16089,"VX_cache genblk5[6] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+16097,"VX_cache genblk5[6] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+15945,"VX_cache genblk5[6] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+16105,"VX_cache genblk5[6] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+16113,"VX_cache genblk5[6] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+16145,"VX_cache genblk5[6] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+16161,"VX_cache genblk5[6] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+16169,"VX_cache genblk5[6] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+16177,"VX_cache genblk5[6] bank qual_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+16185+i*1,"VX_cache genblk5[6] bank valid_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+16193+i*1,"VX_cache genblk5[6] bank addr_st1", true,(i+0), 24,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+16201+i*1,"VX_cache genblk5[6] bank wsel_st1", true,(i+0), 1,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+16209+i*1,"VX_cache genblk5[6] bank writeword_st1", true,(i+0), 31,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+16217+i*2,"VX_cache genblk5[6] bank inst_meta_st1", true,(i+0), 48,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+16233+i*4,"VX_cache genblk5[6] bank writedata_st1", true,(i+0), 127,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+16265+i*1,"VX_cache genblk5[6] bank is_snp_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+16273+i*1,"VX_cache genblk5[6] bank snp_invalidate_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+16281+i*1,"VX_cache genblk5[6] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+16289,"VX_cache genblk5[6] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+16297,"VX_cache genblk5[6] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+16329,"VX_cache genblk5[6] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+16337,"VX_cache genblk5[6] bank miss_st1e", false,-1); - vcdp->declBit(c+16345,"VX_cache genblk5[6] bank dirty_st1e", false,-1); - vcdp->declBus(c+16353,"VX_cache genblk5[6] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+16361,"VX_cache genblk5[6] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+16377,"VX_cache genblk5[6] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+16385,"VX_cache genblk5[6] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+16393,"VX_cache genblk5[6] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+16401,"VX_cache genblk5[6] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+16409,"VX_cache genblk5[6] bank is_snp_st1e", false,-1); - vcdp->declBit(c+16417,"VX_cache genblk5[6] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+16425,"VX_cache genblk5[6] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+16433,"VX_cache genblk5[6] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+16441,"VX_cache genblk5[6] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+16449,"VX_cache genblk5[6] bank valid_st1e", false,-1); - vcdp->declBit(c+16457,"VX_cache genblk5[6] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+16465,"VX_cache genblk5[6] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+16473,"VX_cache genblk5[6] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+16481,"VX_cache genblk5[6] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+16457,"VX_cache genblk5[6] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+48921,"VX_cache genblk5[6] bank valid_st2", false,-1); - vcdp->declBus(c+48929,"VX_cache genblk5[6] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+48937,"VX_cache genblk5[6] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+48945,"VX_cache genblk5[6] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+48953,"VX_cache genblk5[6] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+48985,"VX_cache genblk5[6] bank miss_st2", false,-1); - vcdp->declBit(c+48993,"VX_cache genblk5[6] bank dirty_st2", false,-1); - vcdp->declBus(c+49001,"VX_cache genblk5[6] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+49009,"VX_cache genblk5[6] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+49025,"VX_cache genblk5[6] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+49033,"VX_cache genblk5[6] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+49041,"VX_cache genblk5[6] bank is_snp_st2", false,-1); - vcdp->declBit(c+49049,"VX_cache genblk5[6] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+49057,"VX_cache genblk5[6] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+49065,"VX_cache genblk5[6] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+16489,"VX_cache genblk5[6] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+49073,"VX_cache genblk5[6] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+49081,"VX_cache genblk5[6] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+16497,"VX_cache genblk5[6] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+16505,"VX_cache genblk5[6] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+49057,"VX_cache genblk5[6] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+16513,"VX_cache genblk5[6] bank miss_add_unqual", false,-1); - vcdp->declBit(c+16521,"VX_cache genblk5[6] bank miss_add", false,-1); - vcdp->declBus(c+19913,"VX_cache genblk5[6] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+48929,"VX_cache genblk5[6] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+48937,"VX_cache genblk5[6] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+49041,"VX_cache genblk5[6] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+49049,"VX_cache genblk5[6] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+16529,"VX_cache genblk5[6] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+16537,"VX_cache genblk5[6] bank cwbq_push", false,-1); - vcdp->declBit(c+2057,"VX_cache genblk5[6] bank cwbq_pop", false,-1); - vcdp->declBit(c+49089,"VX_cache genblk5[6] bank cwbq_empty", false,-1); - vcdp->declBit(c+49097,"VX_cache genblk5[6] bank cwbq_full", false,-1); - vcdp->declBit(c+16545,"VX_cache genblk5[6] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+48945,"VX_cache genblk5[6] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+48873,"VX_cache genblk5[6] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+48881,"VX_cache genblk5[6] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+16513,"VX_cache genblk5[6] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+16553,"VX_cache genblk5[6] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+16561,"VX_cache genblk5[6] bank dwbq_push", false,-1); - vcdp->declBit(c+2065,"VX_cache genblk5[6] bank dwbq_pop", false,-1); - vcdp->declBit(c+49105,"VX_cache genblk5[6] bank dwbq_empty", false,-1); - vcdp->declBit(c+49113,"VX_cache genblk5[6] bank dwbq_full", false,-1); - vcdp->declBit(c+16569,"VX_cache genblk5[6] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+16577,"VX_cache genblk5[6] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+16585,"VX_cache genblk5[6] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+16593,"VX_cache genblk5[6] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+16601,"VX_cache genblk5[6] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+49121,"VX_cache genblk5[6] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+49129,"VX_cache genblk5[6] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+1465,"VX_cache genblk5[6] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+1473,"VX_cache genblk5[6] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+49137,"VX_cache genblk5[6] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[6] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58601,"VX_cache genblk5[6] bank snp_req_queue push", false,-1); - vcdp->declBit(c+15793,"VX_cache genblk5[6] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+1481,"VX_cache genblk5[6] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+16609,"VX_cache genblk5[6] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+48729,"VX_cache genblk5[6] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+48737,"VX_cache genblk5[6] bank snp_req_queue full", false,-1); - vcdp->declBus(c+49145,"VX_cache genblk5[6] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+49145,"VX_cache genblk5[6] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+16625,"VX_cache genblk5[6] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+1497,"VX_cache genblk5[6] bank snp_req_queue writing", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+49153+i*2,"VX_cache genblk5[6] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+49409,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+49425,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+49441,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+49449,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+49457,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+48729,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+48737,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+49465,"VX_cache genblk5[6] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[6] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58593,"VX_cache genblk5[6] bank dfp_queue push", false,-1); - vcdp->declBit(c+15825,"VX_cache genblk5[6] bank dfp_queue pop", false,-1); - vcdp->declArray(c+1505,"VX_cache genblk5[6] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+16633,"VX_cache genblk5[6] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+48745,"VX_cache genblk5[6] bank dfp_queue empty", false,-1); - vcdp->declBit(c+48753,"VX_cache genblk5[6] bank dfp_queue full", false,-1); - vcdp->declBus(c+49473,"VX_cache genblk5[6] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+49473,"VX_cache genblk5[6] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+16673,"VX_cache genblk5[6] bank dfp_queue reading", false,-1); - vcdp->declBit(c+1545,"VX_cache genblk5[6] bank dfp_queue writing", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+49481+i*5,"VX_cache genblk5[6] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+50121,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+50161,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+50201,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+50209,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+50217,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+48745,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+48753,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+50225,"VX_cache genblk5[6] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[6] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank core_req_arb reset", false,-1); - vcdp->declBit(c+2049,"VX_cache genblk5[6] bank core_req_arb reqq_push", false,-1); - vcdp->declBus(c+225,"VX_cache genblk5[6] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[6] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[6] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[6] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[6] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[6] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+15873,"VX_cache genblk5[6] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+15905,"VX_cache genblk5[6] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+15913,"VX_cache genblk5[6] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+15921,"VX_cache genblk5[6] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+15929,"VX_cache genblk5[6] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+15881,"VX_cache genblk5[6] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+48761,"VX_cache genblk5[6] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+16681,"VX_cache genblk5[6] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+16689,"VX_cache genblk5[6] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+16697,"VX_cache genblk5[6] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+16705,"VX_cache genblk5[6] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+16737,"VX_cache genblk5[6] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+16769,"VX_cache genblk5[6] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+50241,"VX_cache genblk5[6] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+50249,"VX_cache genblk5[6] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+50257,"VX_cache genblk5[6] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+50289,"VX_cache genblk5[6] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+50241,"VX_cache genblk5[6] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+50249,"VX_cache genblk5[6] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+50257,"VX_cache genblk5[6] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+50289,"VX_cache genblk5[6] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+48769,"VX_cache genblk5[6] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+50321,"VX_cache genblk5[6] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+50329,"VX_cache genblk5[6] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+16785,"VX_cache genblk5[6] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+2073,"VX_cache genblk5[6] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+16793,"VX_cache genblk5[6] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+16801,"VX_cache genblk5[6] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[6] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+2073,"VX_cache genblk5[6] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+16793,"VX_cache genblk5[6] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+1553,"VX_cache genblk5[6] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+16809,"VX_cache genblk5[6] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+50321,"VX_cache genblk5[6] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+48761,"VX_cache genblk5[6] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+50337,"VX_cache genblk5[6] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+50337,"VX_cache genblk5[6] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+16889,"VX_cache genblk5[6] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+1633,"VX_cache genblk5[6] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+50345+i*10,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+50985,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+51065,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+51145,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+51153,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+51161,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+50321,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+48761,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+51169,"VX_cache genblk5[6] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+16897,"VX_cache genblk5[6] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+16897,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+50233,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+15897,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+15889,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+16905,"VX_cache genblk5[6] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[6] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[6] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+16025,"VX_cache genblk5[6] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[6] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+16913,"VX_cache genblk5[6] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+51177,"VX_cache genblk5[6] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+51177,"VX_cache genblk5[6] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[6] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank tag_data_access reset", false,-1); - vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access stall", false,-1); - vcdp->declBit(c+16409,"VX_cache genblk5[6] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+16417,"VX_cache genblk5[6] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+15977,"VX_cache genblk5[6] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+16473,"VX_cache genblk5[6] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+16449,"VX_cache genblk5[6] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+16985,"VX_cache genblk5[6] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+16993,"VX_cache genblk5[6] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+17001,"VX_cache genblk5[6] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+16385,"VX_cache genblk5[6] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+16393,"VX_cache genblk5[6] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+17033,"VX_cache genblk5[6] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+16289,"VX_cache genblk5[6] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+16297,"VX_cache genblk5[6] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+16329,"VX_cache genblk5[6] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+16337,"VX_cache genblk5[6] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+16345,"VX_cache genblk5[6] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+16353,"VX_cache genblk5[6] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+16401,"VX_cache genblk5[6] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+16425,"VX_cache genblk5[6] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+16433,"VX_cache genblk5[6] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+17041+i*1,"VX_cache genblk5[6] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+17049+i*1,"VX_cache genblk5[6] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+17057+i*1,"VX_cache genblk5[6] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+17065+i*1,"VX_cache genblk5[6] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+17073+i*4,"VX_cache genblk5[6] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+17105,"VX_cache genblk5[6] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+17113,"VX_cache genblk5[6] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+17121,"VX_cache genblk5[6] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+17129,"VX_cache genblk5[6] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+17137,"VX_cache genblk5[6] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+17169,"VX_cache genblk5[6] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+17177,"VX_cache genblk5[6] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+16353,"VX_cache genblk5[6] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+16329,"VX_cache genblk5[6] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+16297,"VX_cache genblk5[6] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+17185,"VX_cache genblk5[6] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+17193,"VX_cache genblk5[6] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+16337,"VX_cache genblk5[6] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+17225,"VX_cache genblk5[6] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+17233,"VX_cache genblk5[6] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+17241,"VX_cache genblk5[6] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+17249,"VX_cache genblk5[6] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+17257,"VX_cache genblk5[6] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+17193,"VX_cache genblk5[6] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+17265,"VX_cache genblk5[6] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+17225,"VX_cache genblk5[6] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+17273,"VX_cache genblk5[6] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+17281,"VX_cache genblk5[6] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+17289,"VX_cache genblk5[6] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+17297,"VX_cache genblk5[6] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+17305,"VX_cache genblk5[6] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+17313,"VX_cache genblk5[6] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+17321,"VX_cache genblk5[6] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+17329,"VX_cache genblk5[6] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[6] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+17105,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+17113,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+17121,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+17129,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+17137,"VX_cache genblk5[6] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+17225,"VX_cache genblk5[6] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+17185,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+17241,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+16977,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+17249,"VX_cache genblk5[6] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+17193,"VX_cache genblk5[6] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+16337,"VX_cache genblk5[6] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+51241,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+51273,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+51305,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+51337,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+51369,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+51401,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+51433,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+51465,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+51497,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+51529,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+51561,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+51593,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+51625,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+51657,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+51689,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+51721,"VX_cache genblk5[6] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+51753+i*1,"VX_cache genblk5[6] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+51881,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+51889,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+51897,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+51905,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+51913,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+51921,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+51929,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+51937,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+51945,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+51953,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+51961,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+51969,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+51977,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+51985,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+51993,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+52001,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+52009,"VX_cache genblk5[6] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+52017,"VX_cache genblk5[6] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+17337,"VX_cache genblk5[6] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+52025,"VX_cache genblk5[6] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+52033,"VX_cache genblk5[6] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+16025,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+17345,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+17345,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+52041,"VX_cache genblk5[6] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[6] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[6] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+16025,"VX_cache genblk5[6] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[6] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+17393,"VX_cache genblk5[6] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+52089,"VX_cache genblk5[6] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+52089,"VX_cache genblk5[6] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[6] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58849,"VX_cache genblk5[6] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[6] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[6] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[6] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+16521,"VX_cache genblk5[6] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+16529,"VX_cache genblk5[6] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19913,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+48929,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+48937,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+48873,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+48881,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+48897,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+48905,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+16489,"VX_cache genblk5[6] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+49041,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+49049,"VX_cache genblk5[6] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+48785,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+48793,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+16985,"VX_cache genblk5[6] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+16473,"VX_cache genblk5[6] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+15961,"VX_cache genblk5[6] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+15937,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+15945,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+48809,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+48817,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+48825,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+48801,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+48833,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+15953,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+48849,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+48857,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+48865,"VX_cache genblk5[6] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+52169+i*3,"VX_cache genblk5[6] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+52553,"VX_cache genblk5[6] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+52657,"VX_cache genblk5[6] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+52665,"VX_cache genblk5[6] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+52673,"VX_cache genblk5[6] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+52681,"VX_cache genblk5[6] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+52689,"VX_cache genblk5[6] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+52697,"VX_cache genblk5[6] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+52705,"VX_cache genblk5[6] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+52689,"VX_cache genblk5[6] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+17473,"VX_cache genblk5[6] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+17481,"VX_cache genblk5[6] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+17489,"VX_cache genblk5[6] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+15945,"VX_cache genblk5[6] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+52673,"VX_cache genblk5[6] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+17497,"VX_cache genblk5[6] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+17505,"VX_cache genblk5[6] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+17513,"VX_cache genblk5[6] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+17521,"VX_cache genblk5[6] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+17529,"VX_cache genblk5[6] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+17537,"VX_cache genblk5[6] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[6] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[6] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank cwb_queue reset", false,-1); - vcdp->declBit(c+16537,"VX_cache genblk5[6] bank cwb_queue push", false,-1); - vcdp->declBit(c+2057,"VX_cache genblk5[6] bank cwb_queue pop", false,-1); - vcdp->declArray(c+17545,"VX_cache genblk5[6] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+17569,"VX_cache genblk5[6] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+49089,"VX_cache genblk5[6] bank cwb_queue empty", false,-1); - vcdp->declBit(c+49097,"VX_cache genblk5[6] bank cwb_queue full", false,-1); - vcdp->declBus(c+52713,"VX_cache genblk5[6] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+52713,"VX_cache genblk5[6] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+1641,"VX_cache genblk5[6] bank cwb_queue reading", false,-1); - vcdp->declBit(c+17593,"VX_cache genblk5[6] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+52721+i*3,"VX_cache genblk5[6] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+52913,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+52937,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+52961,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+52969,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+52977,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+49089,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+49097,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+52985,"VX_cache genblk5[6] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[6] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[6] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[6] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[6] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[6] bank dwb_queue reset", false,-1); - vcdp->declBit(c+16561,"VX_cache genblk5[6] bank dwb_queue push", false,-1); - vcdp->declBit(c+2065,"VX_cache genblk5[6] bank dwb_queue pop", false,-1); - vcdp->declArray(c+17601,"VX_cache genblk5[6] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+17657,"VX_cache genblk5[6] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+49105,"VX_cache genblk5[6] bank dwb_queue empty", false,-1); - vcdp->declBit(c+49113,"VX_cache genblk5[6] bank dwb_queue full", false,-1); - vcdp->declBus(c+52993,"VX_cache genblk5[6] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+52993,"VX_cache genblk5[6] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+1649,"VX_cache genblk5[6] bank dwb_queue reading", false,-1); - vcdp->declBit(c+17713,"VX_cache genblk5[6] bank dwb_queue writing", false,-1); - {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+53001+i*7,"VX_cache genblk5[6] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+53225,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+53281,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+53337,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+53345,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+53353,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+49105,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+49113,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+53361,"VX_cache genblk5[6] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58641,"VX_cache genblk5[7] bank CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58857,"VX_cache genblk5[7] bank BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58649,"VX_cache genblk5[7] bank CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank DFPQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank SNRQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank CWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank DWBQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank DFQQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank DRAM_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[7] bank SNOOP_FORWARDING", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[7] bank CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[7] bank SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank reset", false,-1); - vcdp->declBus(c+257,"VX_cache genblk5[7] bank core_req_valid", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[7] bank core_req_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[7] bank core_req_byteen", false,-1, 15,0); - vcdp->declArray(c+58049,"VX_cache genblk5[7] bank core_req_addr", false,-1, 119,0); - vcdp->declArray(c+58081,"VX_cache genblk5[7] bank core_req_data", false,-1, 127,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[7] bank core_req_tag", false,-1, 41,0); - vcdp->declBit(c+19969,"VX_cache genblk5[7] bank core_req_ready", false,-1); - vcdp->declBit(c+19937,"VX_cache genblk5[7] bank core_rsp_valid", false,-1); - vcdp->declBus(c+3569,"VX_cache genblk5[7] bank core_rsp_tid", false,-1, 1,0); - vcdp->declBus(c+3577,"VX_cache genblk5[7] bank core_rsp_data", false,-1, 31,0); - vcdp->declQuad(c+3585,"VX_cache genblk5[7] bank core_rsp_tag", false,-1, 41,0); - vcdp->declBit(c+265,"VX_cache genblk5[7] bank core_rsp_ready", false,-1); - vcdp->declBit(c+3601,"VX_cache genblk5[7] bank dram_fill_req_valid", false,-1); - vcdp->declBus(c+19953,"VX_cache genblk5[7] bank dram_fill_req_addr", false,-1, 24,0); - vcdp->declBit(c+19649,"VX_cache genblk5[7] bank dram_fill_req_ready", false,-1); - vcdp->declBit(c+58609,"VX_cache genblk5[7] bank dram_fill_rsp_valid", false,-1); - vcdp->declArray(c+58289,"VX_cache genblk5[7] bank dram_fill_rsp_data", false,-1, 127,0); - vcdp->declBus(c+58489,"VX_cache genblk5[7] bank dram_fill_rsp_addr", false,-1, 24,0); - vcdp->declBit(c+19945,"VX_cache genblk5[7] bank dram_fill_rsp_ready", false,-1); - vcdp->declBit(c+3609,"VX_cache genblk5[7] bank dram_wb_req_valid", false,-1); - vcdp->declBus(c+3617,"VX_cache genblk5[7] bank dram_wb_req_byteen", false,-1, 15,0); - vcdp->declBus(c+3625,"VX_cache genblk5[7] bank dram_wb_req_addr", false,-1, 24,0); - vcdp->declArray(c+3633,"VX_cache genblk5[7] bank dram_wb_req_data", false,-1, 127,0); - vcdp->declBit(c+273,"VX_cache genblk5[7] bank dram_wb_req_ready", false,-1); - vcdp->declBit(c+58617,"VX_cache genblk5[7] bank snp_req_valid", false,-1); - vcdp->declBus(c+58505,"VX_cache genblk5[7] bank snp_req_addr", false,-1, 24,0); - vcdp->declBit(c+58353,"VX_cache genblk5[7] bank snp_req_invalidate", false,-1); - vcdp->declBus(c+58361,"VX_cache genblk5[7] bank snp_req_tag", false,-1, 27,0); - vcdp->declBit(c+19961,"VX_cache genblk5[7] bank snp_req_ready", false,-1); - vcdp->declBit(c+3665,"VX_cache genblk5[7] bank snp_rsp_valid", false,-1); - vcdp->declBus(c+3673,"VX_cache genblk5[7] bank snp_rsp_tag", false,-1, 27,0); - vcdp->declBit(c+281,"VX_cache genblk5[7] bank snp_rsp_ready", false,-1); - vcdp->declBit(c+17721,"VX_cache genblk5[7] bank snrq_pop", false,-1); - vcdp->declBit(c+53369,"VX_cache genblk5[7] bank snrq_empty", false,-1); - vcdp->declBit(c+53377,"VX_cache genblk5[7] bank snrq_full", false,-1); - vcdp->declBus(c+17729,"VX_cache genblk5[7] bank snrq_addr_st0", false,-1, 24,0); - vcdp->declBit(c+17737,"VX_cache genblk5[7] bank snrq_invalidate_st0", false,-1); - vcdp->declBus(c+17745,"VX_cache genblk5[7] bank snrq_tag_st0", false,-1, 27,0); - vcdp->declBit(c+17753,"VX_cache genblk5[7] bank dfpq_pop", false,-1); - vcdp->declBit(c+53385,"VX_cache genblk5[7] bank dfpq_empty", false,-1); - vcdp->declBit(c+53393,"VX_cache genblk5[7] bank dfpq_full", false,-1); - vcdp->declBus(c+17761,"VX_cache genblk5[7] bank dfpq_addr_st0", false,-1, 24,0); - vcdp->declArray(c+17769,"VX_cache genblk5[7] bank dfpq_filldata_st0", false,-1, 127,0); - vcdp->declBit(c+17801,"VX_cache genblk5[7] bank reqq_pop", false,-1); - vcdp->declBit(c+2081,"VX_cache genblk5[7] bank reqq_push", false,-1); - vcdp->declBit(c+17809,"VX_cache genblk5[7] bank reqq_empty", false,-1); - vcdp->declBit(c+53401,"VX_cache genblk5[7] bank reqq_full", false,-1); - vcdp->declBit(c+17817,"VX_cache genblk5[7] bank reqq_req_st0", false,-1); - vcdp->declBus(c+17825,"VX_cache genblk5[7] bank reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+17833,"VX_cache genblk5[7] bank reqq_req_rw_st0", false,-1); - vcdp->declBus(c+17841,"VX_cache genblk5[7] bank reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+17849,"VX_cache genblk5[7] bank reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+17857,"VX_cache genblk5[7] bank reqq_req_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+17865,"VX_cache genblk5[7] bank mrvq_pop", false,-1); - vcdp->declBit(c+53425,"VX_cache genblk5[7] bank mrvq_full", false,-1); - vcdp->declBit(c+53433,"VX_cache genblk5[7] bank mrvq_stop", false,-1); - vcdp->declBit(c+17873,"VX_cache genblk5[7] bank mrvq_valid_st0", false,-1); - vcdp->declBus(c+53441,"VX_cache genblk5[7] bank mrvq_tid_st0", false,-1, 1,0); - vcdp->declBus(c+53449,"VX_cache genblk5[7] bank mrvq_addr_st0", false,-1, 24,0); - vcdp->declBus(c+53457,"VX_cache genblk5[7] bank mrvq_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+53465,"VX_cache genblk5[7] bank mrvq_writeword_st0", false,-1, 31,0); - vcdp->declQuad(c+53473,"VX_cache genblk5[7] bank mrvq_tag_st0", false,-1, 41,0); - vcdp->declBit(c+17881,"VX_cache genblk5[7] bank mrvq_rw_st0", false,-1); - vcdp->declBus(c+53489,"VX_cache genblk5[7] bank mrvq_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+53497,"VX_cache genblk5[7] bank mrvq_is_snp_st0", false,-1); - vcdp->declBit(c+53505,"VX_cache genblk5[7] bank mrvq_snp_invalidate_st0", false,-1); - vcdp->declBit(c+17889,"VX_cache genblk5[7] bank mrvq_pending_hazard_st1e", false,-1); - vcdp->declBit(c+17897,"VX_cache genblk5[7] bank st2_pending_hazard_st1e", false,-1); - vcdp->declBit(c+17905,"VX_cache genblk5[7] bank force_request_miss_st1e", false,-1); - vcdp->declBus(c+53513,"VX_cache genblk5[7] bank miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+53521,"VX_cache genblk5[7] bank miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+53537,"VX_cache genblk5[7] bank miss_add_rw", false,-1); - vcdp->declBus(c+53545,"VX_cache genblk5[7] bank miss_add_byteen", false,-1, 3,0); - vcdp->declBus(c+19953,"VX_cache genblk5[7] bank addr_st2", false,-1, 24,0); - vcdp->declBit(c+53553,"VX_cache genblk5[7] bank is_fill_st2", false,-1); - vcdp->declBit(c+17913,"VX_cache genblk5[7] bank recover_mrvq_state_st2", false,-1); - vcdp->declBit(c+17921,"VX_cache genblk5[7] bank mrvq_push_stall", false,-1); - vcdp->declBit(c+17929,"VX_cache genblk5[7] bank cwbq_push_stall", false,-1); - vcdp->declBit(c+17937,"VX_cache genblk5[7] bank dwbq_push_stall", false,-1); - vcdp->declBit(c+17945,"VX_cache genblk5[7] bank dram_fill_req_stall", false,-1); - vcdp->declBit(c+17953,"VX_cache genblk5[7] bank stall_bank_pipe", false,-1); - vcdp->declBit(c+17961,"VX_cache genblk5[7] bank is_fill_in_pipe", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+17969+i*1,"VX_cache genblk5[7] bank is_fill_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+17977+i*1,"VX_cache genblk5[7] bank going_to_write_st1", true,(i+0));}} - vcdp->declBus(c+58753,"VX_cache genblk5[7] bank j", false,-1, 31,0); - vcdp->declBit(c+17873,"VX_cache genblk5[7] bank mrvq_pop_unqual", false,-1); - vcdp->declBit(c+17985,"VX_cache genblk5[7] bank dfpq_pop_unqual", false,-1); - vcdp->declBit(c+17993,"VX_cache genblk5[7] bank reqq_pop_unqual", false,-1); - vcdp->declBit(c+18001,"VX_cache genblk5[7] bank snrq_pop_unqual", false,-1); - vcdp->declBit(c+17985,"VX_cache genblk5[7] bank qual_is_fill_st0", false,-1); - vcdp->declBit(c+18009,"VX_cache genblk5[7] bank qual_valid_st0", false,-1); - vcdp->declBus(c+18017,"VX_cache genblk5[7] bank qual_addr_st0", false,-1, 24,0); - vcdp->declBus(c+18025,"VX_cache genblk5[7] bank qual_wsel_st0", false,-1, 1,0); - vcdp->declBit(c+17873,"VX_cache genblk5[7] bank qual_is_mrvq_st0", false,-1); - vcdp->declBus(c+18033,"VX_cache genblk5[7] bank qual_writeword_st0", false,-1, 31,0); - vcdp->declArray(c+18041,"VX_cache genblk5[7] bank qual_writedata_st0", false,-1, 127,0); - vcdp->declQuad(c+18073,"VX_cache genblk5[7] bank qual_inst_meta_st0", false,-1, 48,0); - vcdp->declBit(c+18089,"VX_cache genblk5[7] bank qual_going_to_write_st0", false,-1); - vcdp->declBit(c+18097,"VX_cache genblk5[7] bank qual_is_snp_st0", false,-1); - vcdp->declBit(c+18105,"VX_cache genblk5[7] bank qual_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+18113+i*1,"VX_cache genblk5[7] bank valid_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+18121+i*1,"VX_cache genblk5[7] bank addr_st1", true,(i+0), 24,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+18129+i*1,"VX_cache genblk5[7] bank wsel_st1", true,(i+0), 1,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+18137+i*1,"VX_cache genblk5[7] bank writeword_st1", true,(i+0), 31,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declQuad(c+18145+i*2,"VX_cache genblk5[7] bank inst_meta_st1", true,(i+0), 48,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+18161+i*4,"VX_cache genblk5[7] bank writedata_st1", true,(i+0), 127,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+18193+i*1,"VX_cache genblk5[7] bank is_snp_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+18201+i*1,"VX_cache genblk5[7] bank snp_invalidate_st1", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+18209+i*1,"VX_cache genblk5[7] bank is_mrvq_st1", true,(i+0));}} - vcdp->declBus(c+18217,"VX_cache genblk5[7] bank readword_st1e", false,-1, 31,0); - vcdp->declArray(c+18225,"VX_cache genblk5[7] bank readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+18257,"VX_cache genblk5[7] bank readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+18265,"VX_cache genblk5[7] bank miss_st1e", false,-1); - vcdp->declBit(c+18273,"VX_cache genblk5[7] bank dirty_st1e", false,-1); - vcdp->declBus(c+18281,"VX_cache genblk5[7] bank dirtyb_st1e", false,-1, 15,0); - vcdp->declQuad(c+18289,"VX_cache genblk5[7] bank tag_st1e", false,-1, 41,0); - vcdp->declBus(c+18305,"VX_cache genblk5[7] bank tid_st1e", false,-1, 1,0); - vcdp->declBit(c+18313,"VX_cache genblk5[7] bank mem_rw_st1e", false,-1); - vcdp->declBus(c+18321,"VX_cache genblk5[7] bank mem_byteen_st1e", false,-1, 3,0); - vcdp->declBit(c+18329,"VX_cache genblk5[7] bank fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+18337,"VX_cache genblk5[7] bank is_snp_st1e", false,-1); - vcdp->declBit(c+18345,"VX_cache genblk5[7] bank snp_invalidate_st1e", false,-1); - vcdp->declBit(c+18353,"VX_cache genblk5[7] bank snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+18361,"VX_cache genblk5[7] bank mrvq_init_ready_state_st1e", false,-1); - vcdp->declBit(c+18369,"VX_cache genblk5[7] bank miss_add_because_miss", false,-1); - vcdp->declBit(c+18377,"VX_cache genblk5[7] bank valid_st1e", false,-1); - vcdp->declBit(c+18385,"VX_cache genblk5[7] bank is_mrvq_st1e", false,-1); - vcdp->declBit(c+18393,"VX_cache genblk5[7] bank mrvq_recover_ready_state_st1e", false,-1); - vcdp->declBus(c+18401,"VX_cache genblk5[7] bank addr_st1e", false,-1, 24,0); - vcdp->declBit(c+18409,"VX_cache genblk5[7] bank qual_valid_st1e_2", false,-1); - vcdp->declBit(c+18385,"VX_cache genblk5[7] bank is_mrvq_st1e_st2", false,-1); - vcdp->declBit(c+53561,"VX_cache genblk5[7] bank valid_st2", false,-1); - vcdp->declBus(c+53569,"VX_cache genblk5[7] bank wsel_st2", false,-1, 1,0); - vcdp->declBus(c+53577,"VX_cache genblk5[7] bank writeword_st2", false,-1, 31,0); - vcdp->declBus(c+53585,"VX_cache genblk5[7] bank readword_st2", false,-1, 31,0); - vcdp->declArray(c+53593,"VX_cache genblk5[7] bank readdata_st2", false,-1, 127,0); - vcdp->declBit(c+53625,"VX_cache genblk5[7] bank miss_st2", false,-1); - vcdp->declBit(c+53633,"VX_cache genblk5[7] bank dirty_st2", false,-1); - vcdp->declBus(c+53641,"VX_cache genblk5[7] bank dirtyb_st2", false,-1, 15,0); - vcdp->declQuad(c+53649,"VX_cache genblk5[7] bank inst_meta_st2", false,-1, 48,0); - vcdp->declBus(c+53665,"VX_cache genblk5[7] bank readtag_st2", false,-1, 20,0); - vcdp->declBit(c+53673,"VX_cache genblk5[7] bank fill_saw_dirty_st2", false,-1); - vcdp->declBit(c+53681,"VX_cache genblk5[7] bank is_snp_st2", false,-1); - vcdp->declBit(c+53689,"VX_cache genblk5[7] bank snp_invalidate_st2", false,-1); - vcdp->declBit(c+53697,"VX_cache genblk5[7] bank snp_to_mrvq_st2", false,-1); - vcdp->declBit(c+53705,"VX_cache genblk5[7] bank is_mrvq_st2", false,-1); - vcdp->declBit(c+18417,"VX_cache genblk5[7] bank mrvq_init_ready_state_st2", false,-1); - vcdp->declBit(c+53713,"VX_cache genblk5[7] bank mrvq_recover_ready_state_st2", false,-1); - vcdp->declBit(c+53721,"VX_cache genblk5[7] bank mrvq_init_ready_state_unqual_st2", false,-1); - vcdp->declBit(c+18425,"VX_cache genblk5[7] bank mrvq_init_ready_state_hazard_st0_st1", false,-1); - vcdp->declBit(c+18433,"VX_cache genblk5[7] bank mrvq_init_ready_state_hazard_st1e_st1", false,-1); - vcdp->declBit(c+53697,"VX_cache genblk5[7] bank miss_add_because_pending", false,-1); - vcdp->declBit(c+18441,"VX_cache genblk5[7] bank miss_add_unqual", false,-1); - vcdp->declBit(c+18449,"VX_cache genblk5[7] bank miss_add", false,-1); - vcdp->declBus(c+19953,"VX_cache genblk5[7] bank miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+53569,"VX_cache genblk5[7] bank miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+53577,"VX_cache genblk5[7] bank miss_add_data", false,-1, 31,0); - vcdp->declBit(c+53681,"VX_cache genblk5[7] bank miss_add_is_snp", false,-1); - vcdp->declBit(c+53689,"VX_cache genblk5[7] bank miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+18457,"VX_cache genblk5[7] bank miss_add_is_mrvq", false,-1); - vcdp->declBit(c+18465,"VX_cache genblk5[7] bank cwbq_push", false,-1); - vcdp->declBit(c+2089,"VX_cache genblk5[7] bank cwbq_pop", false,-1); - vcdp->declBit(c+53729,"VX_cache genblk5[7] bank cwbq_empty", false,-1); - vcdp->declBit(c+53737,"VX_cache genblk5[7] bank cwbq_full", false,-1); - vcdp->declBit(c+18473,"VX_cache genblk5[7] bank cwbq_push_unqual", false,-1); - vcdp->declBus(c+53585,"VX_cache genblk5[7] bank cwbq_data", false,-1, 31,0); - vcdp->declBus(c+53513,"VX_cache genblk5[7] bank cwbq_tid", false,-1, 1,0); - vcdp->declQuad(c+53521,"VX_cache genblk5[7] bank cwbq_tag", false,-1, 41,0); - vcdp->declBit(c+18441,"VX_cache genblk5[7] bank dram_fill_req_fast", false,-1); - vcdp->declBit(c+18481,"VX_cache genblk5[7] bank dram_fill_req_unqual", false,-1); - vcdp->declBit(c+18489,"VX_cache genblk5[7] bank dwbq_push", false,-1); - vcdp->declBit(c+2097,"VX_cache genblk5[7] bank dwbq_pop", false,-1); - vcdp->declBit(c+53745,"VX_cache genblk5[7] bank dwbq_empty", false,-1); - vcdp->declBit(c+53753,"VX_cache genblk5[7] bank dwbq_full", false,-1); - vcdp->declBit(c+18497,"VX_cache genblk5[7] bank dwbq_is_dwb_in", false,-1); - vcdp->declBit(c+18505,"VX_cache genblk5[7] bank dwbq_is_snp_in", false,-1); - vcdp->declBit(c+18513,"VX_cache genblk5[7] bank dwbq_is_dwb_out", false,-1); - vcdp->declBit(c+18521,"VX_cache genblk5[7] bank dwbq_is_snp_out", false,-1); - vcdp->declBit(c+18529,"VX_cache genblk5[7] bank dwbq_push_unqual", false,-1); - vcdp->declBus(c+53761,"VX_cache genblk5[7] bank dwbq_req_addr", false,-1, 24,0); - vcdp->declBus(c+53769,"VX_cache genblk5[7] bank snrq_tag_st2", false,-1, 27,0); - vcdp->declBit(c+1657,"VX_cache genblk5[7] bank dram_wb_req_fire", false,-1); - vcdp->declBit(c+1665,"VX_cache genblk5[7] bank snp_rsp_fire", false,-1); - vcdp->declBit(c+53777,"VX_cache genblk5[7] bank dwbq_dual_valid_sel", false,-1); - vcdp->declBus(c+58761,"VX_cache genblk5[7] bank snp_req_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank snp_req_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank snp_req_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank snp_req_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank snp_req_queue reset", false,-1); - vcdp->declBit(c+58617,"VX_cache genblk5[7] bank snp_req_queue push", false,-1); - vcdp->declBit(c+17721,"VX_cache genblk5[7] bank snp_req_queue pop", false,-1); - vcdp->declQuad(c+1673,"VX_cache genblk5[7] bank snp_req_queue data_in", false,-1, 53,0); - vcdp->declQuad(c+18537,"VX_cache genblk5[7] bank snp_req_queue data_out", false,-1, 53,0); - vcdp->declBit(c+53369,"VX_cache genblk5[7] bank snp_req_queue empty", false,-1); - vcdp->declBit(c+53377,"VX_cache genblk5[7] bank snp_req_queue full", false,-1); - vcdp->declBus(c+53785,"VX_cache genblk5[7] bank snp_req_queue size", false,-1, 4,0); - vcdp->declBus(c+53785,"VX_cache genblk5[7] bank snp_req_queue size_r", false,-1, 4,0); - vcdp->declBit(c+18553,"VX_cache genblk5[7] bank snp_req_queue reading", false,-1); - vcdp->declBit(c+1689,"VX_cache genblk5[7] bank snp_req_queue writing", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declQuad(c+53793+i*2,"VX_cache genblk5[7] bank snp_req_queue genblk3 data", true,(i+0), 53,0);}} - vcdp->declQuad(c+54049,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 head_r", false,-1, 53,0); - vcdp->declQuad(c+54065,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 curr_r", false,-1, 53,0); - vcdp->declBus(c+54081,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+54089,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+54097,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+53369,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+53377,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+54105,"VX_cache genblk5[7] bank snp_req_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58769,"VX_cache genblk5[7] bank dfp_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank dfp_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank dfp_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank dfp_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank dfp_queue reset", false,-1); - vcdp->declBit(c+58609,"VX_cache genblk5[7] bank dfp_queue push", false,-1); - vcdp->declBit(c+17753,"VX_cache genblk5[7] bank dfp_queue pop", false,-1); - vcdp->declArray(c+1697,"VX_cache genblk5[7] bank dfp_queue data_in", false,-1, 152,0); - vcdp->declArray(c+18561,"VX_cache genblk5[7] bank dfp_queue data_out", false,-1, 152,0); - vcdp->declBit(c+53385,"VX_cache genblk5[7] bank dfp_queue empty", false,-1); - vcdp->declBit(c+53393,"VX_cache genblk5[7] bank dfp_queue full", false,-1); - vcdp->declBus(c+54113,"VX_cache genblk5[7] bank dfp_queue size", false,-1, 4,0); - vcdp->declBus(c+54113,"VX_cache genblk5[7] bank dfp_queue size_r", false,-1, 4,0); - vcdp->declBit(c+18601,"VX_cache genblk5[7] bank dfp_queue reading", false,-1); - vcdp->declBit(c+1737,"VX_cache genblk5[7] bank dfp_queue writing", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+54121+i*5,"VX_cache genblk5[7] bank dfp_queue genblk3 data", true,(i+0), 152,0);}} - vcdp->declArray(c+54761,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 head_r", false,-1, 152,0); - vcdp->declArray(c+54801,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 curr_r", false,-1, 152,0); - vcdp->declBus(c+54841,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 wr_ptr_r", false,-1, 3,0); - vcdp->declBus(c+54849,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 rd_ptr_r", false,-1, 3,0); - vcdp->declBus(c+54857,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 3,0); - vcdp->declBit(c+53385,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+53393,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+54865,"VX_cache genblk5[7] bank dfp_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank core_req_arb CREQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[7] bank core_req_arb CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank core_req_arb CORE_TAG_ID_BITS", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank core_req_arb clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank core_req_arb reset", false,-1); - vcdp->declBit(c+2081,"VX_cache genblk5[7] bank core_req_arb reqq_push", false,-1); - vcdp->declBus(c+257,"VX_cache genblk5[7] bank core_req_arb bank_valids", false,-1, 3,0); - vcdp->declBus(c+58033,"VX_cache genblk5[7] bank core_req_arb bank_rw", false,-1, 3,0); - vcdp->declBus(c+58041,"VX_cache genblk5[7] bank core_req_arb bank_byteen", false,-1, 15,0); - vcdp->declArray(c+58081,"VX_cache genblk5[7] bank core_req_arb bank_writedata", false,-1, 127,0); - vcdp->declArray(c+58049,"VX_cache genblk5[7] bank core_req_arb bank_addr", false,-1, 119,0); - vcdp->declQuad(c+58113,"VX_cache genblk5[7] bank core_req_arb bank_tag", false,-1, 41,0); - vcdp->declBit(c+17801,"VX_cache genblk5[7] bank core_req_arb reqq_pop", false,-1); - vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb reqq_req_st0", false,-1); - vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb reqq_req_tid_st0", false,-1, 1,0); - vcdp->declBit(c+17833,"VX_cache genblk5[7] bank core_req_arb reqq_req_rw_st0", false,-1); - vcdp->declBus(c+17841,"VX_cache genblk5[7] bank core_req_arb reqq_req_byteen_st0", false,-1, 3,0); - vcdp->declBus(c+17849,"VX_cache genblk5[7] bank core_req_arb reqq_req_addr_st0", false,-1, 29,0); - vcdp->declBus(c+17857,"VX_cache genblk5[7] bank core_req_arb reqq_req_writedata_st0", false,-1, 31,0); - vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank core_req_arb reqq_req_tag_st0", false,-1, 41,0); - vcdp->declBit(c+17809,"VX_cache genblk5[7] bank core_req_arb reqq_empty", false,-1); - vcdp->declBit(c+53401,"VX_cache genblk5[7] bank core_req_arb reqq_full", false,-1); - vcdp->declBus(c+18609,"VX_cache genblk5[7] bank core_req_arb out_per_valids", false,-1, 3,0); - vcdp->declBus(c+18617,"VX_cache genblk5[7] bank core_req_arb out_per_rw", false,-1, 3,0); - vcdp->declBus(c+18625,"VX_cache genblk5[7] bank core_req_arb out_per_byteen", false,-1, 15,0); - vcdp->declArray(c+18633,"VX_cache genblk5[7] bank core_req_arb out_per_addr", false,-1, 119,0); - vcdp->declArray(c+18665,"VX_cache genblk5[7] bank core_req_arb out_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+18697,"VX_cache genblk5[7] bank core_req_arb out_per_tag", false,-1, 41,0); - vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb use_per_valids", false,-1, 3,0); - vcdp->declBus(c+54881,"VX_cache genblk5[7] bank core_req_arb use_per_rw", false,-1, 3,0); - vcdp->declBus(c+54889,"VX_cache genblk5[7] bank core_req_arb use_per_byteen", false,-1, 15,0); - vcdp->declArray(c+54897,"VX_cache genblk5[7] bank core_req_arb use_per_addr", false,-1, 119,0); - vcdp->declArray(c+54929,"VX_cache genblk5[7] bank core_req_arb use_per_writedata", false,-1, 127,0); - vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank core_req_arb use_per_tag", false,-1, 41,0); - vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb qual_valids", false,-1, 3,0); - vcdp->declBus(c+54881,"VX_cache genblk5[7] bank core_req_arb qual_rw", false,-1, 3,0); - vcdp->declBus(c+54889,"VX_cache genblk5[7] bank core_req_arb qual_byteen", false,-1, 15,0); - vcdp->declArray(c+54897,"VX_cache genblk5[7] bank core_req_arb qual_addr", false,-1, 119,0); - vcdp->declArray(c+54929,"VX_cache genblk5[7] bank core_req_arb qual_writedata", false,-1, 127,0); - vcdp->declQuad(c+53409,"VX_cache genblk5[7] bank core_req_arb qual_tag", false,-1, 41,0); - vcdp->declBit(c+54961,"VX_cache genblk5[7] bank core_req_arb o_empty", false,-1); - vcdp->declBit(c+54969,"VX_cache genblk5[7] bank core_req_arb use_empty", false,-1); - vcdp->declBit(c+18713,"VX_cache genblk5[7] bank core_req_arb out_empty", false,-1); - vcdp->declBit(c+2105,"VX_cache genblk5[7] bank core_req_arb push_qual", false,-1); - vcdp->declBit(c+18721,"VX_cache genblk5[7] bank core_req_arb pop_qual", false,-1); - vcdp->declBus(c+18729,"VX_cache genblk5[7] bank core_req_arb real_out_per_valids", false,-1, 3,0); - vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb qual_request_index", false,-1, 1,0); - vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb qual_has_request", false,-1); - vcdp->declBus(c+58777,"VX_cache genblk5[7] bank core_req_arb reqq_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank core_req_arb reqq_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank core_req_arb reqq_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank core_req_arb reqq_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank core_req_arb reqq_queue reset", false,-1); - vcdp->declBit(c+2105,"VX_cache genblk5[7] bank core_req_arb reqq_queue push", false,-1); - vcdp->declBit(c+18721,"VX_cache genblk5[7] bank core_req_arb reqq_queue pop", false,-1); - vcdp->declArray(c+1745,"VX_cache genblk5[7] bank core_req_arb reqq_queue data_in", false,-1, 313,0); - vcdp->declArray(c+18737,"VX_cache genblk5[7] bank core_req_arb reqq_queue data_out", false,-1, 313,0); - vcdp->declBit(c+54961,"VX_cache genblk5[7] bank core_req_arb reqq_queue empty", false,-1); - vcdp->declBit(c+53401,"VX_cache genblk5[7] bank core_req_arb reqq_queue full", false,-1); - vcdp->declBus(c+54977,"VX_cache genblk5[7] bank core_req_arb reqq_queue size", false,-1, 3,0); - vcdp->declBus(c+54977,"VX_cache genblk5[7] bank core_req_arb reqq_queue size_r", false,-1, 3,0); - vcdp->declBit(c+18817,"VX_cache genblk5[7] bank core_req_arb reqq_queue reading", false,-1); - vcdp->declBit(c+1825,"VX_cache genblk5[7] bank core_req_arb reqq_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+54985+i*10,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 data", true,(i+0), 313,0);}} - vcdp->declArray(c+55625,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 head_r", false,-1, 313,0); - vcdp->declArray(c+55705,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 curr_r", false,-1, 313,0); - vcdp->declBus(c+55785,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+55793,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+55801,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+54961,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+53401,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+55809,"VX_cache genblk5[7] bank core_req_arb reqq_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb sel_bank N", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank core_req_arb sel_bank clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank core_req_arb sel_bank reset", false,-1); - vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+18825,"VX_cache genblk5[7] bank core_req_arb sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb sel_bank grant_valid", false,-1); - vcdp->declBus(c+18825,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 grant_onehot_r", false,-1, 3,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder N", false,-1, 31,0); - vcdp->declBus(c+54873,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+17825,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+17817,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder valid_out", false,-1); - vcdp->declBus(c+18833,"VX_cache genblk5[7] bank core_req_arb sel_bank genblk2 priority_encoder i", false,-1, 31,0); - vcdp->declBus(c+58785,"VX_cache genblk5[7] bank s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[7] bank s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank s0_1_c0 reset", false,-1); - vcdp->declBit(c+17953,"VX_cache genblk5[7] bank s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[7] bank s0_1_c0 flush", false,-1); - vcdp->declArray(c+18841,"VX_cache genblk5[7] bank s0_1_c0 in", false,-1, 241,0); - vcdp->declArray(c+55817,"VX_cache genblk5[7] bank s0_1_c0 out", false,-1, 241,0); - vcdp->declArray(c+55817,"VX_cache genblk5[7] bank s0_1_c0 value", false,-1, 241,0); - vcdp->declBus(c+58649,"VX_cache genblk5[7] bank tag_data_access CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank tag_data_access BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank tag_data_access NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank tag_data_access WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access STAGE_1_CYCLES", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access WRITE_ENABLE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access DRAM_ENABLE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank tag_data_access clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank tag_data_access reset", false,-1); - vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access stall", false,-1); - vcdp->declBit(c+18337,"VX_cache genblk5[7] bank tag_data_access is_snp_st1e", false,-1); - vcdp->declBit(c+18345,"VX_cache genblk5[7] bank tag_data_access snp_invalidate_st1e", false,-1); - vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access stall_bank_pipe", false,-1); - vcdp->declBit(c+17905,"VX_cache genblk5[7] bank tag_data_access force_request_miss_st1e", false,-1); - vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access readaddr_st10", false,-1, 3,0); - vcdp->declBus(c+18401,"VX_cache genblk5[7] bank tag_data_access writeaddr_st1e", false,-1, 24,0); - vcdp->declBit(c+18377,"VX_cache genblk5[7] bank tag_data_access valid_req_st1e", false,-1); - vcdp->declBit(c+18913,"VX_cache genblk5[7] bank tag_data_access writefill_st1e", false,-1); - vcdp->declBus(c+18921,"VX_cache genblk5[7] bank tag_data_access writeword_st1e", false,-1, 31,0); - vcdp->declArray(c+18929,"VX_cache genblk5[7] bank tag_data_access writedata_st1e", false,-1, 127,0); - vcdp->declBit(c+18313,"VX_cache genblk5[7] bank tag_data_access mem_rw_st1e", false,-1); - vcdp->declBus(c+18321,"VX_cache genblk5[7] bank tag_data_access mem_byteen_st1e", false,-1, 3,0); - vcdp->declBus(c+18961,"VX_cache genblk5[7] bank tag_data_access wordsel_st1e", false,-1, 1,0); - vcdp->declBus(c+18217,"VX_cache genblk5[7] bank tag_data_access readword_st1e", false,-1, 31,0); - vcdp->declArray(c+18225,"VX_cache genblk5[7] bank tag_data_access readdata_st1e", false,-1, 127,0); - vcdp->declBus(c+18257,"VX_cache genblk5[7] bank tag_data_access readtag_st1e", false,-1, 20,0); - vcdp->declBit(c+18265,"VX_cache genblk5[7] bank tag_data_access miss_st1e", false,-1); - vcdp->declBit(c+18273,"VX_cache genblk5[7] bank tag_data_access dirty_st1e", false,-1); - vcdp->declBus(c+18281,"VX_cache genblk5[7] bank tag_data_access dirtyb_st1e", false,-1, 15,0); - vcdp->declBit(c+18329,"VX_cache genblk5[7] bank tag_data_access fill_saw_dirty_st1e", false,-1); - vcdp->declBit(c+18353,"VX_cache genblk5[7] bank tag_data_access snp_to_mrvq_st1e", false,-1); - vcdp->declBit(c+18361,"VX_cache genblk5[7] bank tag_data_access mrvq_init_ready_state_st1e", false,-1); - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+18969+i*1,"VX_cache genblk5[7] bank tag_data_access read_valid_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBit(c+18977+i*1,"VX_cache genblk5[7] bank tag_data_access read_dirty_st1c", true,(i+0));}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+18985+i*1,"VX_cache genblk5[7] bank tag_data_access read_dirtyb_st1c", true,(i+0), 15,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declBus(c+18993+i*1,"VX_cache genblk5[7] bank tag_data_access read_tag_st1c", true,(i+0), 20,0);}} - {int i; for (i=0; i<1; i++) { - vcdp->declArray(c+19001+i*4,"VX_cache genblk5[7] bank tag_data_access read_data_st1c", true,(i+0), 127,0);}} - vcdp->declBit(c+19033,"VX_cache genblk5[7] bank tag_data_access qual_read_valid_st1", false,-1); - vcdp->declBit(c+19041,"VX_cache genblk5[7] bank tag_data_access qual_read_dirty_st1", false,-1); - vcdp->declBus(c+19049,"VX_cache genblk5[7] bank tag_data_access qual_read_dirtyb_st1", false,-1, 15,0); - vcdp->declBus(c+19057,"VX_cache genblk5[7] bank tag_data_access qual_read_tag_st1", false,-1, 20,0); - vcdp->declArray(c+19065,"VX_cache genblk5[7] bank tag_data_access qual_read_data_st1", false,-1, 127,0); - vcdp->declBit(c+19097,"VX_cache genblk5[7] bank tag_data_access use_read_valid_st1e", false,-1); - vcdp->declBit(c+19105,"VX_cache genblk5[7] bank tag_data_access use_read_dirty_st1e", false,-1); - vcdp->declBus(c+18281,"VX_cache genblk5[7] bank tag_data_access use_read_dirtyb_st1e", false,-1, 15,0); - vcdp->declBus(c+18257,"VX_cache genblk5[7] bank tag_data_access use_read_tag_st1e", false,-1, 20,0); - vcdp->declArray(c+18225,"VX_cache genblk5[7] bank tag_data_access use_read_data_st1e", false,-1, 127,0); - vcdp->declBus(c+19113,"VX_cache genblk5[7] bank tag_data_access use_write_enable", false,-1, 15,0); - vcdp->declArray(c+19121,"VX_cache genblk5[7] bank tag_data_access use_write_data", false,-1, 127,0); - vcdp->declBit(c+18265,"VX_cache genblk5[7] bank tag_data_access fill_sent", false,-1); - vcdp->declBit(c+19153,"VX_cache genblk5[7] bank tag_data_access invalidate_line", false,-1); - vcdp->declBit(c+19161,"VX_cache genblk5[7] bank tag_data_access tags_match", false,-1); - vcdp->declBit(c+19169,"VX_cache genblk5[7] bank tag_data_access real_writefill", false,-1); - vcdp->declBus(c+19177,"VX_cache genblk5[7] bank tag_data_access writetag_st1e", false,-1, 20,0); - vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access writeladdr_st1e", false,-1, 3,0); - vcdp->declBus(c+19185,"VX_cache genblk5[7] bank tag_data_access we", false,-1, 15,0); - vcdp->declArray(c+19121,"VX_cache genblk5[7] bank tag_data_access data_write", false,-1, 127,0); - vcdp->declBit(c+19193,"VX_cache genblk5[7] bank tag_data_access should_write", false,-1); - vcdp->declBit(c+19153,"VX_cache genblk5[7] bank tag_data_access snoop_hit_no_pending", false,-1); - vcdp->declBit(c+19201,"VX_cache genblk5[7] bank tag_data_access req_invalid", false,-1); - vcdp->declBit(c+19209,"VX_cache genblk5[7] bank tag_data_access req_miss", false,-1); - vcdp->declBit(c+19217,"VX_cache genblk5[7] bank tag_data_access real_miss", false,-1); - vcdp->declBit(c+19225,"VX_cache genblk5[7] bank tag_data_access force_core_miss", false,-1); - vcdp->declBit(c+19233,"VX_cache genblk5[7] bank tag_data_access genblk4[0] normal_write", false,-1); - vcdp->declBit(c+19241,"VX_cache genblk5[7] bank tag_data_access genblk4[1] normal_write", false,-1); - vcdp->declBit(c+19249,"VX_cache genblk5[7] bank tag_data_access genblk4[2] normal_write", false,-1); - vcdp->declBit(c+19257,"VX_cache genblk5[7] bank tag_data_access genblk4[3] normal_write", false,-1); - vcdp->declBus(c+58649,"VX_cache genblk5[7] bank tag_data_access tag_data_structure CACHE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank tag_data_access tag_data_structure BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank tag_data_access tag_data_structure NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank tag_data_access tag_data_structure WORD_SIZE", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank tag_data_access tag_data_structure clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank tag_data_access tag_data_structure reset", false,-1); - vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access tag_data_structure stall_bank_pipe", false,-1); - vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_addr", false,-1, 3,0); - vcdp->declBit(c+19033,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_valid", false,-1); - vcdp->declBit(c+19041,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_dirty", false,-1); - vcdp->declBus(c+19049,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_dirtyb", false,-1, 15,0); - vcdp->declBus(c+19057,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_tag", false,-1, 20,0); - vcdp->declArray(c+19065,"VX_cache genblk5[7] bank tag_data_access tag_data_structure read_data", false,-1, 127,0); - vcdp->declBit(c+19153,"VX_cache genblk5[7] bank tag_data_access tag_data_structure invalidate", false,-1); - vcdp->declBus(c+19113,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_enable", false,-1, 15,0); - vcdp->declBit(c+19169,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_fill", false,-1); - vcdp->declBus(c+18905,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_addr", false,-1, 3,0); - vcdp->declBus(c+19177,"VX_cache genblk5[7] bank tag_data_access tag_data_structure tag_index", false,-1, 20,0); - vcdp->declArray(c+19121,"VX_cache genblk5[7] bank tag_data_access tag_data_structure write_data", false,-1, 127,0); - vcdp->declBit(c+18265,"VX_cache genblk5[7] bank tag_data_access tag_data_structure fill_sent", false,-1); - vcdp->declArray(c+55881,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(0)", false,-1, 127,0); - vcdp->declArray(c+55913,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(1)", false,-1, 127,0); - vcdp->declArray(c+55945,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(2)", false,-1, 127,0); - vcdp->declArray(c+55977,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(3)", false,-1, 127,0); - vcdp->declArray(c+56009,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(4)", false,-1, 127,0); - vcdp->declArray(c+56041,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(5)", false,-1, 127,0); - vcdp->declArray(c+56073,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(6)", false,-1, 127,0); - vcdp->declArray(c+56105,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(7)", false,-1, 127,0); - vcdp->declArray(c+56137,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(8)", false,-1, 127,0); - vcdp->declArray(c+56169,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(9)", false,-1, 127,0); - vcdp->declArray(c+56201,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(10)", false,-1, 127,0); - vcdp->declArray(c+56233,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(11)", false,-1, 127,0); - vcdp->declArray(c+56265,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(12)", false,-1, 127,0); - vcdp->declArray(c+56297,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(13)", false,-1, 127,0); - vcdp->declArray(c+56329,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(14)", false,-1, 127,0); - vcdp->declArray(c+56361,"VX_cache genblk5[7] bank tag_data_access tag_data_structure data(15)", false,-1, 127,0); - {int i; for (i=0; i<16; i++) { - vcdp->declBus(c+56393+i*1,"VX_cache genblk5[7] bank tag_data_access tag_data_structure tag", true,(i+0), 20,0);}} - vcdp->declBus(c+56521,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(0)", false,-1, 15,0); - vcdp->declBus(c+56529,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(1)", false,-1, 15,0); - vcdp->declBus(c+56537,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(2)", false,-1, 15,0); - vcdp->declBus(c+56545,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(3)", false,-1, 15,0); - vcdp->declBus(c+56553,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(4)", false,-1, 15,0); - vcdp->declBus(c+56561,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(5)", false,-1, 15,0); - vcdp->declBus(c+56569,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(6)", false,-1, 15,0); - vcdp->declBus(c+56577,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(7)", false,-1, 15,0); - vcdp->declBus(c+56585,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(8)", false,-1, 15,0); - vcdp->declBus(c+56593,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(9)", false,-1, 15,0); - vcdp->declBus(c+56601,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(10)", false,-1, 15,0); - vcdp->declBus(c+56609,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(11)", false,-1, 15,0); - vcdp->declBus(c+56617,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(12)", false,-1, 15,0); - vcdp->declBus(c+56625,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(13)", false,-1, 15,0); - vcdp->declBus(c+56633,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(14)", false,-1, 15,0); - vcdp->declBus(c+56641,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirtyb(15)", false,-1, 15,0); - vcdp->declBus(c+56649,"VX_cache genblk5[7] bank tag_data_access tag_data_structure dirty", false,-1, 15,0); - vcdp->declBus(c+56657,"VX_cache genblk5[7] bank tag_data_access tag_data_structure valid", false,-1, 15,0); - vcdp->declBit(c+19265,"VX_cache genblk5[7] bank tag_data_access tag_data_structure do_write", false,-1); - vcdp->declBus(c+56665,"VX_cache genblk5[7] bank tag_data_access tag_data_structure i", false,-1, 31,0); - vcdp->declBus(c+56673,"VX_cache genblk5[7] bank tag_data_access tag_data_structure j", false,-1, 31,0); - vcdp->declBus(c+58793,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 N", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 reset", false,-1); - vcdp->declBit(c+17953,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 flush", false,-1); - vcdp->declArray(c+19273,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 in", false,-1, 166,0); - vcdp->declArray(c+19273,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 out", false,-1, 166,0); - vcdp->declArray(c+56681,"VX_cache genblk5[7] bank tag_data_access s0_1_c0 value", false,-1, 166,0); - vcdp->declBus(c+58801,"VX_cache genblk5[7] bank st_1e_2 N", false,-1, 31,0); - vcdp->declBus(c+58641,"VX_cache genblk5[7] bank st_1e_2 PASSTHRU", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank st_1e_2 clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank st_1e_2 reset", false,-1); - vcdp->declBit(c+17953,"VX_cache genblk5[7] bank st_1e_2 stall", false,-1); - vcdp->declBit(c+58721,"VX_cache genblk5[7] bank st_1e_2 flush", false,-1); - vcdp->declArray(c+19321,"VX_cache genblk5[7] bank st_1e_2 in", false,-1, 315,0); - vcdp->declArray(c+56729,"VX_cache genblk5[7] bank st_1e_2 out", false,-1, 315,0); - vcdp->declArray(c+56729,"VX_cache genblk5[7] bank st_1e_2 value", false,-1, 315,0); - vcdp->declBus(c+58641,"VX_cache genblk5[7] bank cache_miss_resrv CACHE_ID", false,-1, 31,0); - vcdp->declBus(c+58857,"VX_cache genblk5[7] bank cache_miss_resrv BANK_ID", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank cache_miss_resrv BANK_LINE_SIZE", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank cache_miss_resrv NUM_BANKS", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank cache_miss_resrv WORD_SIZE", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank cache_miss_resrv NUM_REQUESTS", false,-1, 31,0); - vcdp->declBus(c+58657,"VX_cache genblk5[7] bank cache_miss_resrv MRVQ_SIZE", false,-1, 31,0); - vcdp->declBus(c+58689,"VX_cache genblk5[7] bank cache_miss_resrv CORE_TAG_WIDTH", false,-1, 31,0); - vcdp->declBus(c+58697,"VX_cache genblk5[7] bank cache_miss_resrv SNP_REQ_TAG_WIDTH", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank cache_miss_resrv clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank cache_miss_resrv reset", false,-1); - vcdp->declBit(c+18449,"VX_cache genblk5[7] bank cache_miss_resrv miss_add", false,-1); - vcdp->declBit(c+18457,"VX_cache genblk5[7] bank cache_miss_resrv is_mrvq", false,-1); - vcdp->declBus(c+19953,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_addr", false,-1, 24,0); - vcdp->declBus(c+53569,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_wsel", false,-1, 1,0); - vcdp->declBus(c+53577,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_data", false,-1, 31,0); - vcdp->declBus(c+53513,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_tid", false,-1, 1,0); - vcdp->declQuad(c+53521,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_tag", false,-1, 41,0); - vcdp->declBit(c+53537,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_rw", false,-1); - vcdp->declBus(c+53545,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_byteen", false,-1, 3,0); - vcdp->declBit(c+18417,"VX_cache genblk5[7] bank cache_miss_resrv mrvq_init_ready_state", false,-1); - vcdp->declBit(c+53681,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_is_snp", false,-1); - vcdp->declBit(c+53689,"VX_cache genblk5[7] bank cache_miss_resrv miss_add_snp_invalidate", false,-1); - vcdp->declBit(c+53425,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_full", false,-1); - vcdp->declBit(c+53433,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_stop", false,-1); - vcdp->declBit(c+18913,"VX_cache genblk5[7] bank cache_miss_resrv is_fill_st1", false,-1); - vcdp->declBus(c+18401,"VX_cache genblk5[7] bank cache_miss_resrv fill_addr_st1", false,-1, 24,0); - vcdp->declBit(c+17889,"VX_cache genblk5[7] bank cache_miss_resrv pending_hazard", false,-1); - vcdp->declBit(c+17865,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_pop", false,-1); - vcdp->declBit(c+17873,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_valid_st0", false,-1); - vcdp->declBus(c+53449,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_addr_st0", false,-1, 24,0); - vcdp->declBus(c+53457,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_wsel_st0", false,-1, 1,0); - vcdp->declBus(c+53465,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_data_st0", false,-1, 31,0); - vcdp->declBus(c+53441,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_tid_st0", false,-1, 1,0); - vcdp->declQuad(c+53473,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_tag_st0", false,-1, 41,0); - vcdp->declBit(c+17881,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_rw_st0", false,-1); - vcdp->declBus(c+53489,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_byteen_st0", false,-1, 3,0); - vcdp->declBit(c+53497,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_is_snp_st0", false,-1); - vcdp->declBit(c+53505,"VX_cache genblk5[7] bank cache_miss_resrv miss_resrv_snp_invalidate_st0", false,-1); - {int i; for (i=0; i<16; i++) { - vcdp->declArray(c+56809+i*3,"VX_cache genblk5[7] bank cache_miss_resrv metadata_table", true,(i+0), 84,0);}} - vcdp->declArray(c+57193,"VX_cache genblk5[7] bank cache_miss_resrv addr_table", false,-1, 399,0); - vcdp->declBus(c+57297,"VX_cache genblk5[7] bank cache_miss_resrv valid_table", false,-1, 15,0); - vcdp->declBus(c+57305,"VX_cache genblk5[7] bank cache_miss_resrv ready_table", false,-1, 15,0); - vcdp->declBus(c+57313,"VX_cache genblk5[7] bank cache_miss_resrv schedule_ptr", false,-1, 3,0); - vcdp->declBus(c+57321,"VX_cache genblk5[7] bank cache_miss_resrv head_ptr", false,-1, 3,0); - vcdp->declBus(c+57329,"VX_cache genblk5[7] bank cache_miss_resrv tail_ptr", false,-1, 3,0); - vcdp->declBus(c+57337,"VX_cache genblk5[7] bank cache_miss_resrv size", false,-1, 4,0); - vcdp->declBit(c+57345,"VX_cache genblk5[7] bank cache_miss_resrv enqueue_possible", false,-1); - vcdp->declBus(c+57329,"VX_cache genblk5[7] bank cache_miss_resrv enqueue_index", false,-1, 3,0); - vcdp->declBus(c+19401,"VX_cache genblk5[7] bank cache_miss_resrv make_ready", false,-1, 15,0); - vcdp->declBus(c+19409,"VX_cache genblk5[7] bank cache_miss_resrv make_ready_push", false,-1, 15,0); - vcdp->declBus(c+19417,"VX_cache genblk5[7] bank cache_miss_resrv valid_address_match", false,-1, 15,0); - vcdp->declBit(c+17873,"VX_cache genblk5[7] bank cache_miss_resrv dequeue_possible", false,-1); - vcdp->declBus(c+57313,"VX_cache genblk5[7] bank cache_miss_resrv dequeue_index", false,-1, 3,0); - vcdp->declBit(c+19425,"VX_cache genblk5[7] bank cache_miss_resrv mrvq_push", false,-1); - vcdp->declBit(c+19433,"VX_cache genblk5[7] bank cache_miss_resrv mrvq_pop", false,-1); - vcdp->declBit(c+19441,"VX_cache genblk5[7] bank cache_miss_resrv recover_state", false,-1); - vcdp->declBit(c+19449,"VX_cache genblk5[7] bank cache_miss_resrv increment_head", false,-1); - vcdp->declBit(c+19457,"VX_cache genblk5[7] bank cache_miss_resrv update_ready", false,-1); - vcdp->declBit(c+19465,"VX_cache genblk5[7] bank cache_miss_resrv qual_mrvq_init", false,-1); - vcdp->declBus(c+58809,"VX_cache genblk5[7] bank cwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58665,"VX_cache genblk5[7] bank cwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank cwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank cwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank cwb_queue reset", false,-1); - vcdp->declBit(c+18465,"VX_cache genblk5[7] bank cwb_queue push", false,-1); - vcdp->declBit(c+2089,"VX_cache genblk5[7] bank cwb_queue pop", false,-1); - vcdp->declArray(c+19473,"VX_cache genblk5[7] bank cwb_queue data_in", false,-1, 75,0); - vcdp->declArray(c+19497,"VX_cache genblk5[7] bank cwb_queue data_out", false,-1, 75,0); - vcdp->declBit(c+53729,"VX_cache genblk5[7] bank cwb_queue empty", false,-1); - vcdp->declBit(c+53737,"VX_cache genblk5[7] bank cwb_queue full", false,-1); - vcdp->declBus(c+57353,"VX_cache genblk5[7] bank cwb_queue size", false,-1, 3,0); - vcdp->declBus(c+57353,"VX_cache genblk5[7] bank cwb_queue size_r", false,-1, 3,0); - vcdp->declBit(c+1833,"VX_cache genblk5[7] bank cwb_queue reading", false,-1); - vcdp->declBit(c+19521,"VX_cache genblk5[7] bank cwb_queue writing", false,-1); - {int i; for (i=0; i<8; i++) { - vcdp->declArray(c+57361+i*3,"VX_cache genblk5[7] bank cwb_queue genblk3 data", true,(i+0), 75,0);}} - vcdp->declArray(c+57553,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 head_r", false,-1, 75,0); - vcdp->declArray(c+57577,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 curr_r", false,-1, 75,0); - vcdp->declBus(c+57601,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 2,0); - vcdp->declBus(c+57609,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 2,0); - vcdp->declBus(c+57617,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 2,0); - vcdp->declBit(c+53729,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+53737,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+57625,"VX_cache genblk5[7] bank cwb_queue genblk3 genblk2 bypass_r", false,-1); - vcdp->declBus(c+58817,"VX_cache genblk5[7] bank dwb_queue DATAW", false,-1, 31,0); - vcdp->declBus(c+58673,"VX_cache genblk5[7] bank dwb_queue SIZE", false,-1, 31,0); - vcdp->declBus(c+58681,"VX_cache genblk5[7] bank dwb_queue BUFFERED_OUTPUT", false,-1, 31,0); - vcdp->declBit(c+58009,"VX_cache genblk5[7] bank dwb_queue clk", false,-1); - vcdp->declBit(c+58017,"VX_cache genblk5[7] bank dwb_queue reset", false,-1); - vcdp->declBit(c+18489,"VX_cache genblk5[7] bank dwb_queue push", false,-1); - vcdp->declBit(c+2097,"VX_cache genblk5[7] bank dwb_queue pop", false,-1); - vcdp->declArray(c+19529,"VX_cache genblk5[7] bank dwb_queue data_in", false,-1, 198,0); - vcdp->declArray(c+19585,"VX_cache genblk5[7] bank dwb_queue data_out", false,-1, 198,0); - vcdp->declBit(c+53745,"VX_cache genblk5[7] bank dwb_queue empty", false,-1); - vcdp->declBit(c+53753,"VX_cache genblk5[7] bank dwb_queue full", false,-1); - vcdp->declBus(c+57633,"VX_cache genblk5[7] bank dwb_queue size", false,-1, 2,0); - vcdp->declBus(c+57633,"VX_cache genblk5[7] bank dwb_queue size_r", false,-1, 2,0); - vcdp->declBit(c+1841,"VX_cache genblk5[7] bank dwb_queue reading", false,-1); - vcdp->declBit(c+19641,"VX_cache genblk5[7] bank dwb_queue writing", false,-1); - {int i; for (i=0; i<4; i++) { - vcdp->declArray(c+57641+i*7,"VX_cache genblk5[7] bank dwb_queue genblk3 data", true,(i+0), 198,0);}} - vcdp->declArray(c+57865,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 head_r", false,-1, 198,0); - vcdp->declArray(c+57921,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 198,0); - vcdp->declBus(c+57977,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); - vcdp->declBus(c+57985,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); - vcdp->declBus(c+57993,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); - vcdp->declBit(c+53745,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 empty_r", false,-1); - vcdp->declBit(c+53753,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 full_r", false,-1); - vcdp->declBit(c+58001,"VX_cache genblk5[7] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); + vcdp->declArray(c+24121+i*7,"VX_cache genblk5[3] bank dwb_queue genblk3 data", true,(i+0), 199,0);}} + vcdp->declArray(c+24345,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 head_r", false,-1, 199,0); + vcdp->declArray(c+24401,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 curr_r", false,-1, 199,0); + vcdp->declBus(c+24457,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 wr_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24465,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_r", false,-1, 1,0); + vcdp->declBus(c+24473,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 rd_ptr_next_r", false,-1, 1,0); + vcdp->declBit(c+21393,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 empty_r", false,-1); + vcdp->declBit(c+21401,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 full_r", false,-1); + vcdp->declBit(c+24481,"VX_cache genblk5[3] bank dwb_queue genblk3 genblk2 bypass_r", false,-1); } } @@ -5692,221 +2915,53 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV int c = code; if (0 && vcdp && c) {} // Prevent unused // Variables - WData/*127:0*/ __Vtemp1013[4]; - WData/*127:0*/ __Vtemp1032[4]; - WData/*127:0*/ __Vtemp1051[4]; - WData/*127:0*/ __Vtemp1070[4]; - WData/*127:0*/ __Vtemp1089[4]; - WData/*127:0*/ __Vtemp1108[4]; - WData/*127:0*/ __Vtemp1127[4]; - WData/*127:0*/ __Vtemp1146[4]; - WData/*127:0*/ __Vtemp1155[4]; - WData/*127:0*/ __Vtemp1156[4]; - WData/*127:0*/ __Vtemp1157[4]; - WData/*127:0*/ __Vtemp1158[4]; - WData/*127:0*/ __Vtemp1159[4]; - WData/*127:0*/ __Vtemp1160[4]; - WData/*127:0*/ __Vtemp1161[4]; - WData/*127:0*/ __Vtemp1162[4]; - WData/*127:0*/ __Vtemp1163[4]; - WData/*127:0*/ __Vtemp1164[4]; - WData/*127:0*/ __Vtemp1165[4]; - WData/*127:0*/ __Vtemp1166[4]; - WData/*127:0*/ __Vtemp1167[4]; - WData/*127:0*/ __Vtemp1168[4]; - WData/*127:0*/ __Vtemp1169[4]; - WData/*127:0*/ __Vtemp1170[4]; - WData/*127:0*/ __Vtemp1179[4]; - WData/*127:0*/ __Vtemp1180[4]; - WData/*127:0*/ __Vtemp1181[4]; - WData/*127:0*/ __Vtemp1182[4]; - WData/*127:0*/ __Vtemp1183[4]; - WData/*127:0*/ __Vtemp1184[4]; - WData/*127:0*/ __Vtemp1185[4]; - WData/*127:0*/ __Vtemp1186[4]; - WData/*127:0*/ __Vtemp1187[4]; - WData/*127:0*/ __Vtemp1188[4]; - WData/*127:0*/ __Vtemp1189[4]; - WData/*127:0*/ __Vtemp1190[4]; - WData/*127:0*/ __Vtemp1191[4]; - WData/*127:0*/ __Vtemp1192[4]; - WData/*127:0*/ __Vtemp1193[4]; - WData/*127:0*/ __Vtemp1194[4]; - WData/*127:0*/ __Vtemp1203[4]; - WData/*127:0*/ __Vtemp1204[4]; - WData/*127:0*/ __Vtemp1205[4]; - WData/*127:0*/ __Vtemp1206[4]; - WData/*127:0*/ __Vtemp1207[4]; - WData/*127:0*/ __Vtemp1208[4]; - WData/*127:0*/ __Vtemp1209[4]; - WData/*127:0*/ __Vtemp1210[4]; - WData/*127:0*/ __Vtemp1211[4]; - WData/*127:0*/ __Vtemp1212[4]; - WData/*127:0*/ __Vtemp1213[4]; - WData/*127:0*/ __Vtemp1214[4]; - WData/*127:0*/ __Vtemp1215[4]; - WData/*127:0*/ __Vtemp1216[4]; - WData/*127:0*/ __Vtemp1217[4]; - WData/*127:0*/ __Vtemp1218[4]; - WData/*127:0*/ __Vtemp1227[4]; - WData/*127:0*/ __Vtemp1228[4]; - WData/*127:0*/ __Vtemp1229[4]; - WData/*127:0*/ __Vtemp1230[4]; - WData/*127:0*/ __Vtemp1231[4]; - WData/*127:0*/ __Vtemp1232[4]; - WData/*127:0*/ __Vtemp1233[4]; - WData/*127:0*/ __Vtemp1234[4]; - WData/*127:0*/ __Vtemp1235[4]; - WData/*127:0*/ __Vtemp1236[4]; - WData/*127:0*/ __Vtemp1237[4]; - WData/*127:0*/ __Vtemp1238[4]; - WData/*127:0*/ __Vtemp1239[4]; - WData/*127:0*/ __Vtemp1240[4]; - WData/*127:0*/ __Vtemp1241[4]; - WData/*127:0*/ __Vtemp1242[4]; - WData/*127:0*/ __Vtemp1251[4]; - WData/*127:0*/ __Vtemp1252[4]; - WData/*127:0*/ __Vtemp1253[4]; - WData/*127:0*/ __Vtemp1254[4]; - WData/*127:0*/ __Vtemp1255[4]; - WData/*127:0*/ __Vtemp1256[4]; - WData/*127:0*/ __Vtemp1257[4]; - WData/*127:0*/ __Vtemp1258[4]; - WData/*127:0*/ __Vtemp1259[4]; - WData/*127:0*/ __Vtemp1260[4]; - WData/*127:0*/ __Vtemp1261[4]; - WData/*127:0*/ __Vtemp1262[4]; - WData/*127:0*/ __Vtemp1263[4]; - WData/*127:0*/ __Vtemp1264[4]; - WData/*127:0*/ __Vtemp1265[4]; - WData/*127:0*/ __Vtemp1266[4]; - WData/*127:0*/ __Vtemp1275[4]; - WData/*127:0*/ __Vtemp1276[4]; - WData/*127:0*/ __Vtemp1277[4]; - WData/*127:0*/ __Vtemp1278[4]; - WData/*127:0*/ __Vtemp1279[4]; - WData/*127:0*/ __Vtemp1280[4]; - WData/*127:0*/ __Vtemp1281[4]; - WData/*127:0*/ __Vtemp1282[4]; - WData/*127:0*/ __Vtemp1283[4]; - WData/*127:0*/ __Vtemp1284[4]; - WData/*127:0*/ __Vtemp1285[4]; - WData/*127:0*/ __Vtemp1286[4]; - WData/*127:0*/ __Vtemp1287[4]; - WData/*127:0*/ __Vtemp1288[4]; - WData/*127:0*/ __Vtemp1289[4]; - WData/*127:0*/ __Vtemp1290[4]; - WData/*127:0*/ __Vtemp1299[4]; - WData/*127:0*/ __Vtemp1300[4]; - WData/*127:0*/ __Vtemp1301[4]; - WData/*127:0*/ __Vtemp1302[4]; - WData/*127:0*/ __Vtemp1303[4]; - WData/*127:0*/ __Vtemp1304[4]; - WData/*127:0*/ __Vtemp1305[4]; - WData/*127:0*/ __Vtemp1306[4]; - WData/*127:0*/ __Vtemp1307[4]; - WData/*127:0*/ __Vtemp1308[4]; - WData/*127:0*/ __Vtemp1309[4]; - WData/*127:0*/ __Vtemp1310[4]; - WData/*127:0*/ __Vtemp1311[4]; - WData/*127:0*/ __Vtemp1312[4]; - WData/*127:0*/ __Vtemp1313[4]; - WData/*127:0*/ __Vtemp1314[4]; - WData/*127:0*/ __Vtemp1323[4]; - WData/*127:0*/ __Vtemp1324[4]; - WData/*127:0*/ __Vtemp1325[4]; - WData/*127:0*/ __Vtemp1326[4]; - WData/*127:0*/ __Vtemp1327[4]; - WData/*127:0*/ __Vtemp1328[4]; - WData/*127:0*/ __Vtemp1329[4]; - WData/*127:0*/ __Vtemp1330[4]; - WData/*127:0*/ __Vtemp1331[4]; - WData/*127:0*/ __Vtemp1332[4]; - WData/*127:0*/ __Vtemp1333[4]; - WData/*127:0*/ __Vtemp1334[4]; - WData/*127:0*/ __Vtemp1335[4]; - WData/*127:0*/ __Vtemp1336[4]; - WData/*127:0*/ __Vtemp1337[4]; - WData/*127:0*/ __Vtemp1338[4]; - WData/*127:0*/ __Vtemp986[4]; - WData/*127:0*/ __Vtemp987[4]; - WData/*127:0*/ __Vtemp988[4]; - WData/*127:0*/ __Vtemp989[4]; - WData/*127:0*/ __Vtemp990[4]; - WData/*127:0*/ __Vtemp991[4]; - WData/*127:0*/ __Vtemp992[4]; - WData/*127:0*/ __Vtemp993[4]; - WData/*223:0*/ __Vtemp994[7]; - WData/*127:0*/ __Vtemp995[4]; - WData/*127:0*/ __Vtemp1000[4]; - WData/*127:0*/ __Vtemp1006[4]; - WData/*127:0*/ __Vtemp1007[4]; - WData/*127:0*/ __Vtemp1010[4]; - WData/*127:0*/ __Vtemp1011[4]; - WData/*127:0*/ __Vtemp1012[4]; - WData/*127:0*/ __Vtemp1014[4]; - WData/*127:0*/ __Vtemp1019[4]; - WData/*127:0*/ __Vtemp1025[4]; - WData/*127:0*/ __Vtemp1026[4]; - WData/*127:0*/ __Vtemp1029[4]; - WData/*127:0*/ __Vtemp1030[4]; - WData/*127:0*/ __Vtemp1031[4]; - WData/*127:0*/ __Vtemp1033[4]; - WData/*127:0*/ __Vtemp1038[4]; - WData/*127:0*/ __Vtemp1044[4]; - WData/*127:0*/ __Vtemp1045[4]; - WData/*127:0*/ __Vtemp1048[4]; - WData/*127:0*/ __Vtemp1049[4]; - WData/*127:0*/ __Vtemp1050[4]; - WData/*127:0*/ __Vtemp1052[4]; - WData/*127:0*/ __Vtemp1057[4]; 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+ WData/*127:0*/ __Vtemp564[4]; + WData/*127:0*/ __Vtemp565[4]; + WData/*127:0*/ __Vtemp567[4]; + WData/*127:0*/ __Vtemp572[4]; + WData/*127:0*/ __Vtemp578[4]; + WData/*127:0*/ __Vtemp579[4]; + WData/*127:0*/ __Vtemp582[4]; + WData/*127:0*/ __Vtemp583[4]; + WData/*127:0*/ __Vtemp584[4]; + WData/*127:0*/ __Vtemp586[4]; + WData/*127:0*/ __Vtemp591[4]; + WData/*127:0*/ __Vtemp597[4]; + WData/*127:0*/ __Vtemp598[4]; + WData/*127:0*/ __Vtemp601[4]; + WData/*127:0*/ __Vtemp602[4]; + WData/*127:0*/ __Vtemp603[4]; + WData/*127:0*/ __Vtemp612[4]; + WData/*127:0*/ __Vtemp620[4]; + WData/*127:0*/ __Vtemp628[4]; + WData/*127:0*/ __Vtemp636[4]; // Body { - vcdp->fullBus(c+1,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid),32); - vcdp->fullBus(c+9,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready),8); - vcdp->fullBus(c+17,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready),8); - vcdp->fullBus(c+25,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready),8); + vcdp->fullBus(c+1,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_req_bank_sel__per_bank_valid),16); + vcdp->fullBus(c+9,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready),4); + vcdp->fullBus(c+17,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready),4); + vcdp->fullBus(c+25,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready),4); vcdp->fullBus(c+33,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid),4); vcdp->fullBit(c+41,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready)))); vcdp->fullBit(c+49,((1U & (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready)))); @@ -5932,307 +2987,160 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV >> 3U)))); vcdp->fullBit(c+153,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) >> 3U)))); - vcdp->fullBus(c+161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid),4); - vcdp->fullBit(c+169,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 4U)))); - vcdp->fullBit(c+177,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 4U)))); - vcdp->fullBit(c+185,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 4U)))); - vcdp->fullBus(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid),4); - vcdp->fullBit(c+201,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 5U)))); - vcdp->fullBit(c+209,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 5U)))); - vcdp->fullBit(c+217,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 5U)))); - vcdp->fullBus(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid),4); - vcdp->fullBit(c+233,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 6U)))); - vcdp->fullBit(c+241,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 6U)))); - vcdp->fullBit(c+249,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 6U)))); - vcdp->fullBus(c+257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid),4); - vcdp->fullBit(c+265,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 7U)))); - vcdp->fullBit(c+273,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_ready) - >> 7U)))); - vcdp->fullBit(c+281,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_ready) - >> 7U)))); - vcdp->fullBus(c+289,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),8); - vcdp->fullBit(c+297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); - vcdp->fullBit(c+305,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); - vcdp->fullBit(c+313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+401,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+1057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+1065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+1073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+1081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+1089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+1097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+1113,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+1121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+1161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+1169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+1249,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+1257,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+1265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+1273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+1281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+1289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+1305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+1313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+1353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+1361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+1441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+1449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+1457,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+1465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+1473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+1497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+1505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+1545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+1553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+1633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+1641,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+1649,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+1657,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)); - vcdp->fullBit(c+1665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire)); - vcdp->fullQuad(c+1673,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),54); - vcdp->fullBit(c+1689,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); - vcdp->fullArray(c+1697,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),153); - vcdp->fullBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); - vcdp->fullArray(c+1745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); - vcdp->fullBit(c+1825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); - vcdp->fullBit(c+1833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); - vcdp->fullBit(c+1841,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); - vcdp->fullBit(c+1849,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) - & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) - & (~ ((~ (IData)((0U - != - (0xffU - & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) - | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); - vcdp->fullBit(c+1857,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1865,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); - vcdp->fullBit(c+1873,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + vcdp->fullBus(c+161,(vlTOPp->VX_cache__DOT__cache_core_req_bank_sel__DOT__genblk2__DOT__per_bank_ready_sel),4); + vcdp->fullBit(c+169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop)); + vcdp->fullBit(c+177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__reading)); + vcdp->fullBit(c+185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+201,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+265,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+361,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)); + vcdp->fullBit(c+769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire)); + vcdp->fullQuad(c+777,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__snp_req_queue__data_in),55); + vcdp->fullBit(c+793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__writing)); + vcdp->fullArray(c+801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dfp_queue__data_in),154); + vcdp->fullBit(c+841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__writing)); + vcdp->fullArray(c+849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellinp__reqq_queue__data_in),314); + vcdp->fullBit(c+929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__writing)); + vcdp->fullBit(c+937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__reading)); + vcdp->fullBit(c+945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__reading)); + vcdp->fullBit(c+953,((((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_pop) + & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))) + & (~ ((~ (IData)((0U + != + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) + | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)))))); + vcdp->fullBit(c+961,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+969,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready))))); + vcdp->fullBit(c+977,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+1881,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1889,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1897,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))) + | (((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_rsp_fire))))); + vcdp->fullBit(c+985,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+993,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+1001,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 1U))))); - vcdp->fullBit(c+1905,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) + vcdp->fullBit(c+1009,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+1913,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) + vcdp->fullBit(c+1017,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1921,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + vcdp->fullBit(c+1025,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1929,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + vcdp->fullBit(c+1033,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 2U))))); - vcdp->fullBit(c+1937,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) + vcdp->fullBit(c+1041,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+1945,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) + vcdp->fullBit(c+1049,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1953,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + vcdp->fullBit(c+1057,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1961,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) + vcdp->fullBit(c+1065,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) >> 3U))))); - vcdp->fullBit(c+1969,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) + vcdp->fullBit(c+1073,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_wb_req_fire)) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) + >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U))) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))) | (((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) + >> 7U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+1977,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) + vcdp->fullBit(c+1081,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_core_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1985,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+1993,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 4U))))); - vcdp->fullBit(c+2001,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+2009,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+2017,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+2025,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 5U))))); - vcdp->fullBit(c+2033,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+2041,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+2049,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+2057,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 6U))))); - vcdp->fullBit(c+2065,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+2073,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+2081,(((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+2089,((1U & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_ready) - >> 7U))))); - vcdp->fullBit(c+2097,((((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_wb_req_fire)) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U))) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))) - | (((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U) & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_rsp_fire))))); - vcdp->fullBit(c+2105,((((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_core_req_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+2113,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),8); - vcdp->fullBus(c+2121,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),8); - vcdp->fullBus(c+2129,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),16); - vcdp->fullArray(c+2137,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),256); - vcdp->fullArray(c+2201,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),336); - vcdp->fullBus(c+2289,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),8); - vcdp->fullArray(c+2297,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),224); - vcdp->fullBus(c+2353,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),8); - vcdp->fullBus(c+2361,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),8); - vcdp->fullArray(c+2369,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),128); - vcdp->fullArray(c+2401,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),224); - vcdp->fullArray(c+2457,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),1024); - vcdp->fullBus(c+2713,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),8); - vcdp->fullBus(c+2721,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),8); - vcdp->fullArray(c+2729,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),224); - vcdp->fullBus(c+2785,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + vcdp->fullBus(c+1089,(vlTOPp->VX_cache__DOT__per_bank_core_req_ready),4); + vcdp->fullBus(c+1097,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid),4); + vcdp->fullBus(c+1105,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid),8); + vcdp->fullArray(c+1113,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_data),128); + vcdp->fullArray(c+1145,(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag),168); + vcdp->fullBus(c+1193,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid),4); + vcdp->fullArray(c+1201,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_addr),112); + vcdp->fullBus(c+1233,(vlTOPp->VX_cache__DOT__per_bank_dram_fill_rsp_ready),4); + vcdp->fullBus(c+1241,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_valid),4); + vcdp->fullQuad(c+1249,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_byteen),64); + vcdp->fullArray(c+1265,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_addr),112); + vcdp->fullArray(c+1297,(vlTOPp->VX_cache__DOT__per_bank_dram_wb_req_data),512); + vcdp->fullBus(c+1425,(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready),4); + vcdp->fullBus(c+1433,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_valid),4); + vcdp->fullArray(c+1441,(vlTOPp->VX_cache__DOT__per_bank_snp_rsp_tag),112); + vcdp->fullBus(c+1473,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->fullBus(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+2801,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+1481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1489,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+2817,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+1505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & @@ -6241,39 +3149,39 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+2833,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->fullBit(c+1513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1521,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+2841,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1529,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp986[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)))),26); + __Vtemp522[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 0x1cU)); - __Vtemp986[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + __Vtemp522[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] >> 0x1cU)); - __Vtemp986[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + __Vtemp522[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] >> 0x1cU)); - __Vtemp986[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + __Vtemp522[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] >> 0x1cU)); - vcdp->fullArray(c+2849,(__Vtemp986),128); - vcdp->fullBit(c+2881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+2889,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBus(c+2897,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + vcdp->fullArray(c+1537,(__Vtemp522),128); + vcdp->fullBit(c+1569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1577,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+1585,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->fullBus(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+2913,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+1593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1601,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+2929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+1617,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & @@ -6282,39 +3190,39 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+2937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+2945,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->fullBit(c+1625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1633,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+2953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1641,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp987[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)))),26); + __Vtemp523[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 0x1cU)); - __Vtemp987[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + __Vtemp523[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] >> 0x1cU)); - __Vtemp987[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + __Vtemp523[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] >> 0x1cU)); - __Vtemp987[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + __Vtemp523[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] >> 0x1cU)); - vcdp->fullArray(c+2961,(__Vtemp987),128); - vcdp->fullBit(c+2993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+3001,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBus(c+3009,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + vcdp->fullArray(c+1649,(__Vtemp523),128); + vcdp->fullBit(c+1681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1689,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+1697,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->fullBus(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+3025,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+1705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1713,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+3041,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+1729,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & @@ -6323,39 +3231,39 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+3057,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->fullBit(c+1737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1745,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+3065,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1753,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp988[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)))),26); + __Vtemp524[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 0x1cU)); - __Vtemp988[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + __Vtemp524[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] >> 0x1cU)); - __Vtemp988[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + __Vtemp524[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] >> 0x1cU)); - __Vtemp988[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + __Vtemp524[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] >> 0x1cU)); - vcdp->fullArray(c+3073,(__Vtemp988),128); - vcdp->fullBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+3113,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBus(c+3121,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] + vcdp->fullArray(c+1761,(__Vtemp524),128); + vcdp->fullBit(c+1793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1801,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBus(c+1809,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] >> 0xaU))),2); - vcdp->fullBus(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+3137,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+1817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); + vcdp->fullQuad(c+1825,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+3153,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+1841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & @@ -6364,197 +3272,33 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+3169,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) + vcdp->fullBit(c+1849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_dram_wb_req_valid)); + vcdp->fullBus(c+1857,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + << 0xaU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+3177,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] + >> 0x16U)))),16); + vcdp->fullBus(c+1865,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp989[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] + >> 0x1cU)))),26); + __Vtemp525[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] >> 0x1cU)); - __Vtemp989[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] + __Vtemp525[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] >> 0x1cU)); - __Vtemp989[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] + __Vtemp525[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] >> 0x1cU)); - __Vtemp989[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] + __Vtemp525[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] >> 0x1cU)); - vcdp->fullArray(c+3185,(__Vtemp989),128); - vcdp->fullBit(c+3217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+3225,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBus(c+3233,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->fullBus(c+3241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+3249,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+3265,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & - (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+3273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+3281,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+3289,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp990[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp990[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp990[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp990[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->fullArray(c+3297,(__Vtemp990),128); - vcdp->fullBit(c+3329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+3337,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBus(c+3345,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->fullBus(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+3361,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+3377,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & - (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+3385,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+3393,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+3401,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp991[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp991[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp991[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp991[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->fullArray(c+3409,(__Vtemp991),128); - vcdp->fullBit(c+3441,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+3449,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBus(c+3457,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->fullBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+3473,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+3489,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & - (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+3497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+3505,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+3513,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp992[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp992[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp992[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp992[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->fullArray(c+3521,(__Vtemp992),128); - vcdp->fullBit(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+3561,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBus(c+3569,((3U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U] - >> 0xaU))),2); - vcdp->fullBus(c+3577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[0U]),32); - vcdp->fullQuad(c+3585,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[2U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out[1U]))))),42); - vcdp->fullBit(c+3601,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & - (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)))))); - vcdp->fullBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_dram_wb_req_valid)); - vcdp->fullBus(c+3617,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - << 0xbU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - >> 0x15U)))),16); - vcdp->fullBus(c+3625,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[5U] - << 4U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - >> 0x1cU)))),25); - __Vtemp993[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U] - >> 0x1cU)); - __Vtemp993[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[1U] - >> 0x1cU)); - __Vtemp993[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[2U] - >> 0x1cU)); - __Vtemp993[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[4U] - << 4U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[3U] - >> 0x1cU)); - vcdp->fullArray(c+3633,(__Vtemp993),128); - vcdp->fullBit(c+3665,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__curr_bank_snp_rsp_valid)); - vcdp->fullBus(c+3673,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); - vcdp->fullBit(c+3681,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); - vcdp->fullBit(c+3689,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); - vcdp->fullBus(c+3697,(((0xdfU >= (0xffU & ((IData)(0x1cU) + vcdp->fullArray(c+1873,(__Vtemp525),128); + vcdp->fullBit(c+1905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__curr_bank_snp_rsp_valid)); + vcdp->fullBus(c+1913,((0xfffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[0U])),28); + vcdp->fullBit(c+1921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid)); + vcdp->fullBit(c+1929,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dfqq_req)); + vcdp->fullBus(c+1937,(((0x6fU >= (0x7fU & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))) ? (0xfffffffU & (((0U == @@ -6566,7 +3310,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ ((IData)(1U) + - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U)))] @@ -6577,7 +3321,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) | (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr[ - (7U + (3U & (((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)) >> 5U))] @@ -6586,45 +3330,44 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & ((IData)(0x1cU) * (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index)))))) : 0U)),28); - vcdp->fullBit(c+3705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+3713,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); - vcdp->fullBus(c+3721,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),3); - vcdp->fullBit(c+3729,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); - vcdp->fullBit(c+3737,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); - vcdp->fullBit(c+3745,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); - vcdp->fullBus(c+3753,((0xffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])),8); - __Vtemp994[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; - __Vtemp994[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; - __Vtemp994[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; - __Vtemp994[3U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]; - __Vtemp994[4U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[4U]; - __Vtemp994[5U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[5U]; - __Vtemp994[6U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[6U]; - vcdp->fullArray(c+3761,(__Vtemp994),224); - vcdp->fullBus(c+3817,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),8); - vcdp->fullArray(c+3825,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),224); - vcdp->fullBus(c+3881,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) - & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),8); - vcdp->fullBit(c+3889,((1U & ((~ (IData)((0U + vcdp->fullBit(c+1945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+1953,((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)))); + vcdp->fullBus(c+1961,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dwb_bank),2); + vcdp->fullBit(c+1969,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__update_use)); + vcdp->fullBit(c+1977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__reading)); + vcdp->fullBit(c+1985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__writing)); + vcdp->fullBus(c+1993,((0xfU & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))),4); + __Vtemp528[0U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[0U]; + __Vtemp528[1U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[1U]; + __Vtemp528[2U] = vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[2U]; + __Vtemp528[3U] = (0xffffU & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U]); + vcdp->fullArray(c+2001,(__Vtemp528),112); + vcdp->fullBus(c+2033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid),4); + vcdp->fullArray(c+2041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_bank_dram_fill_req_addr),112); + vcdp->fullBus(c+2073,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bqual_bank_dram_fill_req_valid) + & (~ ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index))))),4); + vcdp->fullBit(c+2081,((1U & ((~ (IData)((0U != - (0xffU - & vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[7U])))) + (0xfU + & (vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out[3U] + >> 0x10U))))) | (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+3897,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) + vcdp->fullBit(c+2089,(((0U != (IData)(vlTOPp->VX_cache__DOT__per_bank_dram_fill_req_valid)) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+3905,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),3); - vcdp->fullBit(c+3913,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); - vcdp->fullArray(c+3921,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),232); - vcdp->fullArray(c+3985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),232); - vcdp->fullBit(c+4049,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); - vcdp->fullBus(c+4057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->fullBus(c+4065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullBus(c+4073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->fullBus(c+4081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullArray(c+4089,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); - vcdp->fullQuad(c+4121,(((0x14fU >= (0x1ffU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + vcdp->fullBus(c+2097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+2105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__qual_has_request)); + vcdp->fullArray(c+2113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellinp__dfqq_queue__data_in),116); + vcdp->fullArray(c+2145,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT____Vcellout__dfqq_queue__data_out),116); + vcdp->fullBit(c+2177,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__writing)); + vcdp->fullBus(c+2185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBus(c+2201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+2217,(vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data),128); + vcdp->fullQuad(c+2249,(((0xa7U >= (0xffU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) ? (VL_ULL(0x3ffffffffff) & (((0U == (0x1fU & ((IData)(0x2aU) @@ -6634,7 +3377,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(2U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -6646,7 +3389,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ ((IData)(1U) + - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U)))])) @@ -6663,7 +3406,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) | ((QData)((IData)( vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (0xfU + (7U & (((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) >> 5U))])) @@ -6671,47 +3414,47 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) : VL_ULL(0))),42); - vcdp->fullBus(c+4137,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),8); - vcdp->fullBus(c+4145,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),3); - vcdp->fullBit(c+4153,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); - vcdp->fullBus(c+4161,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->fullBus(c+4169,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) + vcdp->fullBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); + vcdp->fullBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); + vcdp->fullBit(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); + vcdp->fullBus(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),8); - vcdp->fullBus(c+4177,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original))))),4); + vcdp->fullBus(c+2305,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) ^ (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),8); - vcdp->fullBus(c+4185,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullBus(c+4193,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),3); - vcdp->fullBit(c+4201,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); - vcdp->fullBus(c+4209,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),8); - vcdp->fullBus(c+4217,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullBit(c+4225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); - vcdp->fullBus(c+4233,((0x1ffffffU & (IData)( + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original)))),4); + vcdp->fullBus(c+2313,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBus(c+2321,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank),2); + vcdp->fullBit(c+2329,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid)); + vcdp->fullBus(c+2337,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2345,(vlTOPp->VX_cache__DOT__snp_rsp_arb__DOT__sel_ffsq__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullBit(c+2353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+2361,((0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->fullBit(c+4241,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->fullBit(c+2369,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))))); - vcdp->fullBus(c+4249,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->fullBit(c+4257,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->fullBus(c+4265,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp995[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp995[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp995[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp995[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->fullArray(c+4273,(__Vtemp995),128); - vcdp->fullBit(c+4305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); - vcdp->fullBit(c+4313,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+4321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->fullBus(c+4329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->fullBit(c+4337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->fullBus(c+4345,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + vcdp->fullBus(c+2377,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+2385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+2393,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp529[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp529[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp529[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp529[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+2401,(__Vtemp529),128); + vcdp->fullBit(c+2433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+2441,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+2449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+2457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+2465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+2473,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 2U))))),4); - vcdp->fullBus(c+4353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->fullBus(c+4361,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + vcdp->fullBus(c+2481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+2489,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ ((IData)(1U) @@ -6724,52 +3467,52 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))))),32); - vcdp->fullBit(c+4369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->fullBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->fullBit(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->fullBit(c+4393,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->fullBit(c+4401,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( + vcdp->fullBit(c+2497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+2505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+2513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+2521,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+2529,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))); - vcdp->fullBit(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->fullBit(c+4417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->fullBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->fullBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->fullBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->fullBit(c+4449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->fullBit(c+4457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->fullBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->fullBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->fullBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->fullBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->fullBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->fullBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->fullBit(c+4513,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) + vcdp->fullBit(c+2537,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+2545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+2553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+2561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+2569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+2577,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+2585,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+2593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+2601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+2609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+2617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+2625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+2633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+2641,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->fullBus(c+4521,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU + vcdp->fullBus(c+2649,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -6777,40 +3520,40 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) - : 0U)))))),25); - vcdp->fullBus(c+4529,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) + : 0U)))))),26); + vcdp->fullBus(c+2657,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_addr_st0) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (3U & ( @@ -6821,7 +3564,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) : 0U)))),2); - vcdp->fullBus(c+4537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBus(c+2665,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -6848,20 +3591,20 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U)))) : 0U))),32); - __Vtemp1000[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1000[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1000[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1000[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->fullArray(c+4545,(__Vtemp1000),128); - vcdp->fullQuad(c+4577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp534[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp534[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp534[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp534[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+2673,(__Vtemp534),128); + vcdp->fullQuad(c+2705,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -6912,20 +3655,20 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) << 7U) : VL_ULL(0))))),49); - vcdp->fullBit(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) + vcdp->fullBit(c+2721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_rw_st0)) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_pop_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))))); - vcdp->fullBit(c+4601,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBit(c+2729,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U))))); - vcdp->fullBit(c+4609,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBit(c+2737,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snrq_pop_unqual) @@ -6933,27 +3676,27 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U))))); - vcdp->fullBit(c+4617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+4625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+4633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+4641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+4649,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+4665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->fullBit(c+4713,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1006[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + vcdp->fullBit(c+2745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+2753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+2761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+2769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+2777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+2793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+2825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+2833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+2841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp540[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1006[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp540[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1006[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp540[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1006[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp540[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->fullBus(c+4721,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBus(c+2849,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))) - ? 0U : (__Vtemp1006[ + ? 0U : (__Vtemp540[ ((IData)(1U) + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]))] @@ -6962,45 +3705,45 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp1006[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 - [0U])] + | (__Vtemp540[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + [0U])] >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))),32); - __Vtemp1007[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp541[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1007[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp541[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1007[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp541[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1007[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp541[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->fullArray(c+4729,(__Vtemp1007),128); - vcdp->fullBus(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->fullBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); - vcdp->fullBit(c+4777,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->fullBus(c+4785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + vcdp->fullArray(c+2857,(__Vtemp541),128); + vcdp->fullBus(c+2889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+2897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+2905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+2913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c [0U]),16); - vcdp->fullQuad(c+4793,((VL_ULL(0x3ffffffffff) + vcdp->fullQuad(c+2921,((VL_ULL(0x3ffffffffff) & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 7U))),42); - vcdp->fullBus(c+4809,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBus(c+2937,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U]))),2); - vcdp->fullBit(c+4817,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBit(c+2945,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U))))); - vcdp->fullBus(c+4825,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBus(c+2953,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 2U)))),4); - vcdp->fullBit(c+4833,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + vcdp->fullBit(c+2961,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->fullBit(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 + vcdp->fullBit(c+2969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])); - vcdp->fullBit(c+4849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 + vcdp->fullBit(c+2977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])); - vcdp->fullBit(c+4857,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->fullBit(c+4865,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + vcdp->fullBit(c+2985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+2993,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_to_mrvq_st1e) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ @@ -7008,261 +3751,263 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U])))); - vcdp->fullBit(c+4873,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->fullBit(c+4881,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+3001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+3009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U])); - vcdp->fullBit(c+4889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 + vcdp->fullBit(c+3017,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U])); - vcdp->fullBit(c+4897,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+3025,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->fullBus(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->fullBit(c+4913,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBus(c+3033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+3041,((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->fullBit(c+4921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->fullBit(c+4929,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+3049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+3057,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->fullBit(c+4937,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+3065,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->fullBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+4953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+4969,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) + vcdp->fullBit(c+3073,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+3081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+3089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+3097,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->fullBit(c+4985,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+3105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+3113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU))))))); - vcdp->fullBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) + vcdp->fullBit(c+3121,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->fullBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->fullBit(c+5017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + vcdp->fullBit(c+3129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+3137,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+3145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+3153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] >> 6U)))); - vcdp->fullBit(c+5025,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->fullBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->fullQuad(c+5041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->fullBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->fullArray(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->fullBit(c+5105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->fullBus(c+5113,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBit(c+3161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+3169,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+3185,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+3193,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+3233,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+3241,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))),4); - vcdp->fullBus(c+5121,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBus(c+3249,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x12U))),4); - vcdp->fullBus(c+5129,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBus(c+3257,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 2U))),16); - __Vtemp1010[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1010[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1010[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1010[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+5137,(__Vtemp1010),120); - __Vtemp1011[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1011[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1011[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1011[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+5169,(__Vtemp1011),128); - vcdp->fullQuad(c+5201,((VL_ULL(0x3ffffffffff) + __Vtemp544[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp544[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp544[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp544[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+3265,(__Vtemp544),120); + __Vtemp545[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp545[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp545[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp545[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+3297,(__Vtemp545),128); + vcdp->fullQuad(c+3329,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+5217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+5225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+5233,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBit(c+3345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+3353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+3361,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U) & VL_NEGATE_I((IData)( (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->fullArray(c+5241,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->fullBit(c+5321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->fullBus(c+5329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->fullBus(c+5337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullArray(c+5345,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->fullBus(c+5409,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->fullBit(c+5417,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 + vcdp->fullArray(c+3369,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+3449,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+3457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+3465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+3473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+3537,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+3545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])); - vcdp->fullBus(c+5425,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 + vcdp->fullBus(c+3553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writeword_st1 [0U]),32); - __Vtemp1012[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp546[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][0U]; - __Vtemp1012[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp546[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][1U]; - __Vtemp1012[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp546[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][2U]; - __Vtemp1012[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 + __Vtemp546[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__writedata_st1 [0U][3U]; - vcdp->fullArray(c+5433,(__Vtemp1012),128); - vcdp->fullBus(c+5465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullArray(c+3561,(__Vtemp546),128); + vcdp->fullBus(c+3593,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]),2); - vcdp->fullBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+5489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+5497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+5505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+5537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+5545,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + vcdp->fullBit(c+3601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+3609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+3617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+3625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+3633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+3665,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+3673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+3681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])]),16); - vcdp->fullBus(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1013[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + vcdp->fullBus(c+3689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp547[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1013[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + __Vtemp547[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1013[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + __Vtemp547[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1013[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + __Vtemp547[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->fullArray(c+5569,(__Vtemp1013),128); - vcdp->fullBit(c+5601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + vcdp->fullArray(c+3697,(__Vtemp547),128); + vcdp->fullBit(c+3729,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])); - vcdp->fullBit(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + vcdp->fullBit(c+3737,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U])); - vcdp->fullBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+5625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+5681,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+5689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+5697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+5705,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBus(c+3745,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+3753,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+3785,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+3793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+3801,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+3809,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+3817,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+3825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+3833,((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->fullBit(c+5713,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+3841,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->fullBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->fullBit(c+5729,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) + vcdp->fullBit(c+3849,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+3857,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->fullBit(c+5737,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+3865,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); 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+ vcdp->fullBus(c+4041,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->fullBus(c+5921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+5929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+5937,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+5945,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) + vcdp->fullBus(c+4049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+4057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+4065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+4073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->fullBit(c+5953,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->fullBit(c+5961,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->fullBit(c+5969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->fullBit(c+4081,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+4089,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+4097,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->fullArray(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->fullArray(c+6001,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->fullBit(c+6025,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->fullArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->fullArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->fullBit(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->fullBit(c+6153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); - vcdp->fullBus(c+6161,((0x1ffffffU & (IData)( + vcdp->fullArray(c+4105,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+4129,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+4153,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+4161,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->fullArray(c+4217,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->fullBit(c+4273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+4281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+4289,((0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->fullBit(c+6169,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->fullBit(c+4297,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))))); - vcdp->fullBus(c+6177,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->fullBit(c+6185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->fullBus(c+6193,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1014[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1014[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1014[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1014[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->fullArray(c+6201,(__Vtemp1014),128); - vcdp->fullBit(c+6233,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); - vcdp->fullBit(c+6241,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+6249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->fullBus(c+6257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->fullBit(c+6265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->fullBus(c+6273,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + vcdp->fullBus(c+4305,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+4313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+4321,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp548[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp548[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp548[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp548[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+4329,(__Vtemp548),128); + vcdp->fullBit(c+4361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+4369,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+4377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+4385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+4393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+4401,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 2U))))),4); - vcdp->fullBus(c+6281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->fullBus(c+6289,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + vcdp->fullBus(c+4409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+4417,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ ((IData)(1U) @@ -7275,52 +4020,52 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))))),32); - vcdp->fullBit(c+6297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->fullBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->fullBit(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->fullBit(c+6321,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->fullBit(c+6329,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( + vcdp->fullBit(c+4425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+4433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+4441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+4449,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+4457,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))); - vcdp->fullBit(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->fullBit(c+6345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->fullBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->fullBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->fullBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->fullBit(c+6377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->fullBit(c+6385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->fullBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->fullBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->fullBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->fullBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->fullBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->fullBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->fullBit(c+6441,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) + vcdp->fullBit(c+4465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+4473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+4481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+4489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+4497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+4505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+4513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+4521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+4529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+4537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+4545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+4553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+4561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+4569,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->fullBus(c+6449,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU + vcdp->fullBus(c+4577,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -7328,40 +4073,40 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) - : 0U)))))),25); - vcdp->fullBus(c+6457,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) + : 0U)))))),26); + vcdp->fullBus(c+4585,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_addr_st0) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (3U & ( @@ -7372,7 +4117,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) : 0U)))),2); - vcdp->fullBus(c+6465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBus(c+4593,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -7399,20 +4144,20 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U)))) : 0U))),32); - __Vtemp1019[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1019[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1019[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1019[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->fullArray(c+6473,(__Vtemp1019),128); - vcdp->fullQuad(c+6505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp553[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp553[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp553[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp553[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+4601,(__Vtemp553),128); + vcdp->fullQuad(c+4633,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -7463,20 +4208,20 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) << 7U) : VL_ULL(0))))),49); - vcdp->fullBit(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) + vcdp->fullBit(c+4649,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_rw_st0)) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_pop_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))))); - vcdp->fullBit(c+6529,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBit(c+4657,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U))))); - vcdp->fullBit(c+6537,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBit(c+4665,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snrq_pop_unqual) @@ -7484,27 +4229,27 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U))))); - vcdp->fullBit(c+6545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+6553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+6561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+6569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+6577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+6593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->fullBit(c+6641,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1025[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + vcdp->fullBit(c+4673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+4681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+4689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+4697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+4705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+4721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+4753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+4761,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+4769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp559[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1025[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp559[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1025[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp559[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1025[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp559[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->fullBus(c+6649,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBus(c+4777,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))) - ? 0U : (__Vtemp1025[ + ? 0U : (__Vtemp559[ ((IData)(1U) + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]))] @@ -7513,45 +4258,45 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp1025[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 - [0U])] + | (__Vtemp559[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + [0U])] >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))),32); - __Vtemp1026[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp560[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1026[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp560[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1026[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp560[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1026[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp560[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->fullArray(c+6657,(__Vtemp1026),128); - vcdp->fullBus(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->fullBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); - vcdp->fullBit(c+6705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->fullBus(c+6713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + vcdp->fullArray(c+4785,(__Vtemp560),128); + vcdp->fullBus(c+4817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+4825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+4833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+4841,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c [0U]),16); - vcdp->fullQuad(c+6721,((VL_ULL(0x3ffffffffff) + vcdp->fullQuad(c+4849,((VL_ULL(0x3ffffffffff) & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 7U))),42); - vcdp->fullBus(c+6737,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBus(c+4865,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U]))),2); - vcdp->fullBit(c+6745,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBit(c+4873,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U))))); - vcdp->fullBus(c+6753,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBus(c+4881,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 2U)))),4); - vcdp->fullBit(c+6761,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + vcdp->fullBit(c+4889,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->fullBit(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 + vcdp->fullBit(c+4897,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])); - vcdp->fullBit(c+6777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 + vcdp->fullBit(c+4905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])); - vcdp->fullBit(c+6785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->fullBit(c+6793,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + vcdp->fullBit(c+4913,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+4921,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_to_mrvq_st1e) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ @@ -7559,261 +4304,263 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U])))); - vcdp->fullBit(c+6801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->fullBit(c+6809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+4929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+4937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U])); - vcdp->fullBit(c+6817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 + vcdp->fullBit(c+4945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U])); - vcdp->fullBit(c+6825,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+4953,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->fullBus(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->fullBit(c+6841,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBus(c+4961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+4969,((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->fullBit(c+6849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->fullBit(c+6857,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+4977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+4985,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->fullBit(c+6865,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+4993,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->fullBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+6881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+6897,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) + vcdp->fullBit(c+5001,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+5009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+5017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+5025,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->fullBit(c+6913,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+5033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+5041,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU))))))); - vcdp->fullBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) + vcdp->fullBit(c+5049,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->fullBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->fullBit(c+6945,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + vcdp->fullBit(c+5057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+5065,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+5073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+5081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] >> 6U)))); - vcdp->fullBit(c+6953,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->fullBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->fullQuad(c+6969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->fullBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->fullArray(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->fullBit(c+7033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->fullBus(c+7041,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBit(c+5089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+5097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+5113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+5121,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+5161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+5169,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))),4); - vcdp->fullBus(c+7049,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBus(c+5177,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x12U))),4); - vcdp->fullBus(c+7057,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBus(c+5185,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 2U))),16); - __Vtemp1029[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1029[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1029[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1029[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+7065,(__Vtemp1029),120); - __Vtemp1030[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1030[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1030[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1030[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+7097,(__Vtemp1030),128); - vcdp->fullQuad(c+7129,((VL_ULL(0x3ffffffffff) + __Vtemp563[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp563[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp563[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp563[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+5193,(__Vtemp563),120); + __Vtemp564[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp564[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp564[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp564[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+5225,(__Vtemp564),128); + vcdp->fullQuad(c+5257,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+7145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+7153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+7161,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBit(c+5273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+5281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+5289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U) & VL_NEGATE_I((IData)( (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->fullArray(c+7169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->fullBit(c+7249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->fullBus(c+7257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->fullBus(c+7265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullArray(c+7273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->fullBus(c+7337,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->fullBit(c+7345,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 + vcdp->fullArray(c+5297,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+5377,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+5385,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+5393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+5401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+5465,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+5473,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])); - vcdp->fullBus(c+7353,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 + vcdp->fullBus(c+5481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writeword_st1 [0U]),32); - __Vtemp1031[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp565[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][0U]; - __Vtemp1031[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp565[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][1U]; - __Vtemp1031[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp565[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][2U]; - __Vtemp1031[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 + __Vtemp565[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__writedata_st1 [0U][3U]; - vcdp->fullArray(c+7361,(__Vtemp1031),128); - vcdp->fullBus(c+7393,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullArray(c+5489,(__Vtemp565),128); + vcdp->fullBus(c+5521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]),2); - vcdp->fullBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+7417,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+7425,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+7433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+7465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+7473,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + vcdp->fullBit(c+5529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+5537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+5545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+5553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+5561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+5593,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+5601,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+5609,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])]),16); - vcdp->fullBus(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1032[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + vcdp->fullBus(c+5617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp566[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1032[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + __Vtemp566[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1032[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + __Vtemp566[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1032[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + __Vtemp566[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->fullArray(c+7497,(__Vtemp1032),128); - vcdp->fullBit(c+7529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + vcdp->fullArray(c+5625,(__Vtemp566),128); + vcdp->fullBit(c+5657,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])); - vcdp->fullBit(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + vcdp->fullBit(c+5665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U])); - vcdp->fullBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+7553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+7609,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+7617,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+7625,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+7633,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBus(c+5673,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+5681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+5713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+5721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+5729,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+5737,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+5745,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+5753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+5761,((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->fullBit(c+7641,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+5769,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->fullBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->fullBit(c+7657,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) + vcdp->fullBit(c+5777,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+5785,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->fullBit(c+7665,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+5793,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+7673,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+5801,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+7681,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+5809,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+7689,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+5817,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+7697,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->fullArray(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->fullArray(c+7753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->fullBus(c+7833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->fullBus(c+7841,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->fullBit(c+5825,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+5833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->fullArray(c+5881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+5961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+5969,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->fullBus(c+7849,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+7857,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+7865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+7873,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) + vcdp->fullBus(c+5977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+5985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+5993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+6001,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->fullBit(c+7881,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->fullBit(c+7889,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->fullBit(c+7897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->fullBit(c+6009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+6017,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+6025,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->fullArray(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->fullArray(c+7929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->fullBit(c+7953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->fullArray(c+7961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->fullArray(c+8017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->fullBit(c+8073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->fullBit(c+8081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); - vcdp->fullBus(c+8089,((0x1ffffffU & (IData)( + vcdp->fullArray(c+6033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+6057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+6081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+6089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->fullArray(c+6145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->fullBit(c+6201,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+6209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)); + vcdp->fullBus(c+6217,((0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->fullBit(c+8097,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU)))),26); + vcdp->fullBit(c+6225,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))))); - vcdp->fullBus(c+8105,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->fullBit(c+8113,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->fullBus(c+8121,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1033[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1033[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1033[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1033[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->fullArray(c+8129,(__Vtemp1033),128); - vcdp->fullBit(c+8161,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); - vcdp->fullBit(c+8169,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+8177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->fullBus(c+8185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->fullBit(c+8193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->fullBus(c+8201,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + vcdp->fullBus(c+6233,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); + vcdp->fullBit(c+6241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop)); + vcdp->fullBus(c+6249,((0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),26); + __Vtemp567[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; + __Vtemp567[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; + __Vtemp567[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; + __Vtemp567[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; + vcdp->fullArray(c+6257,(__Vtemp567),128); + vcdp->fullBit(c+6289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)); + vcdp->fullBit(c+6297,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); + vcdp->fullBit(c+6305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); + vcdp->fullBus(c+6313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); + vcdp->fullBit(c+6321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)); + vcdp->fullBus(c+6329,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) >> (0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 2U))))),4); - vcdp->fullBus(c+8209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->fullBus(c+8217,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + vcdp->fullBus(c+6337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0),30); + vcdp->fullBus(c+6345,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))) ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ ((IData)(1U) @@ -7826,52 +4573,52 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U))))),32); - vcdp->fullBit(c+8225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->fullBit(c+8233,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->fullBit(c+8241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->fullBit(c+8249,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->fullBit(c+8257,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & (( + vcdp->fullBit(c+6353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+6361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+6369,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+6377,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+6385,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))))); - vcdp->fullBit(c+8265,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->fullBit(c+8273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->fullBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->fullBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->fullBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->fullBit(c+8305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->fullBit(c+8313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->fullBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->fullBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->fullBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->fullBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->fullBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->fullBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->fullBit(c+8369,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) + vcdp->fullBit(c+6393,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+6401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+6409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+6417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+6425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+6433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+6441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+6449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+6457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+6465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+6473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+6481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+6489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+6497,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->fullBus(c+8377,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU + vcdp->fullBus(c+6505,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? - ((0x18fU + ((0x19fU >= (0x1ffU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? - (0x1ffffffU + (0x3ffffffU & (((0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -7879,40 +4626,40 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) : 0U) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) + >> 4U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? - (0x1ffffffU + (0x3ffffffU & (IData)( (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1dU))) - : 0U)))))),25); - vcdp->fullBus(c+8385,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) + : 0U)))))),26); + vcdp->fullBus(c+6513,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_addr_st0) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (3U & ( @@ -7923,7 +4670,7 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U))) : 0U)))),2); - vcdp->fullBus(c+8393,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBus(c+6521,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -7950,20 +4697,20 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) << 5U)))) : 0U))),32); - __Vtemp1038[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1038[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1038[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1038[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->fullArray(c+8401,(__Vtemp1038),128); - vcdp->fullQuad(c+8433,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + __Vtemp572[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp572[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp572[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp572[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+6529,(__Vtemp572),128); + vcdp->fullQuad(c+6561,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? ((VL_ULL(0x1ffffffffff80) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table @@ -8014,20 +4761,20 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) << 7U) : VL_ULL(0))))),49); - vcdp->fullBit(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) + vcdp->fullBit(c+6577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_rw_st0)) ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_pop_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__reqq_req_rw_st0)) ? 1U : 0U))))); - vcdp->fullBit(c+8457,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBit(c+6585,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) ? 1U : 0U))))); - vcdp->fullBit(c+8465,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + vcdp->fullBit(c+6593,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snrq_pop_unqual) @@ -8035,27 +4782,27 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out >> 0x1cU))) : 0U))))); - vcdp->fullBit(c+8473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+8481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+8489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+8497,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+8505,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+8521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); - vcdp->fullBit(c+8569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); - __Vtemp1044[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + vcdp->fullBit(c+6601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+6609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+6617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+6625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+6633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+6649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+6681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+6689,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+6697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp578[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1044[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp578[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1044[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp578[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1044[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp578[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->fullBus(c+8577,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBus(c+6705,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))) - ? 0U : (__Vtemp1044[ + ? 0U : (__Vtemp578[ ((IData)(1U) + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]))] @@ -8064,45 +4811,45 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))) - | (__Vtemp1044[(3U & - vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 - [0U])] + | (__Vtemp578[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + [0U])] >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U] << 5U))))),32); - __Vtemp1045[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp579[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1045[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp579[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1045[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp579[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1045[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + __Vtemp579[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->fullArray(c+8585,(__Vtemp1045),128); - vcdp->fullBus(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->fullBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); - vcdp->fullBit(c+8633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->fullBus(c+8641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + vcdp->fullArray(c+6713,(__Vtemp579),128); + vcdp->fullBus(c+6745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+6753,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+6761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+6769,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c [0U]),16); - vcdp->fullQuad(c+8649,((VL_ULL(0x3ffffffffff) + vcdp->fullQuad(c+6777,((VL_ULL(0x3ffffffffff) & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 7U))),42); - vcdp->fullBus(c+8665,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBus(c+6793,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U]))),2); - vcdp->fullBit(c+8673,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBit(c+6801,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 6U))))); - vcdp->fullBus(c+8681,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 + vcdp->fullBus(c+6809,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__inst_meta_st1 [0U] >> 2U)))),4); - vcdp->fullBit(c+8689,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + vcdp->fullBit(c+6817,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dirty_st1e)))); - vcdp->fullBit(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 + vcdp->fullBit(c+6825,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])); - vcdp->fullBit(c+8705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 + vcdp->fullBit(c+6833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_invalidate_st1 [0U])); - vcdp->fullBit(c+8713,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->fullBit(c+8721,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + vcdp->fullBit(c+6841,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+6849,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_to_mrvq_st1e) | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ @@ -8110,3145 +4857,873 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U])))); - vcdp->fullBit(c+8729,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->fullBit(c+8737,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+6857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+6865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U])); - vcdp->fullBit(c+8745,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 + vcdp->fullBit(c+6873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U])); - vcdp->fullBit(c+8753,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+6881,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_mrvq_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->fullBus(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->fullBit(c+8769,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBus(c+6889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+6897,((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->fullBit(c+8777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->fullBit(c+8785,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+6905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+6913,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & + >> 0x19U))) + == (0x3ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->fullBit(c+8793,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+6921,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU + [0U]) & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])))); - vcdp->fullBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+8809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+8825,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) + vcdp->fullBit(c+6929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+6937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+6945,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+6953,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->fullBit(c+8841,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) + vcdp->fullBit(c+6961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+6969,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add_unqual) & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) | ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU))))))); - vcdp->fullBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) + vcdp->fullBit(c+6977,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwbq_push_stall) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_push_stall)) | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->fullBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->fullBit(c+8873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + vcdp->fullBit(c+6985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+6993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+7001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+7009,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] >> 6U)))); - vcdp->fullBit(c+8881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->fullBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->fullQuad(c+8897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->fullBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->fullArray(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->fullBit(c+8961,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->fullBus(c+8969,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBit(c+7017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+7025,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+7041,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+7049,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+7089,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+7097,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U))),4); - vcdp->fullBus(c+8977,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBus(c+7105,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x12U))),4); - vcdp->fullBus(c+8985,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBus(c+7113,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 2U))),16); - __Vtemp1048[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1048[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1048[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1048[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+8993,(__Vtemp1048),120); - __Vtemp1049[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1049[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1049[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1049[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+9025,(__Vtemp1049),128); - vcdp->fullQuad(c+9057,((VL_ULL(0x3ffffffffff) + __Vtemp582[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp582[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp582[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp582[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+7121,(__Vtemp582),120); + __Vtemp583[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp583[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp583[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp583[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+7153,(__Vtemp583),128); + vcdp->fullQuad(c+7185,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+9073,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+9081,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+9089,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + vcdp->fullBit(c+7201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+7209,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+7217,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] >> 0x16U) & VL_NEGATE_I((IData)( (1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->fullArray(c+9097,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->fullBit(c+9177,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->fullBus(c+9185,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->fullBus(c+9193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullArray(c+9201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->fullBus(c+9265,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->fullBit(c+9273,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 + vcdp->fullArray(c+7225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+7305,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+7313,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+7321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+7329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+7393,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+7401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])); - vcdp->fullBus(c+9281,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 + vcdp->fullBus(c+7409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writeword_st1 [0U]),32); - __Vtemp1050[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp584[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][0U]; - __Vtemp1050[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp584[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][1U]; - __Vtemp1050[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp584[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][2U]; - __Vtemp1050[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 + __Vtemp584[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__writedata_st1 [0U][3U]; - vcdp->fullArray(c+9289,(__Vtemp1050),128); - vcdp->fullBus(c+9321,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullArray(c+7417,(__Vtemp584),128); + vcdp->fullBus(c+7449,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]),2); - vcdp->fullBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+9345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+9353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+9361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+9393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+9401,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + vcdp->fullBit(c+7457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+7465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+7473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+7481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+7489,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+7521,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+7529,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+7537,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])]),16); - vcdp->fullBus(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1051[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + vcdp->fullBus(c+7545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp585[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1051[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + __Vtemp585[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1051[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + __Vtemp585[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1051[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + __Vtemp585[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->fullArray(c+9425,(__Vtemp1051),128); - vcdp->fullBit(c+9457,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + vcdp->fullArray(c+7553,(__Vtemp585),128); + vcdp->fullBit(c+7585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])); - vcdp->fullBit(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + vcdp->fullBit(c+7593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c [0U])); - vcdp->fullBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+9481,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+9537,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+9545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+9553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+9561,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBus(c+7601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+7609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+7641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+7649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+7657,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+7665,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+7673,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+7681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+7689,((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])))); - vcdp->fullBit(c+9569,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 + vcdp->fullBit(c+7697,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->fullBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->fullBit(c+9585,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) + vcdp->fullBit(c+7705,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+7713,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__force_request_miss_st1e) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_snp_st1 [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__is_fill_st1 [0U])) & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__valid_st1 [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->fullBit(c+9593,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+7721,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+9601,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+7729,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+9609,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+7737,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+9617,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 + vcdp->fullBit(c+7745,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__wsel_st1 [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+9625,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->fullArray(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->fullArray(c+9681,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->fullBus(c+9761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->fullBus(c+9769,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + vcdp->fullBit(c+7753,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+7761,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->fullArray(c+7809,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+7889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+7897,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->fullBus(c+9777,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+9785,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+9793,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+9801,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__miss_add) + vcdp->fullBus(c+7905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+7913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); 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(1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->fullBit(c+10393,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->fullBit(c+10401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+10409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+10417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+10425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+10433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+10449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+10481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+10489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); 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+ vcdp->fullBit(c+8281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)); + vcdp->fullBit(c+8289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); + vcdp->fullBit(c+8297,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)); + vcdp->fullBit(c+8305,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); + vcdp->fullBit(c+8313,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss) + & (((0x3ffffffU & (( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) + >> 0x19U))) == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->fullBus(c+10689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->fullBit(c+10697,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->fullBit(c+10705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->fullBit(c+10713,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->fullBit(c+10721,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->fullBit(c+10729,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+10737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+10745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+10753,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+10761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->fullBit(c+10769,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & - (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))))); - vcdp->fullBit(c+10777,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+10785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); - vcdp->fullBit(c+10793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->fullBit(c+10801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->fullBit(c+10809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->fullBit(c+10817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->fullQuad(c+10825,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->fullBit(c+10841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->fullArray(c+10849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->fullBit(c+10889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->fullBus(c+10897,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->fullBus(c+10905,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->fullBus(c+10913,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1067[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1067[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1067[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1067[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+10921,(__Vtemp1067),120); - __Vtemp1068[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1068[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1068[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1068[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+10953,(__Vtemp1068),128); - vcdp->fullQuad(c+10985,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+11001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+11009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+11017,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) - & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); - vcdp->fullArray(c+11025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); - vcdp->fullBit(c+11105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); - vcdp->fullBus(c+11113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); - vcdp->fullBus(c+11121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); - vcdp->fullArray(c+11129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),242); - vcdp->fullBus(c+11193,((0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])),4); - vcdp->fullBit(c+11201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])); - vcdp->fullBus(c+11209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 - [0U]),32); - __Vtemp1069[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x14U)))))); + vcdp->fullBit(c+8321,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e)); + vcdp->fullBit(c+8329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)); + vcdp->fullBit(c+8337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)); + vcdp->fullBit(c+8345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall)); + vcdp->fullBit(c+8353,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall)); + vcdp->fullBit(c+8361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)); + vcdp->fullBit(c+8369,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__stall_bank_pipe)); + vcdp->fullBit(c+8377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_in_pipe)); + vcdp->fullBit(c+8385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1[0])); + vcdp->fullBit(c+8393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__going_to_write_st1[0])); + vcdp->fullBit(c+8401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)); + vcdp->fullBit(c+8409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual)); + vcdp->fullBit(c+8417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual)); + vcdp->fullBit(c+8425,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop)))); + vcdp->fullBus(c+8433,((0x3ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? (0x3ffffffU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? + ((0x19fU + >= + (0x1ffU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? + (0x3ffffffU + & (((0U + == + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) + ? 0U + : + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + ((IData)(1U) + + + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ + (0xfU + & (((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) + >> 5U))] + >> + (0x1fU + & ((IData)(0x1aU) + * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) + : 0U) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? + (0x3ffffffU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0 + >> 4U)) + : + ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? + (0x3ffffffU + & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1dU))) + : 0U)))))),26); + vcdp->fullBus(c+8441,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_addr_st0) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (3U & ( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U))) + : 0U)))),2); + vcdp->fullBus(c+8449,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x15U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? (((0U == (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))) + ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + ((IData)(1U) + + + (3U + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] + << + ((IData)(0x20U) + - + (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U))))) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] + >> (0x1fU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 5U)))) + : 0U))),32); + __Vtemp591[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] + : 0x39U); + __Vtemp591[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] + : 0U); + __Vtemp591[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] + : 0U); + __Vtemp591[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] + : 0U); + vcdp->fullArray(c+8457,(__Vtemp591),128); + vcdp->fullQuad(c+8489,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? ((VL_ULL(0x1ffffffffff80) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) + << 0x3eU) + | (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) + << 0x1eU) + | (VL_ULL(0x3fffffffffffff80) + & ((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) + >> 2U))))) + | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0) + << 6U) + | ((0x3cU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + << 0x1eU) + | (0x3ffffffcU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 2U)))) + | (3U + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] + << 0xdU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] + >> 0x13U)))))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag + << 7U) | (QData)((IData)( + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0) + << 6U) + | ((0x3cU + & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) + >> + (0xfU + & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) + << 2U))) + << 2U)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? ((QData)((IData)( + (0xfffffffU + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) + << 7U) : VL_ULL(0))))),49); + vcdp->fullBit(c+8505,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_rw_st0)) + ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_pop_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__reqq_req_rw_st0)) + ? 1U + : 0U))))); + vcdp->fullBit(c+8513,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] + >> 1U)) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? 1U : 0U))))); + vcdp->fullBit(c+8521,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) + ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) + : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snrq_pop_unqual) + ? (1U & (IData)( + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out + >> 0x1cU))) + : 0U))))); + vcdp->fullBit(c+8529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1[0])); + vcdp->fullBus(c+8537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1[0]),26); + vcdp->fullBus(c+8545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1[0]),2); + vcdp->fullBus(c+8553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1[0]),32); + vcdp->fullQuad(c+8561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1[0]),49); + vcdp->fullArray(c+8577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1[0]),128); + vcdp->fullBit(c+8609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1[0])); + vcdp->fullBit(c+8617,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1[0])); + vcdp->fullBit(c+8625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1[0])); + __Vtemp597[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][0U]; - __Vtemp1069[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + __Vtemp597[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][1U]; - __Vtemp1069[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + __Vtemp597[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][2U]; - __Vtemp1069[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + __Vtemp597[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c [0U][3U]; - vcdp->fullArray(c+11217,(__Vtemp1069),128); - vcdp->fullBus(c+11249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->fullBit(c+11257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+11265,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+11273,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+11281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+11289,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+11321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+11329,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+11337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->fullBus(c+11345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1070[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + vcdp->fullBus(c+8633,((((0U == (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))) + ? 0U : (__Vtemp597[ + ((IData)(1U) + + (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]))] + << ((IData)(0x20U) + - (0x1fU + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))) + | (__Vtemp597[(3U & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U])] + >> (0x1fU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U] + << 5U))))),32); + __Vtemp598[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][0U]; + __Vtemp598[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][1U]; + __Vtemp598[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][2U]; + __Vtemp598[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c + [0U][3U]; + vcdp->fullArray(c+8641,(__Vtemp598),128); + vcdp->fullBus(c+8673,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c + [0U]),20); + vcdp->fullBit(c+8681,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_st1e)); + vcdp->fullBit(c+8689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)); + vcdp->fullBus(c+8697,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c + [0U]),16); + vcdp->fullQuad(c+8705,((VL_ULL(0x3ffffffffff) + & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 7U))),42); + vcdp->fullBus(c+8721,((3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U]))),2); + vcdp->fullBit(c+8729,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] >> 6U))))); + vcdp->fullBus(c+8737,((0xfU & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__inst_meta_st1 + [0U] + >> 2U)))),4); + vcdp->fullBit(c+8745,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dirty_st1e)))); + vcdp->fullBit(c+8753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])); + vcdp->fullBit(c+8761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_invalidate_st1 + [0U])); + vcdp->fullBit(c+8769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); + vcdp->fullBit(c+8777,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_to_mrvq_st1e) + | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])))); + vcdp->fullBit(c+8785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_because_miss)); + vcdp->fullBit(c+8793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U])); + vcdp->fullBit(c+8801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U])); + vcdp->fullBit(c+8809,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_mrvq_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__recover_mrvq_state_st2)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBus(c+8817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U]),26); + vcdp->fullBit(c+8825,((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+8833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); + vcdp->fullBit(c+8841,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfpq_pop_unqual)) + & ((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == (0x3ffffffU & + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); + vcdp->fullBit(c+8849,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U]) & ((0x3ffffffU + & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))) + == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))); + vcdp->fullBit(c+8857,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual)); + vcdp->fullBit(c+8865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add)); + vcdp->fullBit(c+8873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)); + vcdp->fullBit(c+8881,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + >> 6U))) & (~ + (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+8889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_unqual)); + vcdp->fullBit(c+8897,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_unqual) + & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + | ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1aU) & (~ + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + >> 0x1bU))))))); + vcdp->fullBit(c+8905,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual) + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) + & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwbq_push_stall) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_push_stall)) + | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dram_fill_req_stall)))))); + vcdp->fullBit(c+8913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_dwb_in)); + vcdp->fullBit(c+8921,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_is_snp_in)); + vcdp->fullBit(c+8929,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 7U)))); + vcdp->fullBit(c+8937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] + >> 6U)))); + vcdp->fullBit(c+8945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_push_unqual)); + vcdp->fullQuad(c+8953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),55); + vcdp->fullBit(c+8969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); + vcdp->fullArray(c+8977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),154); + vcdp->fullBit(c+9017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); + vcdp->fullBus(c+9025,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U))),4); + vcdp->fullBus(c+9033,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x12U))),4); + vcdp->fullBus(c+9041,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 2U))),16); + __Vtemp601[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + >> 0xaU)); + __Vtemp601[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] + >> 0xaU)); + __Vtemp601[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] + >> 0xaU)); + __Vtemp601[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + << 0x16U) | + (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] + >> 0xaU))); + vcdp->fullArray(c+9049,(__Vtemp601),120); + __Vtemp602[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] + >> 0xaU)); + __Vtemp602[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] + >> 0xaU)); + __Vtemp602[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] + >> 0xaU)); + __Vtemp602[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] + << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] + >> 0xaU)); + vcdp->fullArray(c+9081,(__Vtemp602),128); + vcdp->fullQuad(c+9113,((VL_ULL(0x3ffffffffff) + & (((QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) + << 0x20U) | (QData)((IData)( + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); + vcdp->fullBit(c+9129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); + vcdp->fullBit(c+9137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); + vcdp->fullBus(c+9145,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] + >> 0x16U) & + VL_NEGATE_I((IData)( + (1U + & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); + vcdp->fullArray(c+9153,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out),314); + vcdp->fullBit(c+9233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__reading)); + vcdp->fullBus(c+9241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+9249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i),32); + vcdp->fullArray(c+9257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__s0_1_c0__in),243); + vcdp->fullBus(c+9321,((0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])),6); + vcdp->fullBit(c+9329,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])); + vcdp->fullBus(c+9337,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writeword_st1 + [0U]),32); + __Vtemp603[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][0U]; + __Vtemp603[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][1U]; + __Vtemp603[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][2U]; + __Vtemp603[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__writedata_st1 + [0U][3U]; + vcdp->fullArray(c+9345,(__Vtemp603),128); + vcdp->fullBus(c+9377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]),2); + vcdp->fullBit(c+9385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); + vcdp->fullBit(c+9393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); + vcdp->fullBus(c+9401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); + vcdp->fullBus(c+9409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),20); + vcdp->fullArray(c+9417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); + vcdp->fullBit(c+9449,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBit(c+9457,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty + >> (0x3fU + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])))))); + vcdp->fullBus(c+9465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),16); + vcdp->fullBus(c+9473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U])]),20); + __Vtemp604[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][0U]; - __Vtemp1070[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + __Vtemp604[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][1U]; - __Vtemp1070[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + __Vtemp604[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][2U]; - __Vtemp1070[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + __Vtemp604[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data + [(0x3fU & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 [0U])][3U]; - vcdp->fullArray(c+11353,(__Vtemp1070),128); - vcdp->fullBit(c+11385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->fullBit(c+11393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->fullBus(c+11401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+11409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+11441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+11449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+11457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+11465,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+11473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+11481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+11489,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + vcdp->fullArray(c+9481,(__Vtemp604),128); + vcdp->fullBit(c+9513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])); + vcdp->fullBit(c+9521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c + [0U])); + vcdp->fullBus(c+9529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); + vcdp->fullArray(c+9537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); + vcdp->fullBit(c+9569,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); + vcdp->fullBit(c+9577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); + vcdp->fullBit(c+9585,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); + vcdp->fullBus(c+9593,((0xfffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__addr_st1 + [0U] >> 6U))),20); + vcdp->fullBus(c+9601,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); + vcdp->fullBit(c+9609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); + vcdp->fullBit(c+9617,((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U])) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])))); + vcdp->fullBit(c+9625,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 [0U])) & - (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->fullBit(c+11497,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->fullBit(c+11505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->fullBit(c+11513,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->fullBit(c+11521,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+11529,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+11537,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+11545,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+11553,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->fullArray(c+11561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->fullArray(c+11609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->fullBus(c+11689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->fullBus(c+11697,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->fullBus(c+11705,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+11713,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+11721,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+11729,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->fullBit(c+11737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->fullBit(c+11745,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->fullBit(c+11753,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->fullArray(c+11761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->fullArray(c+11785,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->fullBit(c+11809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->fullArray(c+11817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->fullArray(c+11873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->fullBit(c+11929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->fullBit(c+11937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)); - vcdp->fullBus(c+11945,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->fullBit(c+11953,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))))); - vcdp->fullBus(c+11961,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->fullBit(c+11969,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->fullBus(c+11977,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1071[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1071[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1071[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1071[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->fullArray(c+11985,(__Vtemp1071),128); - vcdp->fullBit(c+12017,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)); - vcdp->fullBit(c+12025,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+12033,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->fullBus(c+12041,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->fullBit(c+12049,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->fullBus(c+12057,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->fullBus(c+12065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->fullBus(c+12073,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->fullBit(c+12081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)); - vcdp->fullBit(c+12089,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible)); - vcdp->fullBit(c+12097,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)); - vcdp->fullBit(c+12105,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match)))); - vcdp->fullBit(c+12113,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss) - & (((0x1ffffffU & ( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]) & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))))); - vcdp->fullBit(c+12121,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e)); - vcdp->fullBit(c+12129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->fullBit(c+12137,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->fullBit(c+12145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->fullBit(c+12153,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->fullBit(c+12161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->fullBit(c+12169,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->fullBit(c+12177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->fullBit(c+12185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->fullBit(c+12193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->fullBit(c+12201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->fullBit(c+12209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->fullBit(c+12217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->fullBit(c+12225,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->fullBus(c+12233,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->fullBus(c+12241,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->fullBus(c+12249,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1076[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1076[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1076[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1076[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->fullArray(c+12257,(__Vtemp1076),128); - vcdp->fullQuad(c+12289,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))),49); - vcdp->fullBit(c+12305,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->fullBit(c+12313,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->fullBit(c+12321,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->fullBit(c+12329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+12337,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+12345,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+12353,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+12361,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+12377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+12409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+12417,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_invalidate_st1[0])); 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- vcdp->fullBit(c+12569,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e)); - vcdp->fullBit(c+12577,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_to_mrvq_st1e) - | ((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U])))); - vcdp->fullBit(c+12585,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_because_miss)); - vcdp->fullBit(c+12593,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U])); - vcdp->fullBit(c+12601,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U])); - vcdp->fullBit(c+12609,((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_mrvq_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__recover_mrvq_state_st2)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])))); 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- vcdp->fullBit(c+12657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+12665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+12673,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+12681,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+12689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_unqual)); - vcdp->fullBit(c+12697,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_unqual) - & ((~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - | ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU) & - (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU))))))); - vcdp->fullBit(c+12705,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+12713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_is_dwb_in)); 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- vcdp->fullBus(c+12833,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->fullBus(c+12841,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1086[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1086[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1086[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1086[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+12849,(__Vtemp1086),120); - __Vtemp1087[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1087[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1087[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1087[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+12881,(__Vtemp1087),128); - vcdp->fullQuad(c+12913,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+12929,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+12937,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+12945,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) - & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); 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- __Vtemp1088[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1088[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1088[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1088[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->fullArray(c+13145,(__Vtemp1088),128); - vcdp->fullBus(c+13177,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->fullBit(c+13185,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+13193,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+13201,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+13209,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+13217,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+13249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+13257,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+13265,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->fullBus(c+13273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1089[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1089[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1089[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1089[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->fullArray(c+13281,(__Vtemp1089),128); - vcdp->fullBit(c+13313,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->fullBit(c+13321,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->fullBus(c+13329,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+13337,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+13369,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+13377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+13385,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+13393,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+13401,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+13409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+13417,((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 + vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c + [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 [0U])) & - (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->fullBit(c+13425,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); 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- vcdp->fullBus(c+13633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+13649,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+13657,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->fullBit(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->fullBit(c+13673,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->fullBit(c+13681,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->fullArray(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->fullArray(c+13713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->fullBit(c+13737,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->fullArray(c+13745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->fullArray(c+13801,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->fullBit(c+13857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->fullBit(c+13865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)); - vcdp->fullBus(c+13873,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); 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- vcdp->fullArray(c+13913,(__Vtemp1090),128); - vcdp->fullBit(c+13945,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)); - vcdp->fullBit(c+13953,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+13961,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->fullBus(c+13969,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->fullBit(c+13977,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->fullBus(c+13985,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->fullBus(c+13993,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->fullBus(c+14001,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->fullBit(c+14009,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)); 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- vcdp->fullBit(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->fullBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->fullBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->fullBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->fullBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->fullBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->fullBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->fullBit(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->fullBit(c+14121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->fullBit(c+14129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->fullBit(c+14137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->fullBit(c+14145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->fullBit(c+14153,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->fullBus(c+14161,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->fullBus(c+14169,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->fullBus(c+14177,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1095[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1095[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1095[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1095[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->fullArray(c+14185,(__Vtemp1095),128); - vcdp->fullQuad(c+14217,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))),49); - vcdp->fullBit(c+14233,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->fullBit(c+14241,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->fullBit(c+14249,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->fullBit(c+14257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+14265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+14273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+14281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+14289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+14305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+14337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+14345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_invalidate_st1[0])); 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- __Vtemp1102[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1102[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1102[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1102[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->fullArray(c+14369,(__Vtemp1102),128); - vcdp->fullBus(c+14401,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->fullBit(c+14409,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_st1e)); - vcdp->fullBit(c+14417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->fullBus(c+14425,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); 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- vcdp->fullBit(c+14585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+14593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+14601,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+14609,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+14617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwbq_push_unqual)); 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- vcdp->fullBit(c+14649,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->fullBit(c+14657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->fullBit(c+14665,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->fullBit(c+14673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->fullQuad(c+14681,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->fullBit(c+14697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->fullArray(c+14705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->fullBit(c+14745,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->fullBus(c+14753,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->fullBus(c+14761,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->fullBus(c+14769,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1105[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1105[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1105[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1105[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+14777,(__Vtemp1105),120); - __Vtemp1106[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1106[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1106[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1106[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+14809,(__Vtemp1106),128); - vcdp->fullQuad(c+14841,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+14857,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+14873,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) - & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); 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- __Vtemp1107[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1107[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1107[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1107[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->fullArray(c+15073,(__Vtemp1107),128); - vcdp->fullBus(c+15105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->fullBit(c+15113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+15121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+15129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+15137,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+15145,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+15177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+15185,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+15193,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->fullBus(c+15201,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1108[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1108[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1108[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1108[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->fullArray(c+15209,(__Vtemp1108),128); - vcdp->fullBit(c+15241,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->fullBit(c+15249,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->fullBus(c+15257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+15265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+15297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+15305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+15313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+15321,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+15329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+15337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+15345,((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->fullBit(c+15353,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->fullBit(c+15361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->fullBit(c+15369,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->fullBit(c+15377,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+15385,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+15393,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+15401,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+15409,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->fullArray(c+15417,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->fullArray(c+15465,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->fullBus(c+15545,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->fullBus(c+15553,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->fullBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+15585,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->fullBit(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->fullBit(c+15601,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->fullBit(c+15609,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->fullArray(c+15617,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->fullArray(c+15641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->fullBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->fullArray(c+15673,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->fullArray(c+15729,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->fullBit(c+15785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->fullBit(c+15793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)); - vcdp->fullBus(c+15801,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); 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- vcdp->fullArray(c+15841,(__Vtemp1109),128); - vcdp->fullBit(c+15873,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)); - vcdp->fullBit(c+15881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+15889,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->fullBus(c+15897,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->fullBit(c+15905,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->fullBus(c+15913,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->fullBus(c+15921,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->fullBus(c+15929,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->fullBit(c+15937,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)); 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- vcdp->fullBit(c+15985,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->fullBit(c+15993,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->fullBit(c+16001,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->fullBit(c+16009,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->fullBit(c+16017,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->fullBit(c+16025,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->fullBit(c+16033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->fullBit(c+16041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->fullBit(c+16049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->fullBit(c+16057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->fullBit(c+16065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->fullBit(c+16073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->fullBit(c+16081,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->fullBus(c+16089,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->fullBus(c+16097,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->fullBus(c+16105,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1114[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1114[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1114[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1114[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->fullArray(c+16113,(__Vtemp1114),128); - vcdp->fullQuad(c+16145,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))),49); - vcdp->fullBit(c+16161,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->fullBit(c+16169,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->fullBit(c+16177,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->fullBit(c+16185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+16193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+16201,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+16209,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+16217,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+16233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+16265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+16273,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_invalidate_st1[0])); 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- __Vtemp1121[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1121[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1121[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1121[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->fullArray(c+16297,(__Vtemp1121),128); - vcdp->fullBus(c+16329,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->fullBit(c+16337,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_st1e)); - vcdp->fullBit(c+16345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->fullBus(c+16353,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); 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- vcdp->fullBus(c+16473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]),25); - vcdp->fullBit(c+16481,((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->fullBit(c+16489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)); - vcdp->fullBit(c+16497,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfpq_pop_unqual)) - & ((0x1ffffffU & (( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == (0x1ffffffU & - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]))))); - vcdp->fullBit(c+16505,((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual) - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U]) & ((0x1ffffffU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))) - == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])))); - vcdp->fullBit(c+16513,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+16521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+16529,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+16537,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+16545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwbq_push_unqual)); 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- vcdp->fullBit(c+16577,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->fullBit(c+16585,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->fullBit(c+16593,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->fullBit(c+16601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->fullQuad(c+16609,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->fullBit(c+16625,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->fullArray(c+16633,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->fullBit(c+16673,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->fullBus(c+16681,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->fullBus(c+16689,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->fullBus(c+16697,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1124[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1124[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1124[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1124[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+16705,(__Vtemp1124),120); - __Vtemp1125[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1125[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1125[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1125[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+16737,(__Vtemp1125),128); - vcdp->fullQuad(c+16769,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+16785,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+16793,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+16801,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) - & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); 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- __Vtemp1126[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1126[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1126[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1126[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->fullArray(c+17001,(__Vtemp1126),128); - vcdp->fullBus(c+17033,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->fullBit(c+17041,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+17049,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+17057,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+17065,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+17073,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+17105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+17113,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+17121,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->fullBus(c+17129,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1127[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1127[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1127[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1127[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->fullArray(c+17137,(__Vtemp1127),128); - vcdp->fullBit(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->fullBit(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->fullBus(c+17185,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+17193,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+17225,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+17233,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+17241,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+17249,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+17257,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+17265,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+17273,((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->fullBit(c+17281,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->fullBit(c+17289,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->fullBit(c+17297,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->fullBit(c+17305,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+17313,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+17321,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+17329,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+17337,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->fullArray(c+17345,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->fullArray(c+17393,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->fullBus(c+17473,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->fullBus(c+17481,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->fullBus(c+17489,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+17497,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+17505,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+17513,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->fullBit(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->fullBit(c+17529,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->fullBit(c+17537,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->fullArray(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->fullArray(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->fullBit(c+17593,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->fullArray(c+17601,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->fullArray(c+17657,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->fullBit(c+17713,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->fullBit(c+17721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)); - vcdp->fullBus(c+17729,((0x1ffffffU & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU)))),25); - vcdp->fullBit(c+17737,((1U & (IData)((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))))); - vcdp->fullBus(c+17745,((0xfffffffU & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out))),28); - vcdp->fullBit(c+17753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop)); - vcdp->fullBus(c+17761,((0x1ffffffU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U])),25); - __Vtemp1128[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U]; - __Vtemp1128[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U]; - __Vtemp1128[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U]; - __Vtemp1128[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U]; - vcdp->fullArray(c+17769,(__Vtemp1128),128); - vcdp->fullBit(c+17801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)); - vcdp->fullBit(c+17809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request))))); - vcdp->fullBit(c+17817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_has_request)); - vcdp->fullBus(c+17825,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index),2); - vcdp->fullBit(c+17833,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)); - vcdp->fullBus(c+17841,((0xfU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> (0xfU & - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))))),4); - vcdp->fullBus(c+17849,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0),30); - vcdp->fullBus(c+17857,((((0U == (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << ((IData)(0x20U) - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))),32); - vcdp->fullBit(c+17865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)); 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- vcdp->fullBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__recover_mrvq_state_st2)); - vcdp->fullBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)); - vcdp->fullBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_stall)); - vcdp->fullBit(c+17937,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall)); - vcdp->fullBit(c+17945,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)); - vcdp->fullBit(c+17953,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__stall_bank_pipe)); - vcdp->fullBit(c+17961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_in_pipe)); - vcdp->fullBit(c+17969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1[0])); - vcdp->fullBit(c+17977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__going_to_write_st1[0])); - vcdp->fullBit(c+17985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual)); - vcdp->fullBit(c+17993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual)); - vcdp->fullBit(c+18001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual)); - vcdp->fullBit(c+18009,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop)))); - vcdp->fullBus(c+18017,((0x1ffffffU & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? (0x1ffffffU - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[4U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? - ((0x18fU - >= - (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? - (0x1ffffffU - & (((0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? - (0x1ffffffU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0 - >> 5U)) - : - ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? - (0x1ffffffU - & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1dU))) - : 0U)))))),25); - vcdp->fullBus(c+18025,((3U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_addr_st0) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (3U & - ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U))) - : 0U)))),2); - vcdp->fullBus(c+18033,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? (((0U == (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))) - ? 0U : (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - ((IData)(1U) - + - (3U - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata[ - (3U & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index))] - >> (0x1fU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 5U)))) - : 0U))),32); - __Vtemp1133[0U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[0U] - : 0x39U); - __Vtemp1133[1U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[1U] - : 0U); - __Vtemp1133[2U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[2U] - : 0U); - __Vtemp1133[3U] = ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out[3U] - : 0U); - vcdp->fullArray(c+18041,(__Vtemp1133),128); - vcdp->fullQuad(c+18073,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? ((VL_ULL(0x1ffffffffff80) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x3eU) - | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x1eU) - | (VL_ULL(0x3fffffffffffff80) - & ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 2U))))) - | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0) - << 6U) - | ((0x3cU - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) - | (0x3ffffffcU - & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))) - | (3U - & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - ? ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag - << 7U) | (QData)((IData)( - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0) - << 6U) - | ((0x3cU - & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen) - >> - (0xfU - & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index) - << 2U))) - << 2U)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__qual_request_index)))))) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? ((QData)((IData)( - (0xfffffffU - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out)))) - << 7U) - : VL_ULL(0))))),49); - vcdp->fullBit(c+18089,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfpq_pop_unqual) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_rw_st0)) - ? 1U : (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_pop_unqual) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__reqq_req_rw_st0)) - ? 1U - : 0U))))); - vcdp->fullBit(c+18097,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? 1U : 0U))))); - vcdp->fullBit(c+18105,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__dequeue_possible) - ? (1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]) - : ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snrq_pop_unqual) - ? (1U & (IData)( - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out - >> 0x1cU))) - : 0U))))); - vcdp->fullBit(c+18113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1[0])); - vcdp->fullBus(c+18121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1[0]),25); - vcdp->fullBus(c+18129,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1[0]),2); - vcdp->fullBus(c+18137,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writeword_st1[0]),32); - vcdp->fullQuad(c+18145,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__inst_meta_st1[0]),49); - vcdp->fullArray(c+18161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1[0]),128); - vcdp->fullBit(c+18193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1[0])); - vcdp->fullBit(c+18201,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_invalidate_st1[0])); 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- __Vtemp1140[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][0U]; - __Vtemp1140[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][1U]; - __Vtemp1140[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][2U]; - __Vtemp1140[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c - [0U][3U]; - vcdp->fullArray(c+18225,(__Vtemp1140),128); - vcdp->fullBus(c+18257,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c - [0U]),21); - vcdp->fullBit(c+18265,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_st1e)); - vcdp->fullBit(c+18273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dirty_st1e)); - vcdp->fullBus(c+18281,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c - [0U]),16); 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- vcdp->fullBit(c+18441,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_unqual)); - vcdp->fullBit(c+18449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add)); - vcdp->fullBit(c+18457,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)); - vcdp->fullBit(c+18465,(((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual) - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))) - & (~ (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U))) & (~ - (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_stall) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_push_stall)) - | (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dram_fill_req_stall)))))); - vcdp->fullBit(c+18473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwbq_push_unqual)); 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- vcdp->fullBit(c+18505,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_is_snp_in)); - vcdp->fullBit(c+18513,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 6U)))); - vcdp->fullBit(c+18521,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out[6U] - >> 5U)))); - vcdp->fullBit(c+18529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_push_unqual)); - vcdp->fullQuad(c+18537,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__snp_req_queue__data_out),54); - vcdp->fullBit(c+18553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__reading)); - vcdp->fullArray(c+18561,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dfp_queue__data_out),153); - vcdp->fullBit(c+18601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__reading)); - vcdp->fullBus(c+18609,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U))),4); - vcdp->fullBus(c+18617,((0xfU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x12U))),4); - vcdp->fullBus(c+18625,((0xffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 2U))),16); - __Vtemp1143[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - >> 0xaU)); - __Vtemp1143[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[6U] - >> 0xaU)); - __Vtemp1143[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[7U] - >> 0xaU)); - __Vtemp1143[3U] = (0xffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - << 0x16U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[8U] - >> 0xaU))); - vcdp->fullArray(c+18633,(__Vtemp1143),120); - __Vtemp1144[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U] - >> 0xaU)); - __Vtemp1144[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[2U] - >> 0xaU)); - __Vtemp1144[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[3U] - >> 0xaU)); - __Vtemp1144[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[5U] - << 0x16U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[4U] - >> 0xaU)); - vcdp->fullArray(c+18665,(__Vtemp1144),128); - vcdp->fullQuad(c+18697,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[0U]))))),42); - vcdp->fullBit(c+18713,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)); - vcdp->fullBit(c+18721,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__pop_qual)); - vcdp->fullBus(c+18729,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT____Vcellout__reqq_queue__data_out[9U] - >> 0x16U) - & VL_NEGATE_I((IData)( - (1U - & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__out_empty)))))))),4); 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- __Vtemp1145[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][0U]; - __Vtemp1145[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][1U]; - __Vtemp1145[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][2U]; - __Vtemp1145[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__writedata_st1 - [0U][3U]; - vcdp->fullArray(c+18929,(__Vtemp1145),128); - vcdp->fullBus(c+18961,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]),2); - vcdp->fullBit(c+18969,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c[0])); - vcdp->fullBit(c+18977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c[0])); - vcdp->fullBus(c+18985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirtyb_st1c[0]),16); - vcdp->fullBus(c+18993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_tag_st1c[0]),21); - vcdp->fullArray(c+19001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_data_st1c[0]),128); - vcdp->fullBit(c+19033,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBit(c+19041,((1U & ((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty) - >> (0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U]))))); - vcdp->fullBus(c+19049,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])]),16); - vcdp->fullBus(c+19057,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])]),21); - __Vtemp1146[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][0U]; - __Vtemp1146[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][1U]; - __Vtemp1146[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][2U]; - __Vtemp1146[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [(0xfU & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U])][3U]; - vcdp->fullArray(c+19065,(__Vtemp1146),128); - vcdp->fullBit(c+19097,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])); - vcdp->fullBit(c+19105,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_dirty_st1c - [0U])); - vcdp->fullBus(c+19113,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable),16); - vcdp->fullArray(c+19121,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__data_write),128); - vcdp->fullBit(c+19153,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__snoop_hit_no_pending)); - vcdp->fullBit(c+19161,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match)); - vcdp->fullBit(c+19169,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_writefill)); - vcdp->fullBus(c+19177,((0x1fffffU & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__addr_st1 - [0U] >> 4U))),21); - vcdp->fullBus(c+19185,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__we),16); - vcdp->fullBit(c+19193,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)); - vcdp->fullBit(c+19201,((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])))); - vcdp->fullBit(c+19209,(((((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U] & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__read_valid_st1c - [0U]) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) & - (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); - vcdp->fullBit(c+19217,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); - vcdp->fullBit(c+19225,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__force_request_miss_st1e) - & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_snp_st1 - [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__is_fill_st1 - [0U])) - & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__valid_st1 - [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); - vcdp->fullBit(c+19233,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+19241,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+19249,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+19257,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__wsel_st1 - [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); - vcdp->fullBit(c+19265,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); - vcdp->fullArray(c+19273,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),167); - vcdp->fullArray(c+19321,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); - vcdp->fullBus(c+19401,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); - vcdp->fullBus(c+19409,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) - << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); - vcdp->fullBus(c+19417,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); - vcdp->fullBit(c+19425,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); - vcdp->fullBit(c+19433,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); - vcdp->fullBit(c+19441,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__miss_add_is_mrvq)))); - vcdp->fullBit(c+19449,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); - vcdp->fullBit(c+19457,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); - vcdp->fullBit(c+19465,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) - & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); - vcdp->fullArray(c+19473,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); - vcdp->fullArray(c+19497,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); - vcdp->fullBit(c+19521,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); - vcdp->fullArray(c+19529,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),199); - vcdp->fullArray(c+19585,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),199); - vcdp->fullBit(c+19641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); - vcdp->fullBit(c+19649,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19657,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19665,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19673,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tags_match))))); + vcdp->fullBit(c+9633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss)); + vcdp->fullBit(c+9641,((((((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__force_request_miss_st1e) + & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_snp_st1 + [0U])) & (~ vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__is_fill_st1 + [0U])) + & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__valid_st1 + [0U]) & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__real_miss))))); + vcdp->fullBit(c+9649,(((0U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9657,(((1U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9665,(((2U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9673,(((3U == vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__wsel_st1 + [0U]) & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__should_write)))); + vcdp->fullBit(c+9681,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__use_write_enable)))); + vcdp->fullArray(c+9689,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT____Vcellinp__s0_1_c0__in),166); + vcdp->fullArray(c+9737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__st_1e_2__in),316); + vcdp->fullBus(c+9817,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready),16); + vcdp->fullBus(c+9825,((0xffffU & (((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)) + << (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr)))),16); + vcdp->fullBus(c+9833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_address_match),16); + vcdp->fullBit(c+9841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push)); + vcdp->fullBit(c+9849,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_pop)); + vcdp->fullBit(c+9857,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__miss_add_is_mrvq)))); + vcdp->fullBit(c+9865,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__increment_head)); + vcdp->fullBit(c+9873,((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__make_ready)))); + vcdp->fullBit(c+9881,(((IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__mrvq_push) + & (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__mrvq_init_ready_state_st2)))); + vcdp->fullArray(c+9889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__cwb_queue__data_in),76); + vcdp->fullArray(c+9913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__cwb_queue__data_out),76); + vcdp->fullBit(c+9937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__writing)); + vcdp->fullArray(c+9945,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellinp__dwb_queue__data_in),200); + vcdp->fullArray(c+10001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT____Vcellout__dwb_queue__data_out),200); + vcdp->fullBit(c+10057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__writing)); + vcdp->fullBit(c+10065,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10073,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10081,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10089,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19681,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19689,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19697,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19705,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19713,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + >> 0x19U)))),26); + vcdp->fullBit(c+10097,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10105,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10113,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10121,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10129,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19721,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19729,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19737,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19745,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19753,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + >> 0x19U)))),26); + vcdp->fullBit(c+10137,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10145,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10153,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10161,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10169,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19761,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19769,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19777,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19785,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19793,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) + >> 0x19U)))),26); + vcdp->fullBit(c+10177,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10185,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10193,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); + vcdp->fullBit(c+10201,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10209,((0x3ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19801,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19809,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19817,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19825,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19833,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19841,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19849,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19857,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19865,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19873,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19881,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19889,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19897,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19905,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19913,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19921,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19929,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19937,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBit(c+19945,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19953,((0x1ffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU)))),25); - vcdp->fullBit(c+19961,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBit(c+19969,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+19977,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); - vcdp->fullBit(c+19985,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBus(c+19993,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); - vcdp->fullBit(c+20001,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r))))); - vcdp->fullBus(c+20009,(((IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r) - ? vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r - : vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r)),28); - vcdp->fullBit(c+20017,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+20025,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+20033,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); - vcdp->fullBus(c+20041,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[0]),28); - vcdp->fullBus(c+20042,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__data[1]),28); - vcdp->fullBus(c+20057,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),28); - vcdp->fullBus(c+20065,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),28); - vcdp->fullBit(c+20073,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r)); - vcdp->fullBit(c+20081,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r)); - vcdp->fullBit(c+20089,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r)); - vcdp->fullBit(c+20097,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+20105,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),8); - vcdp->fullArray(c+20113,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),224); - vcdp->fullBit(c+20169,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+20177,((1U & (~ (IData)((0U + >> 0x19U)))),26); + vcdp->fullBit(c+10217,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBit(c+10225,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); + vcdp->fullBus(c+10233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_addr),28); + vcdp->fullBit(c+10241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+10249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__use_valid),2); + vcdp->fullBit(c+10257,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->fullBus(c+10265,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk2__DOT__head_r),28); + vcdp->fullBit(c+10273,((1U & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); + vcdp->fullBit(c+10281,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r)); + vcdp->fullBus(c+10289,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid),4); + vcdp->fullArray(c+10297,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_addr),112); + vcdp->fullBit(c+10329,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10337,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__use_per_bank_dram_fill_req_valid))))))); - vcdp->fullBus(c+20185,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),4); - vcdp->fullArray(c+20193,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),232); - vcdp->fullArray(c+20201,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),232); - vcdp->fullArray(c+20209,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),232); - vcdp->fullArray(c+20217,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),232); - vcdp->fullArray(c+20225,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[4]),232); - vcdp->fullArray(c+20233,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[5]),232); - vcdp->fullArray(c+20241,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[6]),232); - vcdp->fullArray(c+20249,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[7]),232); - vcdp->fullArray(c+20705,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),232); - vcdp->fullArray(c+20769,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),232); - vcdp->fullBus(c+20833,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+20841,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+20849,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+20857,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+20865,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),8); - vcdp->fullBit(c+20873,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); - vcdp->fullBus(c+20881,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),8); - vcdp->fullBit(c+20889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+20897,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+20905,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+20913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+20921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullQuad(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->fullBit(c+20945,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBit(c+20953,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBus(c+20961,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+10345,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__size_r),3); + vcdp->fullArray(c+10353,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[0]),116); + vcdp->fullArray(c+10357,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[1]),116); + vcdp->fullArray(c+10361,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[2]),116); + vcdp->fullArray(c+10365,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__data[3]),116); + vcdp->fullArray(c+10481,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),116); + vcdp->fullArray(c+10513,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),116); + vcdp->fullBus(c+10545,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+10553,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+10561,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+10569,(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+10577,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use),4); + vcdp->fullBit(c+10585,((0U == (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use)))); + vcdp->fullBus(c+10593,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original),4); + vcdp->fullBit(c+10601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+10617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+10633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+10641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+10657,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+10665,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+10673,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->fullBus(c+20969,(((0x18fU >= (0x1ffU - & ((IData)(0x19U) + vcdp->fullBus(c+10681,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (( + ? (0x3ffffffU & (( (0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -11256,37 +5731,37 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+20977,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->fullBus(c+10689,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->fullBus(c+20985,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+10697,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->fullQuad(c+20993,((VL_ULL(0x3ffffffffff) + vcdp->fullQuad(c+10705,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -11298,19 +5773,19 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->fullBus(c+21009,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+10721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->fullBit(c+21017,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+10729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->fullBit(c+21025,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+10737,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+21033,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+21041,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+10745,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+10753,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -11319,424 +5794,224 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->fullBit(c+21057,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->fullBit(c+10769,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->fullBus(c+21065,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBus(c+10777,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->fullBit(c+21073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->fullBit(c+21081,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->fullBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+21097,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+21105,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1154[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1154[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1154[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1154[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+21113,(__Vtemp1154),128); - vcdp->fullBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+10801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+10809,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+10817,(((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp612[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp612[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp612[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp612[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+10825,(__Vtemp612),128); + vcdp->fullBit(c+10857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->fullBit(c+21153,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBit(c+10865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->fullBus(c+21161,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+10873,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); - vcdp->fullQuad(c+21169,((VL_ULL(0x1ffffffffffff) + vcdp->fullQuad(c+10881,((VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->fullBus(c+21185,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->fullBit(c+21193,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBus(c+10897,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+10905,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U)))); - vcdp->fullBit(c+21201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10913,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vcdp->fullBit(c+21209,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10921,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x16U)))); - vcdp->fullBit(c+21217,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10929,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U)))); - vcdp->fullBit(c+21225,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)))); - vcdp->fullBit(c+21233,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10945,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU)))); - vcdp->fullBit(c+21241,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+10953,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U)))); - vcdp->fullBit(c+21249,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+21257,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+21265,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+21273,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBus(c+21281,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->fullBus(c+21289,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBit(c+10961,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+10977,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+10985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+10993,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+11001,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))),28); - vcdp->fullBit(c+21297,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->fullBus(c+21305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->fullQuad(c+21313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->fullQuad(c+21315,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->fullQuad(c+21317,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->fullQuad(c+21319,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->fullQuad(c+21321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+21323,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+21325,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+21327,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+21329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+21331,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+21333,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+21335,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->fullQuad(c+21337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->fullQuad(c+21339,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->fullQuad(c+21341,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->fullQuad(c+21343,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->fullQuad(c+21569,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->fullQuad(c+21585,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->fullBus(c+21601,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->fullBus(c+21609,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->fullBus(c+21617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->fullBit(c+21625,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+21633,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); - vcdp->fullArray(c+21641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); - vcdp->fullArray(c+21646,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); - vcdp->fullArray(c+21651,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); 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- vcdp->fullBus(c+22497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); - vcdp->fullArray(c+22505,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); - vcdp->fullArray(c+22515,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); - vcdp->fullArray(c+22525,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); - vcdp->fullArray(c+22535,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); - vcdp->fullArray(c+22545,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); - vcdp->fullArray(c+22555,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); - vcdp->fullArray(c+22565,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); - vcdp->fullArray(c+22575,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); - vcdp->fullArray(c+23145,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); - vcdp->fullArray(c+23225,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); - vcdp->fullBus(c+23305,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+23313,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+23321,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+23329,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullArray(c+23337,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); - __Vtemp1155[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][0U]; - __Vtemp1155[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][1U]; - __Vtemp1155[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][2U]; - __Vtemp1155[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][3U]; - vcdp->fullArray(c+23401,(__Vtemp1155),128); - __Vtemp1156[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][0U]; - __Vtemp1156[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1156[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1156[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->fullArray(c+23433,(__Vtemp1156),128); - __Vtemp1157[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1157[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1157[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1157[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; - vcdp->fullArray(c+23465,(__Vtemp1157),128); - __Vtemp1158[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][0U]; - __Vtemp1158[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][1U]; - __Vtemp1158[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][2U]; - __Vtemp1158[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][3U]; - vcdp->fullArray(c+23497,(__Vtemp1158),128); - __Vtemp1159[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][0U]; - __Vtemp1159[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][1U]; - __Vtemp1159[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][2U]; - __Vtemp1159[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][3U]; - vcdp->fullArray(c+23529,(__Vtemp1159),128); - __Vtemp1160[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][0U]; - __Vtemp1160[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][1U]; - __Vtemp1160[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][2U]; - __Vtemp1160[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][3U]; - vcdp->fullArray(c+23561,(__Vtemp1160),128); - __Vtemp1161[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][0U]; - __Vtemp1161[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][1U]; - __Vtemp1161[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][2U]; - __Vtemp1161[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][3U]; - vcdp->fullArray(c+23593,(__Vtemp1161),128); - __Vtemp1162[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][0U]; - __Vtemp1162[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][1U]; - __Vtemp1162[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][2U]; - __Vtemp1162[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][3U]; - vcdp->fullArray(c+23625,(__Vtemp1162),128); - __Vtemp1163[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][0U]; - __Vtemp1163[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1163[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1163[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->fullArray(c+23657,(__Vtemp1163),128); - __Vtemp1164[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1164[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1164[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; - __Vtemp1164[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; - vcdp->fullArray(c+23689,(__Vtemp1164),128); - __Vtemp1165[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][0U]; - __Vtemp1165[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][1U]; - __Vtemp1165[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][2U]; - __Vtemp1165[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][3U]; - vcdp->fullArray(c+23721,(__Vtemp1165),128); - __Vtemp1166[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][0U]; - __Vtemp1166[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][1U]; - __Vtemp1166[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][2U]; - __Vtemp1166[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+23753,(__Vtemp1166),128); - __Vtemp1167[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1167[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1167[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1167[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+23785,(__Vtemp1167),128); - __Vtemp1168[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1168[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1168[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1168[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->fullArray(c+23817,(__Vtemp1168),128); - __Vtemp1169[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1169[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1169[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1169[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; - vcdp->fullArray(c+23849,(__Vtemp1169),128); - __Vtemp1170[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][0U]; - __Vtemp1170[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][1U]; - __Vtemp1170[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][2U]; - __Vtemp1170[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][3U]; - vcdp->fullArray(c+23881,(__Vtemp1170),128); - vcdp->fullBus(c+23913,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); - vcdp->fullBus(c+23914,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); - vcdp->fullBus(c+23915,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); - vcdp->fullBus(c+23916,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); - vcdp->fullBus(c+23917,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); - vcdp->fullBus(c+23918,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); - vcdp->fullBus(c+23919,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); - vcdp->fullBus(c+23920,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); - vcdp->fullBus(c+23921,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); - vcdp->fullBus(c+23922,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); - vcdp->fullBus(c+23923,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); 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+ vcdp->fullArray(c+12729,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->fullQuad(c+12793,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->fullQuad(c+12809,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->fullBus(c+12825,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+12833,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+12841,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->fullArray(c+12889,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+12969,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+12972,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+12975,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+12978,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+12981,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+12984,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+12987,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+12990,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+12993,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+12996,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+12999,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+13002,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+13005,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+13008,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+13011,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+13014,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+13353,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->fullBus(c+13457,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+13465,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+13473,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+13481,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+13489,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+13497,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+13505,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+13513,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->fullArray(c+13521,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+13524,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+13527,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+13530,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+13617,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+13641,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+13665,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+13673,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+13681,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+13689,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+13697,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+13705,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+13712,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+13719,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+13726,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+13929,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+13985,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+14041,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+14049,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+14057,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+14065,(vlTOPp->VX_cache__DOT__genblk5__BRA__0__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+14073,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14081,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+14089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14097,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+14105,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+14113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+14129,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+14137,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+14145,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->fullBus(c+25609,(((0x18fU >= (0x1ffU - & ((IData)(0x19U) + vcdp->fullBus(c+14153,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (( + ? (0x3ffffffU & (( (0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -11744,37 +6019,37 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+25617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->fullBus(c+14161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->fullBus(c+25625,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+14169,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->fullQuad(c+25633,((VL_ULL(0x3ffffffffff) + vcdp->fullQuad(c+14177,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -11786,19 +6061,19 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->fullBus(c+25649,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+14193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->fullBit(c+25657,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+14201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->fullBit(c+25665,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+14209,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+25673,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+25681,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+14217,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+14225,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -11807,424 +6082,224 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->fullBit(c+25697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->fullBit(c+14241,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->fullBus(c+25705,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBus(c+14249,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->fullBit(c+25713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->fullBit(c+25721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14265,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->fullBus(c+25729,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+25737,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+25745,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1178[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1178[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1178[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1178[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+25753,(__Vtemp1178),128); - vcdp->fullBit(c+25785,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+14273,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+14281,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+14289,(((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp620[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp620[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp620[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp620[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+14297,(__Vtemp620),128); + vcdp->fullBit(c+14329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->fullBit(c+25793,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBit(c+14337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->fullBus(c+25801,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+14345,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); - vcdp->fullQuad(c+25809,((VL_ULL(0x1ffffffffffff) + vcdp->fullQuad(c+14353,((VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->fullBus(c+25825,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->fullBit(c+25833,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBus(c+14369,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+14377,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U)))); - vcdp->fullBit(c+25841,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14385,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vcdp->fullBit(c+25849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14393,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x16U)))); - vcdp->fullBit(c+25857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14401,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U)))); - vcdp->fullBit(c+25865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14409,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)))); - vcdp->fullBit(c+25873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14417,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU)))); - vcdp->fullBit(c+25881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+14425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U)))); - vcdp->fullBit(c+25889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+25897,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+25905,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+25913,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBus(c+25921,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->fullBus(c+25929,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBit(c+14433,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14441,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+14449,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+14457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+14465,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+14473,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))),28); - vcdp->fullBit(c+25937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->fullBus(c+25945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->fullQuad(c+25953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->fullQuad(c+25955,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->fullQuad(c+25957,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->fullQuad(c+25959,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->fullQuad(c+25961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+25963,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+25965,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+25967,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+25969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+25971,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+25973,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+25975,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->fullQuad(c+25977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->fullQuad(c+25979,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->fullQuad(c+25981,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->fullQuad(c+25983,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->fullQuad(c+26209,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->fullQuad(c+26225,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->fullBus(c+26241,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->fullBus(c+26249,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->fullBus(c+26257,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->fullBit(c+26265,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+26273,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); - vcdp->fullArray(c+26281,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); - vcdp->fullArray(c+26286,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); - vcdp->fullArray(c+26291,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); - vcdp->fullArray(c+26296,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); - vcdp->fullArray(c+26301,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); - vcdp->fullArray(c+26306,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); - vcdp->fullArray(c+26311,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); - vcdp->fullArray(c+26316,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); - vcdp->fullArray(c+26321,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); - vcdp->fullArray(c+26326,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); - vcdp->fullArray(c+26331,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); - vcdp->fullArray(c+26336,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); - vcdp->fullArray(c+26341,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); - vcdp->fullArray(c+26346,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); - vcdp->fullArray(c+26351,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); - vcdp->fullArray(c+26356,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); - vcdp->fullArray(c+26921,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); - vcdp->fullArray(c+26961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); - vcdp->fullBus(c+27001,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->fullBus(c+27009,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->fullBus(c+27017,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->fullBit(c+27025,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+27033,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); - vcdp->fullBus(c+27041,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); - vcdp->fullBus(c+27049,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); - vcdp->fullArray(c+27057,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); - vcdp->fullArray(c+27089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); - vcdp->fullBit(c+27121,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+27129,((1U & (~ (IData)((0U + vcdp->fullBit(c+14481,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); + vcdp->fullBus(c+14489,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); + vcdp->fullQuad(c+14497,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),55); + vcdp->fullQuad(c+14499,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),55); + vcdp->fullQuad(c+14501,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),55); + vcdp->fullQuad(c+14503,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),55); + vcdp->fullQuad(c+14505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),55); + vcdp->fullQuad(c+14507,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->fullQuad(c+14509,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->fullQuad(c+14511,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->fullQuad(c+14513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->fullQuad(c+14515,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->fullQuad(c+14517,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->fullQuad(c+14519,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->fullQuad(c+14521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->fullQuad(c+14523,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->fullQuad(c+14525,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->fullQuad(c+14527,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->fullQuad(c+14753,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->fullQuad(c+14769,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->fullBus(c+14785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+14793,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+14801,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+14809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+14817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); + vcdp->fullArray(c+14825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),154); + vcdp->fullArray(c+14830,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),154); + vcdp->fullArray(c+14835,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),154); + vcdp->fullArray(c+14840,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),154); + vcdp->fullArray(c+14845,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),154); + vcdp->fullArray(c+14850,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->fullArray(c+14855,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->fullArray(c+14860,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->fullArray(c+14865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->fullArray(c+14870,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->fullArray(c+14875,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->fullArray(c+14880,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->fullArray(c+14885,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->fullArray(c+14890,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->fullArray(c+14895,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->fullArray(c+14900,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->fullArray(c+15465,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->fullArray(c+15505,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->fullBus(c+15545,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+15553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+15561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+15569,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+15577,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+15585,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+15593,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+15601,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+15633,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+15665,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+15673,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); - vcdp->fullBus(c+27137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); - vcdp->fullArray(c+27145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); - vcdp->fullArray(c+27155,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); - vcdp->fullArray(c+27165,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); - vcdp->fullArray(c+27175,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); - vcdp->fullArray(c+27185,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); - vcdp->fullArray(c+27195,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); - vcdp->fullArray(c+27205,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); - vcdp->fullArray(c+27215,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); - vcdp->fullArray(c+27785,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); - vcdp->fullArray(c+27865,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); - vcdp->fullBus(c+27945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+27953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+27961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+27969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullArray(c+27977,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); - __Vtemp1179[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][0U]; - __Vtemp1179[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][1U]; - __Vtemp1179[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][2U]; - __Vtemp1179[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][3U]; - vcdp->fullArray(c+28041,(__Vtemp1179),128); - __Vtemp1180[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][0U]; - __Vtemp1180[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1180[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1180[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->fullArray(c+28073,(__Vtemp1180),128); - __Vtemp1181[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1181[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1181[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1181[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; - vcdp->fullArray(c+28105,(__Vtemp1181),128); - __Vtemp1182[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][0U]; - __Vtemp1182[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][1U]; - __Vtemp1182[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][2U]; - __Vtemp1182[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][3U]; - vcdp->fullArray(c+28137,(__Vtemp1182),128); - __Vtemp1183[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][0U]; - __Vtemp1183[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][1U]; - __Vtemp1183[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][2U]; - __Vtemp1183[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][3U]; - vcdp->fullArray(c+28169,(__Vtemp1183),128); - __Vtemp1184[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][0U]; - __Vtemp1184[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][1U]; - __Vtemp1184[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][2U]; - __Vtemp1184[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][3U]; - vcdp->fullArray(c+28201,(__Vtemp1184),128); - __Vtemp1185[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][0U]; - __Vtemp1185[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][1U]; - __Vtemp1185[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][2U]; - __Vtemp1185[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][3U]; - vcdp->fullArray(c+28233,(__Vtemp1185),128); - __Vtemp1186[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][0U]; - __Vtemp1186[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][1U]; - __Vtemp1186[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][2U]; - __Vtemp1186[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][3U]; - vcdp->fullArray(c+28265,(__Vtemp1186),128); - __Vtemp1187[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][0U]; - __Vtemp1187[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1187[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1187[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->fullArray(c+28297,(__Vtemp1187),128); - __Vtemp1188[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1188[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1188[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; - __Vtemp1188[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; - vcdp->fullArray(c+28329,(__Vtemp1188),128); - __Vtemp1189[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][0U]; - __Vtemp1189[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][1U]; - __Vtemp1189[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][2U]; - __Vtemp1189[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][3U]; - vcdp->fullArray(c+28361,(__Vtemp1189),128); - __Vtemp1190[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][0U]; - __Vtemp1190[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][1U]; - __Vtemp1190[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][2U]; - __Vtemp1190[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+28393,(__Vtemp1190),128); - __Vtemp1191[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1191[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1191[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1191[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+28425,(__Vtemp1191),128); - __Vtemp1192[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1192[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1192[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1192[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->fullArray(c+28457,(__Vtemp1192),128); - __Vtemp1193[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1193[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1193[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1193[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; - vcdp->fullArray(c+28489,(__Vtemp1193),128); - __Vtemp1194[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][0U]; - __Vtemp1194[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][1U]; - __Vtemp1194[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][2U]; - __Vtemp1194[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][3U]; - vcdp->fullArray(c+28521,(__Vtemp1194),128); - vcdp->fullBus(c+28553,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); - vcdp->fullBus(c+28554,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); - vcdp->fullBus(c+28555,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); - vcdp->fullBus(c+28556,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); - vcdp->fullBus(c+28557,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); - vcdp->fullBus(c+28558,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); - vcdp->fullBus(c+28559,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); - vcdp->fullBus(c+28560,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); - vcdp->fullBus(c+28561,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); - vcdp->fullBus(c+28562,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); - vcdp->fullBus(c+28563,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); - vcdp->fullBus(c+28564,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); - vcdp->fullBus(c+28565,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); - vcdp->fullBus(c+28566,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); - vcdp->fullBus(c+28567,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); - vcdp->fullBus(c+28568,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); - vcdp->fullBus(c+28681,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0U]),16); - vcdp->fullBus(c+28689,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [1U]),16); - vcdp->fullBus(c+28697,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [2U]),16); - vcdp->fullBus(c+28705,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [3U]),16); - vcdp->fullBus(c+28713,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [4U]),16); - vcdp->fullBus(c+28721,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [5U]),16); - vcdp->fullBus(c+28729,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [6U]),16); - vcdp->fullBus(c+28737,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [7U]),16); - vcdp->fullBus(c+28745,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [8U]),16); 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- vcdp->fullBus(c+28809,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); - vcdp->fullBus(c+28817,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); - vcdp->fullBus(c+28825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); - vcdp->fullBus(c+28833,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); - vcdp->fullArray(c+28841,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); - vcdp->fullArray(c+28889,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); - vcdp->fullArray(c+28969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); - vcdp->fullArray(c+28972,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); 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+ vcdp->fullArray(c+16468,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+16471,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+16474,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+16477,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+16480,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+16483,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+16486,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+16825,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->fullBus(c+16929,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+16937,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+16945,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+16953,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+16961,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+16969,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+16977,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+16985,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->fullArray(c+16993,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+16996,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+16999,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+17002,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+17089,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+17113,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+17137,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+17145,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+17153,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+17161,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+17169,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+17177,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+17184,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+17191,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+17198,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+17401,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+17457,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+17513,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+17521,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+17529,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+17537,(vlTOPp->VX_cache__DOT__genblk5__BRA__1__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+17545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+17561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17569,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+17577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+17585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+17601,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+17609,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+17617,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->fullBus(c+30249,(((0x18fU >= (0x1ffU - & ((IData)(0x19U) + vcdp->fullBus(c+17625,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (( + ? (0x3ffffffU & (( (0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -12232,37 +6307,37 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+30257,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->fullBus(c+17633,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->fullBus(c+30265,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+17641,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->fullQuad(c+30273,((VL_ULL(0x3ffffffffff) + vcdp->fullQuad(c+17649,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -12274,19 +6349,19 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->fullBus(c+30289,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+17665,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->fullBit(c+30297,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+17673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->fullBit(c+30305,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+17681,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+30313,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+30321,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+17689,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+17697,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -12295,424 +6370,224 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->fullBit(c+30337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->fullBit(c+17713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->fullBus(c+30345,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBus(c+17721,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->fullBit(c+30353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17729,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->fullBit(c+30361,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17737,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->fullBus(c+30369,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+30377,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+30385,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1202[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1202[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1202[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1202[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+30393,(__Vtemp1202),128); - vcdp->fullBit(c+30425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+17745,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+17753,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+17761,(((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp628[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp628[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp628[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp628[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+17769,(__Vtemp628),128); + vcdp->fullBit(c+17801,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->fullBit(c+30433,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBit(c+17809,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->fullBus(c+30441,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+17817,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); - vcdp->fullQuad(c+30449,((VL_ULL(0x1ffffffffffff) + vcdp->fullQuad(c+17825,((VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->fullBus(c+30465,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->fullBit(c+30473,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBus(c+17841,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+17849,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U)))); - vcdp->fullBit(c+30481,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vcdp->fullBit(c+30489,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17865,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x16U)))); - vcdp->fullBit(c+30497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17873,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U)))); - vcdp->fullBit(c+30505,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17881,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)))); - vcdp->fullBit(c+30513,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17889,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1bU)))); - vcdp->fullBit(c+30521,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+17897,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x19U)))); - vcdp->fullBit(c+30529,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+30537,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+30545,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+30553,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBus(c+30561,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->fullBus(c+30569,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBit(c+17905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+17921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+17929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+17937,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+17945,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))),28); - vcdp->fullBit(c+30577,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->fullBus(c+30585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->fullQuad(c+30593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->fullQuad(c+30595,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->fullQuad(c+30597,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->fullQuad(c+30599,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->fullQuad(c+30601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+30603,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+30605,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+30607,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+30609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+30611,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+30613,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+30615,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->fullQuad(c+30617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->fullQuad(c+30619,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->fullQuad(c+30621,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->fullQuad(c+30623,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->fullQuad(c+30849,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->fullQuad(c+30865,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->fullBus(c+30881,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->fullBus(c+30889,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->fullBus(c+30897,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->fullBit(c+30905,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+30913,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); - vcdp->fullArray(c+30921,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); - vcdp->fullArray(c+30926,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); - vcdp->fullArray(c+30931,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); 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+ vcdp->fullQuad(c+17979,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->fullQuad(c+17981,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->fullQuad(c+17983,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->fullQuad(c+17985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->fullQuad(c+17987,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->fullQuad(c+17989,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->fullQuad(c+17991,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->fullQuad(c+17993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->fullQuad(c+17995,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->fullQuad(c+17997,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->fullQuad(c+17999,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->fullQuad(c+18225,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->fullQuad(c+18241,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->fullBus(c+18257,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+18265,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); 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+ vcdp->fullArray(c+18362,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->fullArray(c+18367,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->fullArray(c+18372,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->fullArray(c+18937,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->fullArray(c+18977,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->fullBus(c+19017,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+19025,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+19033,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); 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- vcdp->fullArray(c+31845,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); - vcdp->fullArray(c+31855,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); - vcdp->fullArray(c+32425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); - vcdp->fullArray(c+32505,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); - vcdp->fullBus(c+32585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+32593,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+32601,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+32609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullArray(c+32617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); - __Vtemp1203[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][0U]; - __Vtemp1203[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][1U]; - __Vtemp1203[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][2U]; - __Vtemp1203[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][3U]; - vcdp->fullArray(c+32681,(__Vtemp1203),128); - __Vtemp1204[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][0U]; - __Vtemp1204[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1204[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1204[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->fullArray(c+32713,(__Vtemp1204),128); - __Vtemp1205[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1205[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1205[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1205[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; 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- __Vtemp1211[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1211[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1211[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->fullArray(c+32937,(__Vtemp1211),128); - __Vtemp1212[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1212[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1212[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; - __Vtemp1212[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; 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- __Vtemp1214[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+33033,(__Vtemp1214),128); - __Vtemp1215[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1215[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1215[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1215[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+33065,(__Vtemp1215),128); - __Vtemp1216[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1216[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1216[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1216[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->fullArray(c+33097,(__Vtemp1216),128); - __Vtemp1217[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1217[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1217[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1217[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; - vcdp->fullArray(c+33129,(__Vtemp1217),128); - __Vtemp1218[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][0U]; - __Vtemp1218[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][1U]; - __Vtemp1218[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][2U]; - __Vtemp1218[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][3U]; - vcdp->fullArray(c+33161,(__Vtemp1218),128); - vcdp->fullBus(c+33193,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); - vcdp->fullBus(c+33194,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); - vcdp->fullBus(c+33195,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); - vcdp->fullBus(c+33196,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); - vcdp->fullBus(c+33197,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); - vcdp->fullBus(c+33198,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); - vcdp->fullBus(c+33199,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); - vcdp->fullBus(c+33200,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); - vcdp->fullBus(c+33201,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); - vcdp->fullBus(c+33202,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); - vcdp->fullBus(c+33203,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); 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- vcdp->fullBus(c+33337,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [2U]),16); - vcdp->fullBus(c+33345,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [3U]),16); - vcdp->fullBus(c+33353,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [4U]),16); - vcdp->fullBus(c+33361,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [5U]),16); - vcdp->fullBus(c+33369,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [6U]),16); - vcdp->fullBus(c+33377,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [7U]),16); - vcdp->fullBus(c+33385,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [8U]),16); - vcdp->fullBus(c+33393,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [9U]),16); - vcdp->fullBus(c+33401,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xaU]),16); - vcdp->fullBus(c+33409,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xbU]),16); - vcdp->fullBus(c+33417,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xcU]),16); - vcdp->fullBus(c+33425,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xdU]),16); - vcdp->fullBus(c+33433,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xeU]),16); - vcdp->fullBus(c+33441,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xfU]),16); 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+ vcdp->fullArray(c+20465,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+20468,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+20471,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+20474,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+20561,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+20585,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+20609,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+20617,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+20625,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+20633,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+20641,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+20649,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+20656,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+20663,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+20670,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+20873,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+20929,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+20985,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+20993,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+21001,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+21009,(vlTOPp->VX_cache__DOT__genblk5__BRA__2__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+21017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+21033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+21049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullQuad(c+21057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); + vcdp->fullBit(c+21073,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBit(c+21081,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+21089,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xdU) | ( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x13U)))),2); - vcdp->fullBus(c+34889,(((0x18fU >= (0x1ffU - & ((IData)(0x19U) + vcdp->fullBus(c+21097,(((0x19fU >= (0x1ffU + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (( + ? (0x3ffffffU & (( (0U == (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) ? 0U : @@ -12720,37 +6595,37 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV ((IData)(1U) + (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U)))] << ((IData)(0x20U) - (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ (0xfU - & (((IData)(0x19U) + & (((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) >> 5U))] >> (0x1fU - & ((IData)(0x19U) + & ((IData)(0x1aU) * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+34897,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + : 0U)),26); + vcdp->fullBus(c+21105,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 2U)))),2); - vcdp->fullBus(c+34905,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+21113,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] >> 0x15U))),32); - vcdp->fullQuad(c+34913,((VL_ULL(0x3ffffffffff) + vcdp->fullQuad(c+21121,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) @@ -12762,19 +6637,19 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) >> 9U))))),42); - vcdp->fullBus(c+34929,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBus(c+21137,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] << 0x1cU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 4U)))),4); - vcdp->fullBit(c+34937,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+21145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] >> 1U)))); - vcdp->fullBit(c+34945,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table + vcdp->fullBit(c+21153,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table [vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+34953,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+34961,((VL_ULL(0x3ffffffffff) + vcdp->fullBus(c+21161,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); + vcdp->fullQuad(c+21169,((VL_ULL(0x3ffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) << 0x39U) | (((QData)((IData)( @@ -12783,2464 +6658,292 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV | ((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) >> 7U))))),42); - vcdp->fullBit(c+34977,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] + vcdp->fullBit(c+21185,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 6U)))); - vcdp->fullBus(c+34985,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBus(c+21193,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x1eU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 2U)))),4); - vcdp->fullBit(c+34993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+21201,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x14U)))); - vcdp->fullBit(c+35001,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+21209,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x13U)))); - vcdp->fullBus(c+35009,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+35017,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+35025,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1226[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1226[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1226[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1226[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+35033,(__Vtemp1226),128); - vcdp->fullBit(c+35065,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+21217,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x17U)))),2); + vcdp->fullBus(c+21225,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + >> 0x17U))),32); + vcdp->fullBus(c+21233,(((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + >> 0x17U))),32); + __Vtemp636[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 0x17U)); + __Vtemp636[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + >> 0x17U)); + __Vtemp636[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] + >> 0x17U)); + __Vtemp636[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] + << 9U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] + >> 0x17U)); + vcdp->fullArray(c+21241,(__Vtemp636),128); + vcdp->fullBit(c+21273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 2U)))); - vcdp->fullBit(c+35073,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBit(c+21281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] >> 1U)))); - vcdp->fullBus(c+35081,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + vcdp->fullBus(c+21289,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] << 0xfU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] >> 0x11U)))),16); - vcdp->fullQuad(c+35089,((VL_ULL(0x1ffffffffffff) + vcdp->fullQuad(c+21297,((VL_ULL(0x1ffffffffffff) & (((QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) << 0x20U) | (QData)((IData)( vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->fullBus(c+35105,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->fullBit(c+35113,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBus(c+21313,((0xfffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] + << 0x1dU) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + >> 3U)))),20); + vcdp->fullBit(c+21321,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x15U)))); - vcdp->fullBit(c+35121,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+21329,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x17U)))); - vcdp->fullBit(c+35129,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+21337,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x16U)))); - vcdp->fullBit(c+35137,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+21345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x18U)))); - vcdp->fullBit(c+35145,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + vcdp->fullBit(c+21353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] >> 0x1aU)))); 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- vcdp->fullBus(c+35201,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->fullBus(c+35209,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] + vcdp->fullBit(c+21377,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBit(c+21393,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+21401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); + vcdp->fullBus(c+21409,(((0x3ffffc0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] + << 3U)) + | (0x3fU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] + << 7U) + | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] + >> 0x19U))))),26); + vcdp->fullBus(c+21417,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] << 0x19U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] >> 7U)))),28); - vcdp->fullBit(c+35217,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->fullBus(c+35225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->fullQuad(c+35233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->fullQuad(c+35235,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->fullQuad(c+35237,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->fullQuad(c+35239,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->fullQuad(c+35241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+35243,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+35245,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+35247,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+35249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+35251,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+35253,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+35255,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->fullQuad(c+35257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->fullQuad(c+35259,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->fullQuad(c+35261,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->fullQuad(c+35263,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->fullQuad(c+35489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->fullQuad(c+35505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->fullBus(c+35521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->fullBus(c+35529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); - vcdp->fullBus(c+35537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); - vcdp->fullBit(c+35545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+35553,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__size_r),5); - vcdp->fullArray(c+35561,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[0]),153); - vcdp->fullArray(c+35566,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[1]),153); - vcdp->fullArray(c+35571,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[2]),153); - vcdp->fullArray(c+35576,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[3]),153); - vcdp->fullArray(c+35581,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); - vcdp->fullArray(c+35586,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); - vcdp->fullArray(c+35591,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); - vcdp->fullArray(c+35596,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); - vcdp->fullArray(c+35601,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); - vcdp->fullArray(c+35606,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); - vcdp->fullArray(c+35611,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); - vcdp->fullArray(c+35616,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); - vcdp->fullArray(c+35621,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); - vcdp->fullArray(c+35626,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); - vcdp->fullArray(c+35631,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); - vcdp->fullArray(c+35636,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); - vcdp->fullArray(c+36201,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); - vcdp->fullArray(c+36241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); - vcdp->fullBus(c+36281,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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+ vcdp->fullQuad(c+21451,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),55); + vcdp->fullQuad(c+21453,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),55); + vcdp->fullQuad(c+21455,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),55); + vcdp->fullQuad(c+21457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),55); + vcdp->fullQuad(c+21459,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),55); + vcdp->fullQuad(c+21461,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),55); + vcdp->fullQuad(c+21463,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),55); + vcdp->fullQuad(c+21465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),55); + vcdp->fullQuad(c+21467,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),55); + vcdp->fullQuad(c+21469,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),55); + vcdp->fullQuad(c+21471,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),55); + vcdp->fullQuad(c+21697,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),55); + vcdp->fullQuad(c+21713,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),55); + vcdp->fullBus(c+21729,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+21737,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); 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+ vcdp->fullArray(c+21794,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),154); + vcdp->fullArray(c+21799,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),154); + vcdp->fullArray(c+21804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),154); + vcdp->fullArray(c+21809,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),154); + vcdp->fullArray(c+21814,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),154); + vcdp->fullArray(c+21819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),154); + vcdp->fullArray(c+21824,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),154); + vcdp->fullArray(c+21829,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),154); + vcdp->fullArray(c+21834,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),154); + vcdp->fullArray(c+21839,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),154); + vcdp->fullArray(c+21844,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),154); + vcdp->fullArray(c+22409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),154); + vcdp->fullArray(c+22449,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),154); + vcdp->fullBus(c+22489,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); + vcdp->fullBus(c+22497,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); + vcdp->fullBus(c+22505,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),4); + vcdp->fullBit(c+22513,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+22521,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids),4); + vcdp->fullBus(c+22529,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_rw),4); + vcdp->fullBus(c+22537,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_byteen),16); + vcdp->fullArray(c+22545,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_addr),120); + vcdp->fullArray(c+22577,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_writedata),128); + vcdp->fullBit(c+22609,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); + vcdp->fullBit(c+22617,((1U & (~ (IData)((0U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_valids))))))); - vcdp->fullBus(c+36417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),4); - vcdp->fullArray(c+36425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); - vcdp->fullArray(c+36435,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); - vcdp->fullArray(c+36445,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); - vcdp->fullArray(c+36455,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); - vcdp->fullArray(c+36465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[4]),314); - vcdp->fullArray(c+36475,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[5]),314); - vcdp->fullArray(c+36485,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[6]),314); - vcdp->fullArray(c+36495,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[7]),314); - vcdp->fullArray(c+37065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); - vcdp->fullArray(c+37145,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); - vcdp->fullBus(c+37225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+37233,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+37241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); 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- __Vtemp1228[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1228[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1228[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->fullArray(c+37353,(__Vtemp1228),128); - __Vtemp1229[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1229[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1229[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1229[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; - vcdp->fullArray(c+37385,(__Vtemp1229),128); - __Vtemp1230[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][0U]; - __Vtemp1230[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][1U]; - __Vtemp1230[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][2U]; - __Vtemp1230[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][3U]; - vcdp->fullArray(c+37417,(__Vtemp1230),128); - __Vtemp1231[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][0U]; - __Vtemp1231[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][1U]; - __Vtemp1231[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][2U]; 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- __Vtemp1235[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1235[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1235[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->fullArray(c+37577,(__Vtemp1235),128); - __Vtemp1236[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1236[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1236[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; - __Vtemp1236[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; - vcdp->fullArray(c+37609,(__Vtemp1236),128); - __Vtemp1237[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][0U]; - __Vtemp1237[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][1U]; - __Vtemp1237[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][2U]; - __Vtemp1237[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][3U]; - vcdp->fullArray(c+37641,(__Vtemp1237),128); - __Vtemp1238[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][0U]; - __Vtemp1238[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][1U]; - __Vtemp1238[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][2U]; - __Vtemp1238[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+37673,(__Vtemp1238),128); - __Vtemp1239[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1239[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1239[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1239[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+37705,(__Vtemp1239),128); - __Vtemp1240[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1240[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1240[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1240[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->fullArray(c+37737,(__Vtemp1240),128); - __Vtemp1241[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1241[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1241[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1241[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; - vcdp->fullArray(c+37769,(__Vtemp1241),128); - __Vtemp1242[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][0U]; - __Vtemp1242[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][1U]; - __Vtemp1242[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][2U]; - __Vtemp1242[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][3U]; - vcdp->fullArray(c+37801,(__Vtemp1242),128); - vcdp->fullBus(c+37833,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); - vcdp->fullBus(c+37834,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); - vcdp->fullBus(c+37835,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); - vcdp->fullBus(c+37836,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); - vcdp->fullBus(c+37837,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); - vcdp->fullBus(c+37838,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); - vcdp->fullBus(c+37839,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); - vcdp->fullBus(c+37840,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); - vcdp->fullBus(c+37841,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); - vcdp->fullBus(c+37842,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); - vcdp->fullBus(c+37843,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); - vcdp->fullBus(c+37844,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); - vcdp->fullBus(c+37845,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); - vcdp->fullBus(c+37846,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); - vcdp->fullBus(c+37847,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); - vcdp->fullBus(c+37848,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); - vcdp->fullBus(c+37961,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0U]),16); - vcdp->fullBus(c+37969,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [1U]),16); - vcdp->fullBus(c+37977,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [2U]),16); - vcdp->fullBus(c+37985,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [3U]),16); - vcdp->fullBus(c+37993,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [4U]),16); - vcdp->fullBus(c+38001,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [5U]),16); - vcdp->fullBus(c+38009,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [6U]),16); - vcdp->fullBus(c+38017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [7U]),16); - vcdp->fullBus(c+38025,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [8U]),16); - vcdp->fullBus(c+38033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [9U]),16); - vcdp->fullBus(c+38041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xaU]),16); - vcdp->fullBus(c+38049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xbU]),16); - vcdp->fullBus(c+38057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xcU]),16); - vcdp->fullBus(c+38065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xdU]),16); - vcdp->fullBus(c+38073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xeU]),16); - vcdp->fullBus(c+38081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xfU]),16); - vcdp->fullBus(c+38089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); - vcdp->fullBus(c+38097,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); - vcdp->fullBus(c+38105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); - vcdp->fullBus(c+38113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); - vcdp->fullArray(c+38121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); - vcdp->fullArray(c+38169,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); - vcdp->fullArray(c+38249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); - vcdp->fullArray(c+38252,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); 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- vcdp->fullBus(c+38745,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); - vcdp->fullBus(c+38753,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); - vcdp->fullBus(c+38761,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); - vcdp->fullBus(c+38769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); - vcdp->fullBus(c+38777,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); - vcdp->fullBit(c+38785,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBus(c+38793,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); - vcdp->fullArray(c+38801,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); - vcdp->fullArray(c+38804,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); - vcdp->fullArray(c+38807,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); - vcdp->fullArray(c+38810,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); - vcdp->fullArray(c+38813,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); - vcdp->fullArray(c+38816,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); - vcdp->fullArray(c+38819,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); - vcdp->fullArray(c+38822,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); - vcdp->fullArray(c+38993,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->fullArray(c+39017,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->fullBus(c+39041,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+39049,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+39057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+39065,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+39073,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->fullArray(c+39081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->fullArray(c+39088,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->fullArray(c+39095,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->fullArray(c+39102,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->fullArray(c+39305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->fullArray(c+39361,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->fullBus(c+39417,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->fullBus(c+39425,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->fullBus(c+39433,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->fullBit(c+39441,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBit(c+39449,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+39457,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+39465,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+39473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+39481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullQuad(c+39489,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->fullBit(c+39505,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBit(c+39513,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBus(c+39521,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))),2); - vcdp->fullBus(c+39529,(((0x18fU >= (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (( - (0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+39537,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->fullBus(c+39545,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->fullQuad(c+39553,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->fullBus(c+39569,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->fullBit(c+39577,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->fullBit(c+39585,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+39593,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+39601,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->fullBit(c+39617,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->fullBus(c+39625,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->fullBit(c+39633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->fullBit(c+39641,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); - vcdp->fullBus(c+39649,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+39657,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+39665,(((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1250[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1250[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1250[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1250[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+39673,(__Vtemp1250),128); - vcdp->fullBit(c+39705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->fullBit(c+39713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->fullBus(c+39721,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); 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- vcdp->fullBus(c+39849,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))),28); - vcdp->fullBit(c+39857,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->fullBus(c+39865,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->fullQuad(c+39873,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->fullQuad(c+39875,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->fullQuad(c+39877,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->fullQuad(c+39879,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->fullQuad(c+39881,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+39883,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+39885,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+39887,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+39889,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+39891,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+39893,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+39895,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->fullQuad(c+39897,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->fullQuad(c+39899,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->fullQuad(c+39901,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->fullQuad(c+39903,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->fullQuad(c+40129,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->fullQuad(c+40145,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->fullBus(c+40161,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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- vcdp->fullArray(c+40221,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[4]),153); - vcdp->fullArray(c+40226,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[5]),153); - vcdp->fullArray(c+40231,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[6]),153); - vcdp->fullArray(c+40236,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[7]),153); - vcdp->fullArray(c+40241,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[8]),153); - vcdp->fullArray(c+40246,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[9]),153); - vcdp->fullArray(c+40251,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[10]),153); - vcdp->fullArray(c+40256,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[11]),153); - vcdp->fullArray(c+40261,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[12]),153); - vcdp->fullArray(c+40266,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[13]),153); - vcdp->fullArray(c+40271,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[14]),153); - vcdp->fullArray(c+40276,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__data[15]),153); - vcdp->fullArray(c+40841,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),153); - vcdp->fullArray(c+40881,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),153); - vcdp->fullBus(c+40921,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); - vcdp->fullBus(c+40929,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),4); 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- vcdp->fullArray(c+41961,(__Vtemp1251),128); - __Vtemp1252[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][0U]; - __Vtemp1252[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1252[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1252[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->fullArray(c+41993,(__Vtemp1252),128); - __Vtemp1253[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1253[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1253[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1253[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; - vcdp->fullArray(c+42025,(__Vtemp1253),128); - __Vtemp1254[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][0U]; - __Vtemp1254[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][1U]; - __Vtemp1254[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][2U]; - __Vtemp1254[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][3U]; - vcdp->fullArray(c+42057,(__Vtemp1254),128); - __Vtemp1255[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][0U]; - __Vtemp1255[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][1U]; - __Vtemp1255[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][2U]; - __Vtemp1255[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][3U]; - vcdp->fullArray(c+42089,(__Vtemp1255),128); - __Vtemp1256[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][0U]; - __Vtemp1256[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][1U]; - __Vtemp1256[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][2U]; - __Vtemp1256[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][3U]; - vcdp->fullArray(c+42121,(__Vtemp1256),128); - __Vtemp1257[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][0U]; - __Vtemp1257[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][1U]; - __Vtemp1257[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][2U]; - __Vtemp1257[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][3U]; - vcdp->fullArray(c+42153,(__Vtemp1257),128); - __Vtemp1258[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][0U]; - __Vtemp1258[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][1U]; - __Vtemp1258[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][2U]; - __Vtemp1258[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][3U]; - vcdp->fullArray(c+42185,(__Vtemp1258),128); - __Vtemp1259[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][0U]; - __Vtemp1259[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1259[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1259[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->fullArray(c+42217,(__Vtemp1259),128); - __Vtemp1260[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1260[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1260[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; - __Vtemp1260[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; - vcdp->fullArray(c+42249,(__Vtemp1260),128); - __Vtemp1261[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][0U]; - __Vtemp1261[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][1U]; - __Vtemp1261[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][2U]; - __Vtemp1261[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][3U]; - vcdp->fullArray(c+42281,(__Vtemp1261),128); - __Vtemp1262[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][0U]; - __Vtemp1262[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][1U]; - __Vtemp1262[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][2U]; - __Vtemp1262[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+42313,(__Vtemp1262),128); - __Vtemp1263[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1263[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1263[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1263[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+42345,(__Vtemp1263),128); - __Vtemp1264[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1264[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1264[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1264[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->fullArray(c+42377,(__Vtemp1264),128); - __Vtemp1265[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1265[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1265[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1265[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; - vcdp->fullArray(c+42409,(__Vtemp1265),128); - __Vtemp1266[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][0U]; - __Vtemp1266[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][1U]; - __Vtemp1266[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][2U]; - __Vtemp1266[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][3U]; - vcdp->fullArray(c+42441,(__Vtemp1266),128); - vcdp->fullBus(c+42473,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); - vcdp->fullBus(c+42474,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); - vcdp->fullBus(c+42475,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); - vcdp->fullBus(c+42476,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[3]),21); - vcdp->fullBus(c+42477,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[4]),21); - vcdp->fullBus(c+42478,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[5]),21); - vcdp->fullBus(c+42479,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[6]),21); - vcdp->fullBus(c+42480,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[7]),21); - vcdp->fullBus(c+42481,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[8]),21); - vcdp->fullBus(c+42482,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[9]),21); - vcdp->fullBus(c+42483,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); - vcdp->fullBus(c+42484,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); - vcdp->fullBus(c+42485,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); - vcdp->fullBus(c+42486,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); - vcdp->fullBus(c+42487,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); - vcdp->fullBus(c+42488,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); - vcdp->fullBus(c+42601,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0U]),16); - vcdp->fullBus(c+42609,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [1U]),16); - vcdp->fullBus(c+42617,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [2U]),16); - vcdp->fullBus(c+42625,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [3U]),16); - vcdp->fullBus(c+42633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [4U]),16); - vcdp->fullBus(c+42641,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [5U]),16); - vcdp->fullBus(c+42649,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [6U]),16); - vcdp->fullBus(c+42657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [7U]),16); - vcdp->fullBus(c+42665,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [8U]),16); - vcdp->fullBus(c+42673,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [9U]),16); - vcdp->fullBus(c+42681,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xaU]),16); - vcdp->fullBus(c+42689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xbU]),16); - vcdp->fullBus(c+42697,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xcU]),16); - vcdp->fullBus(c+42705,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xdU]),16); - vcdp->fullBus(c+42713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xeU]),16); - vcdp->fullBus(c+42721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xfU]),16); - vcdp->fullBus(c+42729,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); - vcdp->fullBus(c+42737,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); - vcdp->fullBus(c+42745,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); - vcdp->fullBus(c+42753,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); - vcdp->fullArray(c+42761,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); - vcdp->fullArray(c+42809,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); - vcdp->fullArray(c+42889,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); - vcdp->fullArray(c+42892,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); - vcdp->fullArray(c+42895,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); - vcdp->fullArray(c+42898,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); - vcdp->fullArray(c+42901,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); - vcdp->fullArray(c+42904,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); - vcdp->fullArray(c+42907,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); - vcdp->fullArray(c+42910,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); - vcdp->fullArray(c+42913,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); - vcdp->fullArray(c+42916,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); - vcdp->fullArray(c+42919,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); - vcdp->fullArray(c+42922,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); - vcdp->fullArray(c+42925,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); - vcdp->fullArray(c+42928,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); - vcdp->fullArray(c+42931,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); - vcdp->fullArray(c+42934,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); - vcdp->fullArray(c+43273,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); - vcdp->fullBus(c+43377,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); - vcdp->fullBus(c+43385,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); - vcdp->fullBus(c+43393,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); - vcdp->fullBus(c+43401,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); - vcdp->fullBus(c+43409,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); - vcdp->fullBus(c+43417,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); - vcdp->fullBit(c+43425,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBus(c+43433,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); - vcdp->fullArray(c+43441,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); - vcdp->fullArray(c+43444,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); - vcdp->fullArray(c+43447,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); - vcdp->fullArray(c+43450,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); - vcdp->fullArray(c+43453,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); - vcdp->fullArray(c+43456,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); - vcdp->fullArray(c+43459,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); - vcdp->fullArray(c+43462,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); - vcdp->fullArray(c+43633,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->fullArray(c+43657,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->fullBus(c+43681,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+43689,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+43697,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+43705,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+43713,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->fullArray(c+43721,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->fullArray(c+43728,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->fullArray(c+43735,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->fullArray(c+43742,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->fullArray(c+43945,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->fullArray(c+44001,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->fullBus(c+44057,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->fullBus(c+44065,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->fullBus(c+44073,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->fullBit(c+44081,(vlTOPp->VX_cache__DOT__genblk5__BRA__4__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBit(c+44089,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+44097,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+44105,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+44113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+44121,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullQuad(c+44129,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->fullBit(c+44145,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBit(c+44153,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBus(c+44161,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))),2); - vcdp->fullBus(c+44169,(((0x18fU >= (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (( - (0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+44177,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->fullBus(c+44185,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->fullQuad(c+44193,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->fullBus(c+44209,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->fullBit(c+44217,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->fullBit(c+44225,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+44233,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+44241,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->fullBit(c+44257,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->fullBus(c+44265,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->fullBit(c+44273,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->fullBit(c+44281,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); - vcdp->fullBus(c+44289,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+44297,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+44305,(((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1274[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1274[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1274[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1274[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+44313,(__Vtemp1274),128); - vcdp->fullBit(c+44345,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->fullBit(c+44353,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->fullBus(c+44361,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); 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- vcdp->fullBit(c+44425,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)))); - vcdp->fullBit(c+44433,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)))); - vcdp->fullBit(c+44441,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U)))); - vcdp->fullBit(c+44449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+44457,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+44465,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+44473,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBus(c+44481,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); 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- vcdp->fullQuad(c+44521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+44523,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+44525,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+44527,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+44529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+44531,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+44533,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+44535,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->fullQuad(c+44537,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->fullQuad(c+44539,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->fullQuad(c+44541,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->fullQuad(c+44543,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->fullQuad(c+44769,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->fullQuad(c+44785,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->fullBus(c+44801,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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- vcdp->fullBus(c+46521,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+46529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullArray(c+46537,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); - __Vtemp1275[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][0U]; - __Vtemp1275[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][1U]; - __Vtemp1275[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][2U]; - __Vtemp1275[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][3U]; - vcdp->fullArray(c+46601,(__Vtemp1275),128); - __Vtemp1276[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][0U]; - __Vtemp1276[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1276[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1276[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->fullArray(c+46633,(__Vtemp1276),128); - __Vtemp1277[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1277[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1277[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1277[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; - vcdp->fullArray(c+46665,(__Vtemp1277),128); - __Vtemp1278[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][0U]; - __Vtemp1278[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][1U]; - __Vtemp1278[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][2U]; - __Vtemp1278[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][3U]; - vcdp->fullArray(c+46697,(__Vtemp1278),128); - __Vtemp1279[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][0U]; - __Vtemp1279[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][1U]; - __Vtemp1279[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][2U]; - __Vtemp1279[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][3U]; - vcdp->fullArray(c+46729,(__Vtemp1279),128); - __Vtemp1280[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][0U]; - __Vtemp1280[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][1U]; - __Vtemp1280[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][2U]; - __Vtemp1280[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][3U]; - vcdp->fullArray(c+46761,(__Vtemp1280),128); - __Vtemp1281[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][0U]; - __Vtemp1281[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][1U]; - __Vtemp1281[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][2U]; - __Vtemp1281[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][3U]; - vcdp->fullArray(c+46793,(__Vtemp1281),128); - __Vtemp1282[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][0U]; - __Vtemp1282[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][1U]; - __Vtemp1282[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][2U]; - __Vtemp1282[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][3U]; - vcdp->fullArray(c+46825,(__Vtemp1282),128); - __Vtemp1283[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][0U]; - __Vtemp1283[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1283[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1283[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->fullArray(c+46857,(__Vtemp1283),128); - __Vtemp1284[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1284[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1284[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; - __Vtemp1284[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; - vcdp->fullArray(c+46889,(__Vtemp1284),128); - __Vtemp1285[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][0U]; - __Vtemp1285[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][1U]; - __Vtemp1285[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][2U]; - __Vtemp1285[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][3U]; - vcdp->fullArray(c+46921,(__Vtemp1285),128); - __Vtemp1286[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][0U]; - __Vtemp1286[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][1U]; - __Vtemp1286[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][2U]; - __Vtemp1286[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+46953,(__Vtemp1286),128); - __Vtemp1287[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1287[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1287[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1287[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+46985,(__Vtemp1287),128); - __Vtemp1288[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1288[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1288[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1288[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->fullArray(c+47017,(__Vtemp1288),128); - __Vtemp1289[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1289[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1289[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1289[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; - vcdp->fullArray(c+47049,(__Vtemp1289),128); - __Vtemp1290[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][0U]; - __Vtemp1290[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][1U]; - __Vtemp1290[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][2U]; - __Vtemp1290[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xfU][3U]; - vcdp->fullArray(c+47081,(__Vtemp1290),128); - vcdp->fullBus(c+47113,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[0]),21); - vcdp->fullBus(c+47114,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[1]),21); - vcdp->fullBus(c+47115,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[2]),21); 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- vcdp->fullBus(c+47123,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[10]),21); - vcdp->fullBus(c+47124,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[11]),21); - vcdp->fullBus(c+47125,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[12]),21); - vcdp->fullBus(c+47126,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[13]),21); - vcdp->fullBus(c+47127,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[14]),21); - vcdp->fullBus(c+47128,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__tag[15]),21); - vcdp->fullBus(c+47241,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0U]),16); - vcdp->fullBus(c+47249,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [1U]),16); - vcdp->fullBus(c+47257,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [2U]),16); - vcdp->fullBus(c+47265,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [3U]),16); - vcdp->fullBus(c+47273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [4U]),16); - vcdp->fullBus(c+47281,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [5U]),16); - vcdp->fullBus(c+47289,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [6U]),16); - vcdp->fullBus(c+47297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [7U]),16); - vcdp->fullBus(c+47305,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [8U]),16); - vcdp->fullBus(c+47313,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [9U]),16); - vcdp->fullBus(c+47321,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xaU]),16); - vcdp->fullBus(c+47329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xbU]),16); - vcdp->fullBus(c+47337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xcU]),16); - vcdp->fullBus(c+47345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xdU]),16); - vcdp->fullBus(c+47353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xeU]),16); - vcdp->fullBus(c+47361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirtyb - [0xfU]),16); - vcdp->fullBus(c+47369,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),16); - vcdp->fullBus(c+47377,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),16); - vcdp->fullBus(c+47385,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); - vcdp->fullBus(c+47393,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); - vcdp->fullArray(c+47401,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),167); - vcdp->fullArray(c+47449,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); - vcdp->fullArray(c+47529,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); - vcdp->fullArray(c+47532,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); - vcdp->fullArray(c+47535,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); - vcdp->fullArray(c+47538,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); - vcdp->fullArray(c+47541,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); - vcdp->fullArray(c+47544,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); - vcdp->fullArray(c+47547,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); - vcdp->fullArray(c+47550,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); - vcdp->fullArray(c+47553,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); - vcdp->fullArray(c+47556,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); - vcdp->fullArray(c+47559,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); - vcdp->fullArray(c+47562,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); - vcdp->fullArray(c+47565,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); - vcdp->fullArray(c+47568,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); - vcdp->fullArray(c+47571,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); - vcdp->fullArray(c+47574,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); - vcdp->fullArray(c+47913,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),400); - vcdp->fullBus(c+48017,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); - vcdp->fullBus(c+48025,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); - vcdp->fullBus(c+48033,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); - vcdp->fullBus(c+48041,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); - vcdp->fullBus(c+48049,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); - vcdp->fullBus(c+48057,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); - vcdp->fullBit(c+48065,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBus(c+48073,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),4); - vcdp->fullArray(c+48081,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); - vcdp->fullArray(c+48084,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); - vcdp->fullArray(c+48087,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); - vcdp->fullArray(c+48090,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); - vcdp->fullArray(c+48093,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[4]),76); - vcdp->fullArray(c+48096,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[5]),76); - vcdp->fullArray(c+48099,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[6]),76); - vcdp->fullArray(c+48102,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[7]),76); - vcdp->fullArray(c+48273,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->fullArray(c+48297,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->fullBus(c+48321,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+48329,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+48337,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+48345,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+48353,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->fullArray(c+48361,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->fullArray(c+48368,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->fullArray(c+48375,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->fullArray(c+48382,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->fullArray(c+48585,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->fullArray(c+48641,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->fullBus(c+48697,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->fullBus(c+48705,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->fullBus(c+48713,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->fullBit(c+48721,(vlTOPp->VX_cache__DOT__genblk5__BRA__5__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBit(c+48729,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+48737,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+48745,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+48753,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dfp_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+48761,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullQuad(c+48769,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__use_per_tag),42); - vcdp->fullBit(c+48785,((0x10U == (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBit(c+48793,((0xbU < (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); - vcdp->fullBus(c+48801,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xdU) | ( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x13U)))),2); - vcdp->fullBus(c+48809,(((0x18fU >= (0x1ffU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? (0x1ffffffU & (( - (0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+48817,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->fullBus(c+48825,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->fullQuad(c+48833,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->fullBus(c+48849,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->fullBit(c+48857,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->fullBit(c+48865,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+48873,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+48881,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->fullBit(c+48897,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->fullBus(c+48905,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->fullBit(c+48913,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->fullBit(c+48921,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); - vcdp->fullBus(c+48929,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+48937,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+48945,(((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1298[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1298[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1298[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1298[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+48953,(__Vtemp1298),128); - vcdp->fullBit(c+48985,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->fullBit(c+48993,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->fullBus(c+49001,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); 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- vcdp->fullBus(c+49129,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))),28); - vcdp->fullBit(c+49137,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->fullBus(c+49145,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->fullQuad(c+49153,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->fullQuad(c+49155,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->fullQuad(c+49157,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->fullQuad(c+49159,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->fullQuad(c+49161,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+49163,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+49165,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+49167,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+49169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+49171,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+49173,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+49175,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); 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- vcdp->fullBus(c+51161,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+51169,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullArray(c+51177,(vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); - __Vtemp1299[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][0U]; - __Vtemp1299[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][1U]; - __Vtemp1299[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][2U]; - __Vtemp1299[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][3U]; 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- __Vtemp1301[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; - vcdp->fullArray(c+51305,(__Vtemp1301),128); - __Vtemp1302[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][0U]; - __Vtemp1302[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][1U]; - __Vtemp1302[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][2U]; - __Vtemp1302[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][3U]; - vcdp->fullArray(c+51337,(__Vtemp1302),128); - __Vtemp1303[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][0U]; - __Vtemp1303[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][1U]; - __Vtemp1303[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][2U]; - __Vtemp1303[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][3U]; - vcdp->fullArray(c+51369,(__Vtemp1303),128); - __Vtemp1304[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][0U]; - __Vtemp1304[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][1U]; - __Vtemp1304[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][2U]; - __Vtemp1304[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][3U]; - vcdp->fullArray(c+51401,(__Vtemp1304),128); - __Vtemp1305[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][0U]; - __Vtemp1305[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][1U]; - __Vtemp1305[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][2U]; - __Vtemp1305[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][3U]; - vcdp->fullArray(c+51433,(__Vtemp1305),128); - __Vtemp1306[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][0U]; - __Vtemp1306[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][1U]; - __Vtemp1306[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][2U]; - __Vtemp1306[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][3U]; 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- __Vtemp1308[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][3U]; - vcdp->fullArray(c+51529,(__Vtemp1308),128); - __Vtemp1309[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][0U]; - __Vtemp1309[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][1U]; - __Vtemp1309[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][2U]; - __Vtemp1309[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xaU][3U]; - vcdp->fullArray(c+51561,(__Vtemp1309),128); - __Vtemp1310[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][0U]; - __Vtemp1310[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][1U]; - __Vtemp1310[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][2U]; - __Vtemp1310[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+51593,(__Vtemp1310),128); - __Vtemp1311[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1311[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1311[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1311[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+51625,(__Vtemp1311),128); - __Vtemp1312[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; - __Vtemp1312[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][1U]; - __Vtemp1312[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][2U]; - __Vtemp1312[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][3U]; - vcdp->fullArray(c+51657,(__Vtemp1312),128); - __Vtemp1313[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][0U]; - __Vtemp1313[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][1U]; - __Vtemp1313[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][2U]; - __Vtemp1313[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__6__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xeU][3U]; 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(0x1ffffffU & (( - (0U - == - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))) - ? 0U - : - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - ((IData)(1U) - + - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table[ - (0xfU - & (((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)) - >> 5U))] - >> - (0x1fU - & ((IData)(0x19U) - * (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr)))))) - : 0U)),25); - vcdp->fullBus(c+53457,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1eU) | - (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 2U)))),2); - vcdp->fullBus(c+53465,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U] - << 0xbU) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - >> 0x15U))),32); - vcdp->fullQuad(c+53473,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][2U])) - << 0x37U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U])) - << 0x17U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U])) - >> 9U))))),42); - vcdp->fullBus(c+53489,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][1U] - << 0x1cU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 4U)))),4); - vcdp->fullBit(c+53497,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U] - >> 1U)))); - vcdp->fullBit(c+53505,((1U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table - [vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr][0U]))); - vcdp->fullBus(c+53513,((3U & vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])),2); - vcdp->fullQuad(c+53521,((VL_ULL(0x3ffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U])) - << 0x39U) | (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x19U) - | ((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U])) - >> 7U))))),42); - vcdp->fullBit(c+53537,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 6U)))); - vcdp->fullBus(c+53545,((0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x1eU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 2U)))),4); - vcdp->fullBit(c+53553,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x14U)))); - vcdp->fullBit(c+53561,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x13U)))); - vcdp->fullBus(c+53569,((3U & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x18U)))),2); - vcdp->fullBus(c+53577,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - >> 0x18U))),32); - vcdp->fullBus(c+53585,(((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[7U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - >> 0x18U))),32); - __Vtemp1322[0U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 0x18U)); - __Vtemp1322[1U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - >> 0x18U)); - __Vtemp1322[2U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[4U] - >> 0x18U)); - __Vtemp1322[3U] = ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[6U] - << 8U) | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[5U] - >> 0x18U)); - vcdp->fullArray(c+53593,(__Vtemp1322),128); - vcdp->fullBit(c+53625,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 2U)))); - vcdp->fullBit(c+53633,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 1U)))); - vcdp->fullBus(c+53641,((0xffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 0xfU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - >> 0x11U)))),16); - vcdp->fullQuad(c+53649,((VL_ULL(0x1ffffffffffff) - & (((QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U])) - << 0x20U) | (QData)((IData)( - vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U]))))),49); - vcdp->fullBus(c+53665,((0x1fffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[3U] - << 0x1dU) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - >> 3U)))),21); - vcdp->fullBit(c+53673,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x15U)))); - vcdp->fullBit(c+53681,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x17U)))); - vcdp->fullBit(c+53689,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x16U)))); - vcdp->fullBit(c+53697,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x18U)))); - vcdp->fullBit(c+53705,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1aU)))); - vcdp->fullBit(c+53713,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x1bU)))); - vcdp->fullBit(c+53721,((1U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - >> 0x19U)))); - vcdp->fullBit(c+53729,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+53737,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBit(c+53745,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__empty_r)); - vcdp->fullBit(c+53753,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__full_r)); - vcdp->fullBus(c+53761,(((0x1fffff0U & (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[2U] - << 1U)) - | (0xfU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[9U] - << 6U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[8U] - >> 0x1aU))))),25); - vcdp->fullBus(c+53769,((0xfffffffU & ((vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[1U] - << 0x19U) - | (vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__st_1e_2__DOT__value[0U] - >> 7U)))),28); - vcdp->fullBit(c+53777,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwbq_dual_valid_sel)); - vcdp->fullBus(c+53785,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__size_r),5); - vcdp->fullQuad(c+53793,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[0]),54); - vcdp->fullQuad(c+53795,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[1]),54); - vcdp->fullQuad(c+53797,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[2]),54); - vcdp->fullQuad(c+53799,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[3]),54); - vcdp->fullQuad(c+53801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[4]),54); - vcdp->fullQuad(c+53803,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[5]),54); - vcdp->fullQuad(c+53805,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[6]),54); - vcdp->fullQuad(c+53807,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[7]),54); - vcdp->fullQuad(c+53809,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[8]),54); - vcdp->fullQuad(c+53811,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[9]),54); - vcdp->fullQuad(c+53813,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[10]),54); - vcdp->fullQuad(c+53815,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[11]),54); - vcdp->fullQuad(c+53817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[12]),54); - vcdp->fullQuad(c+53819,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[13]),54); - vcdp->fullQuad(c+53821,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[14]),54); - vcdp->fullQuad(c+53823,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__data[15]),54); - vcdp->fullQuad(c+54049,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),54); - vcdp->fullQuad(c+54065,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),54); - vcdp->fullBus(c+54081,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__snp_req_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),4); 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- vcdp->fullBus(c+55801,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+55809,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullArray(c+55817,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__s0_1_c0__DOT__value),242); - __Vtemp1323[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][0U]; - __Vtemp1323[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][1U]; - __Vtemp1323[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][2U]; - __Vtemp1323[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0U][3U]; - vcdp->fullArray(c+55881,(__Vtemp1323),128); - __Vtemp1324[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][0U]; - __Vtemp1324[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][1U]; - __Vtemp1324[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][2U]; - __Vtemp1324[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [1U][3U]; - vcdp->fullArray(c+55913,(__Vtemp1324),128); - __Vtemp1325[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][0U]; - __Vtemp1325[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][1U]; - __Vtemp1325[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][2U]; - __Vtemp1325[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [2U][3U]; - vcdp->fullArray(c+55945,(__Vtemp1325),128); - __Vtemp1326[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][0U]; - __Vtemp1326[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][1U]; - __Vtemp1326[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][2U]; - __Vtemp1326[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [3U][3U]; - vcdp->fullArray(c+55977,(__Vtemp1326),128); - __Vtemp1327[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][0U]; - __Vtemp1327[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][1U]; - __Vtemp1327[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][2U]; - __Vtemp1327[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [4U][3U]; - vcdp->fullArray(c+56009,(__Vtemp1327),128); - __Vtemp1328[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][0U]; - __Vtemp1328[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][1U]; - __Vtemp1328[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][2U]; - __Vtemp1328[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [5U][3U]; - vcdp->fullArray(c+56041,(__Vtemp1328),128); - __Vtemp1329[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][0U]; - __Vtemp1329[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][1U]; - __Vtemp1329[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][2U]; - __Vtemp1329[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [6U][3U]; - vcdp->fullArray(c+56073,(__Vtemp1329),128); - __Vtemp1330[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][0U]; - __Vtemp1330[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][1U]; - __Vtemp1330[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][2U]; - __Vtemp1330[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [7U][3U]; - vcdp->fullArray(c+56105,(__Vtemp1330),128); - __Vtemp1331[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][0U]; - __Vtemp1331[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][1U]; - __Vtemp1331[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][2U]; - __Vtemp1331[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [8U][3U]; - vcdp->fullArray(c+56137,(__Vtemp1331),128); - __Vtemp1332[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][0U]; - __Vtemp1332[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][1U]; - __Vtemp1332[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [9U][2U]; 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- __Vtemp1334[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][2U]; - __Vtemp1334[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xbU][3U]; - vcdp->fullArray(c+56233,(__Vtemp1334),128); - __Vtemp1335[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][0U]; - __Vtemp1335[1U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][1U]; - __Vtemp1335[2U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][2U]; - __Vtemp1335[3U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xcU][3U]; - vcdp->fullArray(c+56265,(__Vtemp1335),128); - __Vtemp1336[0U] = vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__data - [0xdU][0U]; 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- vcdp->fullArray(c+57553,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); - vcdp->fullArray(c+57577,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); - vcdp->fullBus(c+57601,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),3); - vcdp->fullBus(c+57609,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),3); - vcdp->fullBus(c+57617,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),3); - vcdp->fullBit(c+57625,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBus(c+57633,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); - vcdp->fullArray(c+57641,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),199); - vcdp->fullArray(c+57648,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),199); - vcdp->fullArray(c+57655,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),199); - vcdp->fullArray(c+57662,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),199); - vcdp->fullArray(c+57865,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),199); - vcdp->fullArray(c+57921,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),199); - vcdp->fullBus(c+57977,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); - vcdp->fullBus(c+57985,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); - vcdp->fullBus(c+57993,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); - vcdp->fullBit(c+58001,(vlTOPp->VX_cache__DOT__genblk5__BRA__7__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); - vcdp->fullBit(c+58009,(vlTOPp->clk)); - vcdp->fullBit(c+58017,(vlTOPp->reset)); - vcdp->fullBus(c+58025,(vlTOPp->core_req_valid),4); - vcdp->fullBus(c+58033,(vlTOPp->core_req_rw),4); - vcdp->fullBus(c+58041,(vlTOPp->core_req_byteen),16); - vcdp->fullArray(c+58049,(vlTOPp->core_req_addr),120); - vcdp->fullArray(c+58081,(vlTOPp->core_req_data),128); - vcdp->fullQuad(c+58113,(vlTOPp->core_req_tag),42); - vcdp->fullBit(c+58129,(vlTOPp->core_req_ready)); - vcdp->fullBus(c+58137,(vlTOPp->core_rsp_valid),4); - vcdp->fullArray(c+58145,(vlTOPp->core_rsp_data),128); - vcdp->fullQuad(c+58177,(vlTOPp->core_rsp_tag),42); - vcdp->fullBit(c+58193,(vlTOPp->core_rsp_ready)); - vcdp->fullBit(c+58201,(vlTOPp->dram_req_valid)); - vcdp->fullBit(c+58209,(vlTOPp->dram_req_rw)); - vcdp->fullBus(c+58217,(vlTOPp->dram_req_byteen),16); - vcdp->fullBus(c+58225,(vlTOPp->dram_req_addr),28); - vcdp->fullArray(c+58233,(vlTOPp->dram_req_data),128); - vcdp->fullBus(c+58265,(vlTOPp->dram_req_tag),28); - vcdp->fullBit(c+58273,(vlTOPp->dram_req_ready)); - vcdp->fullBit(c+58281,(vlTOPp->dram_rsp_valid)); - vcdp->fullArray(c+58289,(vlTOPp->dram_rsp_data),128); - vcdp->fullBus(c+58321,(vlTOPp->dram_rsp_tag),28); - vcdp->fullBit(c+58329,(vlTOPp->dram_rsp_ready)); - vcdp->fullBit(c+58337,(vlTOPp->snp_req_valid)); - vcdp->fullBus(c+58345,(vlTOPp->snp_req_addr),28); - vcdp->fullBit(c+58353,(vlTOPp->snp_req_invalidate)); - vcdp->fullBus(c+58361,(vlTOPp->snp_req_tag),28); - vcdp->fullBit(c+58369,(vlTOPp->snp_req_ready)); - vcdp->fullBit(c+58377,(vlTOPp->snp_rsp_valid)); - vcdp->fullBus(c+58385,(vlTOPp->snp_rsp_tag),28); - vcdp->fullBit(c+58393,(vlTOPp->snp_rsp_ready)); - vcdp->fullBus(c+58401,(vlTOPp->snp_fwdout_valid),2); - vcdp->fullQuad(c+58409,(vlTOPp->snp_fwdout_addr),56); - vcdp->fullBus(c+58425,(vlTOPp->snp_fwdout_invalidate),2); - vcdp->fullBus(c+58433,(vlTOPp->snp_fwdout_tag),2); - vcdp->fullBus(c+58441,(vlTOPp->snp_fwdout_ready),2); - vcdp->fullBus(c+58449,(vlTOPp->snp_fwdin_valid),2); - vcdp->fullBus(c+58457,(vlTOPp->snp_fwdin_tag),2); - vcdp->fullBus(c+58465,(vlTOPp->snp_fwdin_ready),2); - vcdp->fullBit(c+58473,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) - >> (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58481,(((IData)(vlTOPp->dram_rsp_valid) - & (0U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBus(c+58489,((0x1ffffffU & (vlTOPp->dram_rsp_tag - >> 3U))),25); - vcdp->fullBit(c+58497,(((IData)(vlTOPp->snp_req_valid) - & (0U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBus(c+58505,((0x1ffffffU & (vlTOPp->snp_req_addr - >> 3U))),25); - vcdp->fullBit(c+58513,(((IData)(vlTOPp->dram_rsp_valid) - & (1U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBit(c+58521,(((IData)(vlTOPp->snp_req_valid) - & (1U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58529,(((IData)(vlTOPp->dram_rsp_valid) - & (2U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBit(c+58537,(((IData)(vlTOPp->snp_req_valid) - & (2U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58545,(((IData)(vlTOPp->dram_rsp_valid) - & (3U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBit(c+58553,(((IData)(vlTOPp->snp_req_valid) - & (3U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58561,(((IData)(vlTOPp->dram_rsp_valid) - & (4U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBit(c+58569,(((IData)(vlTOPp->snp_req_valid) - & (4U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58577,(((IData)(vlTOPp->dram_rsp_valid) - & (5U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBit(c+58585,(((IData)(vlTOPp->snp_req_valid) - & (5U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58593,(((IData)(vlTOPp->dram_rsp_valid) - & (6U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBit(c+58601,(((IData)(vlTOPp->snp_req_valid) - & (6U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58609,(((IData)(vlTOPp->dram_rsp_valid) - & (7U == (7U & vlTOPp->dram_rsp_tag))))); - vcdp->fullBit(c+58617,(((IData)(vlTOPp->snp_req_valid) - & (7U == (7U & vlTOPp->snp_req_addr))))); - vcdp->fullBit(c+58625,(((IData)(vlTOPp->dram_req_valid) + vcdp->fullBus(c+22625,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__size_r),3); + vcdp->fullArray(c+22633,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[0]),314); + vcdp->fullArray(c+22643,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[1]),314); + vcdp->fullArray(c+22653,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[2]),314); + vcdp->fullArray(c+22663,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__data[3]),314); + vcdp->fullArray(c+22953,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),314); + vcdp->fullArray(c+23033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),314); + vcdp->fullBus(c+23113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+23121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+23129,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+23137,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__core_req_arb__DOT__reqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullArray(c+23145,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__s0_1_c0__DOT__value),243); + vcdp->fullQuad(c+23209,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__dirty),64); + vcdp->fullQuad(c+23225,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__valid),64); + vcdp->fullBus(c+23241,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__i),32); + vcdp->fullBus(c+23249,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__tag_data_structure__DOT__j),32); + vcdp->fullArray(c+23257,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__tag_data_access__DOT__s0_1_c0__DOT__value),166); + vcdp->fullArray(c+23305,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__st_1e_2__DOT__value),316); + vcdp->fullArray(c+23385,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[0]),85); + vcdp->fullArray(c+23388,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[1]),85); + vcdp->fullArray(c+23391,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[2]),85); + vcdp->fullArray(c+23394,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[3]),85); + vcdp->fullArray(c+23397,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[4]),85); + vcdp->fullArray(c+23400,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[5]),85); + vcdp->fullArray(c+23403,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[6]),85); + vcdp->fullArray(c+23406,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[7]),85); + vcdp->fullArray(c+23409,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[8]),85); + vcdp->fullArray(c+23412,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[9]),85); + vcdp->fullArray(c+23415,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[10]),85); + vcdp->fullArray(c+23418,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[11]),85); + vcdp->fullArray(c+23421,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[12]),85); + vcdp->fullArray(c+23424,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[13]),85); + vcdp->fullArray(c+23427,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[14]),85); + vcdp->fullArray(c+23430,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__metadata_table[15]),85); + vcdp->fullArray(c+23769,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__addr_table),416); + vcdp->fullBus(c+23873,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__valid_table),16); + vcdp->fullBus(c+23881,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__ready_table),16); + vcdp->fullBus(c+23889,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__schedule_ptr),4); + vcdp->fullBus(c+23897,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__head_ptr),4); + vcdp->fullBus(c+23905,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__tail_ptr),4); + vcdp->fullBus(c+23913,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size),5); + vcdp->fullBit(c+23921,((0x10U != (IData)(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cache_miss_resrv__DOT__size)))); + vcdp->fullBus(c+23929,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__size_r),3); + vcdp->fullArray(c+23937,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[0]),76); + vcdp->fullArray(c+23940,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[1]),76); + vcdp->fullArray(c+23943,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[2]),76); + vcdp->fullArray(c+23946,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__data[3]),76); + vcdp->fullArray(c+24033,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),76); + vcdp->fullArray(c+24057,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),76); + vcdp->fullBus(c+24081,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+24089,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+24097,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+24105,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__cwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBus(c+24113,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__size_r),3); + vcdp->fullArray(c+24121,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[0]),200); + vcdp->fullArray(c+24128,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[1]),200); + vcdp->fullArray(c+24135,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[2]),200); + vcdp->fullArray(c+24142,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__data[3]),200); + vcdp->fullArray(c+24345,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__head_r),200); + vcdp->fullArray(c+24401,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__curr_r),200); + vcdp->fullBus(c+24457,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__wr_ptr_r),2); + vcdp->fullBus(c+24465,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_r),2); + vcdp->fullBus(c+24473,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__rd_ptr_next_r),2); + vcdp->fullBit(c+24481,(vlTOPp->VX_cache__DOT__genblk5__BRA__3__KET____DOT__bank__DOT__dwb_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r)); + vcdp->fullBit(c+24489,(vlTOPp->clk)); + vcdp->fullBit(c+24497,(vlTOPp->reset)); + vcdp->fullBus(c+24505,(vlTOPp->core_req_valid),4); + vcdp->fullBus(c+24513,(vlTOPp->core_req_rw),4); + vcdp->fullBus(c+24521,(vlTOPp->core_req_byteen),16); + vcdp->fullArray(c+24529,(vlTOPp->core_req_addr),120); + vcdp->fullArray(c+24561,(vlTOPp->core_req_data),128); + vcdp->fullQuad(c+24593,(vlTOPp->core_req_tag),42); + vcdp->fullBit(c+24609,(vlTOPp->core_req_ready)); + vcdp->fullBus(c+24617,(vlTOPp->core_rsp_valid),4); + vcdp->fullArray(c+24625,(vlTOPp->core_rsp_data),128); + vcdp->fullQuad(c+24657,(vlTOPp->core_rsp_tag),42); + vcdp->fullBit(c+24673,(vlTOPp->core_rsp_ready)); + vcdp->fullBit(c+24681,(vlTOPp->dram_req_valid)); + vcdp->fullBit(c+24689,(vlTOPp->dram_req_rw)); + vcdp->fullBus(c+24697,(vlTOPp->dram_req_byteen),16); + vcdp->fullBus(c+24705,(vlTOPp->dram_req_addr),28); + vcdp->fullArray(c+24713,(vlTOPp->dram_req_data),128); + vcdp->fullBus(c+24745,(vlTOPp->dram_req_tag),28); + vcdp->fullBit(c+24753,(vlTOPp->dram_req_ready)); + vcdp->fullBit(c+24761,(vlTOPp->dram_rsp_valid)); + vcdp->fullArray(c+24769,(vlTOPp->dram_rsp_data),128); + vcdp->fullBus(c+24801,(vlTOPp->dram_rsp_tag),28); + vcdp->fullBit(c+24809,(vlTOPp->dram_rsp_ready)); + vcdp->fullBit(c+24817,(vlTOPp->snp_req_valid)); + vcdp->fullBus(c+24825,(vlTOPp->snp_req_addr),28); + vcdp->fullBit(c+24833,(vlTOPp->snp_req_invalidate)); + vcdp->fullBus(c+24841,(vlTOPp->snp_req_tag),28); + vcdp->fullBit(c+24849,(vlTOPp->snp_req_ready)); + vcdp->fullBit(c+24857,(vlTOPp->snp_rsp_valid)); + vcdp->fullBus(c+24865,(vlTOPp->snp_rsp_tag),28); + vcdp->fullBit(c+24873,(vlTOPp->snp_rsp_ready)); + vcdp->fullBus(c+24881,(vlTOPp->snp_fwdout_valid),2); + vcdp->fullQuad(c+24889,(vlTOPp->snp_fwdout_addr),56); + vcdp->fullBus(c+24905,(vlTOPp->snp_fwdout_invalidate),2); + vcdp->fullBus(c+24913,(vlTOPp->snp_fwdout_tag),2); + vcdp->fullBus(c+24921,(vlTOPp->snp_fwdout_ready),2); + vcdp->fullBus(c+24929,(vlTOPp->snp_fwdin_valid),2); + vcdp->fullBus(c+24937,(vlTOPp->snp_fwdin_tag),2); + vcdp->fullBus(c+24945,(vlTOPp->snp_fwdin_ready),2); + vcdp->fullBit(c+24953,((1U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_snp_req_ready) + >> (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+24961,(((IData)(vlTOPp->dram_rsp_valid) + & (0U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBus(c+24969,((0x3ffffffU & (vlTOPp->dram_rsp_tag + >> 2U))),26); + vcdp->fullBit(c+24977,(((IData)(vlTOPp->snp_req_valid) + & (0U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBus(c+24985,((0x3ffffffU & (vlTOPp->snp_req_addr + >> 2U))),26); + vcdp->fullBit(c+24993,(((IData)(vlTOPp->dram_rsp_valid) + & (1U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+25001,(((IData)(vlTOPp->snp_req_valid) + & (1U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+25009,(((IData)(vlTOPp->dram_rsp_valid) + & (2U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+25017,(((IData)(vlTOPp->snp_req_valid) + & (2U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+25025,(((IData)(vlTOPp->dram_rsp_valid) + & (3U == (3U & vlTOPp->dram_rsp_tag))))); + vcdp->fullBit(c+25033,(((IData)(vlTOPp->snp_req_valid) + & (3U == (3U & vlTOPp->snp_req_addr))))); + vcdp->fullBit(c+25041,(((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))))); - vcdp->fullBit(c+58633,((((IData)(vlTOPp->dram_req_valid) + vcdp->fullBit(c+25049,((((IData)(vlTOPp->dram_req_valid) & (~ (IData)(vlTOPp->dram_req_rw))) - & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__genblk3__DOT__genblk2__DOT__full_r))))); - vcdp->fullBus(c+58641,(0U),32); - vcdp->fullBus(c+58649,(0x800U),32); - vcdp->fullBus(c+58657,(0x10U),32); - vcdp->fullBus(c+58665,(8U),32); - vcdp->fullBus(c+58673,(4U),32); - vcdp->fullBus(c+58681,(1U),32); - vcdp->fullBus(c+58689,(0x2aU),32); - vcdp->fullBus(c+58697,(0x1cU),32); - vcdp->fullBus(c+58705,(2U),32); - vcdp->fullBus(c+58713,(4U),32); - vcdp->fullBit(c+58721,(0U)); - vcdp->fullBus(c+58729,(0xe8U),32); - vcdp->fullBus(c+58737,(8U),32); - vcdp->fullBus(c+58745,(0U),32); - vcdp->fullBus(c+58753,(1U),32); - vcdp->fullBus(c+58761,(0x36U),32); - vcdp->fullBus(c+58769,(0x99U),32); - vcdp->fullBus(c+58777,(0x13aU),32); - vcdp->fullBus(c+58785,(0xf2U),32); - vcdp->fullBus(c+58793,(0xa7U),32); - vcdp->fullBus(c+58801,(0x13cU),32); - vcdp->fullBus(c+58809,(0x4cU),32); - vcdp->fullBus(c+58817,(0xc7U),32); - vcdp->fullBus(c+58825,(2U),32); - vcdp->fullBus(c+58833,(3U),32); - vcdp->fullBus(c+58841,(5U),32); - vcdp->fullBus(c+58849,(6U),32); - vcdp->fullBus(c+58857,(7U),32); + & (~ (IData)(vlTOPp->VX_cache__DOT__cache_dram_req_arb__DOT__prfqq__DOT__pfq_queue__DOT__size_r))))); + vcdp->fullBus(c+25057,(0U),32); + vcdp->fullBus(c+25065,(0x1000U),32); + vcdp->fullBus(c+25073,(0x10U),32); + vcdp->fullBus(c+25081,(4U),32); + vcdp->fullBus(c+25089,(1U),32); + vcdp->fullBus(c+25097,(0x2aU),32); + vcdp->fullBus(c+25105,(8U),32); + vcdp->fullBus(c+25113,(0x1cU),32); + vcdp->fullBus(c+25121,(2U),32); + vcdp->fullBus(c+25129,(4U),32); + vcdp->fullBit(c+25137,(0U)); + vcdp->fullBus(c+25145,(0x74U),32); + vcdp->fullBus(c+25153,(0U),32); + vcdp->fullBus(c+25161,(1U),32); + vcdp->fullBus(c+25169,(0x37U),32); + vcdp->fullBus(c+25177,(0x9aU),32); + vcdp->fullBus(c+25185,(0x13aU),32); + vcdp->fullBus(c+25193,(0xf3U),32); + vcdp->fullBus(c+25201,(0xa6U),32); + vcdp->fullBus(c+25209,(0x13cU),32); + vcdp->fullBus(c+25217,(0x4cU),32); + vcdp->fullBus(c+25225,(0xc8U),32); + vcdp->fullBus(c+25233,(2U),32); + vcdp->fullBus(c+25241,(3U),32); } } diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ver.d b/hw/unit_tests/cache/obj_dir/VVX_cache__ver.d new file mode 100644 index 00000000..ddad5949 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__ver.d @@ -0,0 +1 @@ +obj_dir/VVX_cache.cpp obj_dir/VVX_cache.h obj_dir/VVX_cache.mk obj_dir/VVX_cache__Syms.cpp obj_dir/VVX_cache__Syms.h obj_dir/VVX_cache__Trace.cpp obj_dir/VVX_cache__Trace__Slow.cpp obj_dir/VVX_cache__ver.d obj_dir/VVX_cache_classes.mk : /usr/local/bin/verilator_bin ../../rtl//VX_config.vh ../../rtl//VX_define.vh ../../rtl//VX_scope.vh ../../rtl//VX_user_config.vh ../../rtl/cache/VX_bank.v ../../rtl/cache/VX_bank_core_req_arb.v ../../rtl/cache/VX_cache.v ../../rtl/cache/VX_cache_config.vh ../../rtl/cache/VX_cache_core_req_bank_sel.v ../../rtl/cache/VX_cache_core_rsp_merge.v ../../rtl/cache/VX_cache_dram_fill_arb.v ../../rtl/cache/VX_cache_dram_req_arb.v ../../rtl/cache/VX_cache_miss_resrv.v ../../rtl/cache/VX_prefetcher.v ../../rtl/cache/VX_snp_forwarder.v ../../rtl/cache/VX_snp_rsp_arb.v ../../rtl/cache/VX_tag_data_access.v ../../rtl/cache/VX_tag_data_structure.v ../../rtl/libs/VX_fair_arbiter.v ../../rtl/libs/VX_fixed_arbiter.v ../../rtl/libs/VX_generic_queue.v ../../rtl/libs/VX_generic_register.v ../../rtl/libs/VX_indexable_queue.v ../../rtl/libs/VX_priority_encoder.v /usr/local/bin/verilator_bin diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat b/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat new file mode 100644 index 00000000..74156b70 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat @@ -0,0 +1,37 @@ +# DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. +C "--language 1800-2009 --assert -Wall --trace -Wno-DECLFILENAME --x-initial unique -exe cachesim.cpp testbench.cpp -I../../rtl/ -I../../rtl/cache -I../../rtl/libs -DNDEBUG -cc VX_cache.v -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -CFLAGS -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 --exe cachesim.cpp testbench.cpp" +S 6992 4983715 1593571269 845187304 1593571269 845187304 "../../rtl//VX_config.vh" +S 8927 4983721 1593571269 845187304 1593571269 845187304 "../../rtl//VX_define.vh" +S 16028 4983736 1593571269 849188141 1593571269 849188141 "../../rtl//VX_scope.vh" +S 147 4980795 1592347024 921834494 1592347024 921834494 "../../rtl//VX_user_config.vh" +S 34555 4983741 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank.v" +S 6128 4983742 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank_core_req_arb.v" +S 22942 4985366 1594500482 317211549 1594500482 317211549 "../../rtl/cache/VX_cache.v" +S 2842 4983744 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_config.vh" +S 1745 4983745 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_req_bank_sel.v" +S 3719 4983746 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_rsp_merge.v" +S 3602 4983747 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_dram_fill_arb.v" +S 4396 4985343 1593571951 15994059 1593571951 7993214 "../../rtl/cache/VX_cache_dram_req_arb.v" +S 7305 4983749 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_miss_resrv.v" +S 1996 4983748 1593571988 408039126 1593571988 396037801 "../../rtl/cache/VX_prefetcher.v" +S 5064 4983751 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_forwarder.v" +S 1210 4983752 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_rsp_arb.v" +S 8840 4983753 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_access.v" +S 3211 4983754 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_structure.v" +S 1865 4983777 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fair_arbiter.v" +S 1022 4983778 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fixed_arbiter.v" +S 5974 4983779 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_queue.v" +S 582 4983780 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_register.v" +S 1552 4983782 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_indexable_queue.v" +S 491 4983785 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_priority_encoder.v" +S 8183216 2503059 1591812755 756668753 1591812755 756668753 "/usr/local/bin/verilator_bin" +T 3001929 4983824 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.cpp" +T 93468 4983825 1594500491 473600112 1594500491 473600112 "obj_dir/VVX_cache.h" +T 2104 4983826 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.mk" +T 8694 4983827 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.cpp" +T 4866 4983828 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.h" +T 429460 4983829 1594500491 469599943 1594500491 469599943 "obj_dir/VVX_cache__Trace.cpp" +T 700979 4983830 1594500491 461599603 1594500491 461599603 "obj_dir/VVX_cache__Trace__Slow.cpp" +T 1118 4980960 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__ver.d" +T 0 0 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__verFiles.dat" +T 1315 4983831 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache_classes.mk" diff --git a/hw/unit_tests/cache/obj_dir/cache_sim.d b/hw/unit_tests/cache/obj_dir/cache_sim.d new file mode 100644 index 00000000..55cd8534 --- /dev/null +++ b/hw/unit_tests/cache/obj_dir/cache_sim.d @@ -0,0 +1,6 @@ +cache_sim.o: ../cache_sim.cpp VVX_cache.h \ + /usr/local/share/verilator/include/verilated_heavy.h \ + /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilatedos.h VVX_cache__Syms.h \ + VVX_cache.h /usr/local/share/verilator/include/verilated.h \ + /usr/local/share/verilator/include/verilated_vcd_c.h diff --git a/hw/unit_tests/cache/obj_dir/cache_sim.o b/hw/unit_tests/cache/obj_dir/cache_sim.o new file mode 100644 index 0000000000000000000000000000000000000000..26536c9d0ddea6044d625b64f35a6ebaf96d89c2 GIT binary patch literal 6200 zcmbuDUu+b|8Nla!1Op+qLrP0Z)m{Q=fx^ZY426iaXUxJ{b%GO^il?1|^XasYs3bPxK|CRTNHO+2k#$(iWwWLZwzhkO#;^WvNux@0*?P zZfM~^~*Rtu^1IB|Y;L$kWMS?z6B`+A+BtQ)iXt>(f4bI=;ypJrCEZ1b{P;$_>+9)CE|v<elW!Th$6=D^80b&>M#lgh?DC1mz5X`x~<(pBZ3taD`?6 zVFdq=@PntOFXGvPY7b0!n4edm?`~!N(EZs2`m2<6D4s#keME9Iu_Gt0ClZSFdG%_@}`e=Oq-C3lt_+p>>2uFb7t!S%`&%adJO&0MZ% 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a/hw/unit_tests/cache/obj_dir/VVX_cache.cpp +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.cpp @@ -13,7 +13,7 @@ CData/*1:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_ba CData/*0:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16]; IData/*31:0*/ VVX_cache::__Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; CData/*1:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16]; -CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16]; +CData/*0:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16]; IData/*31:0*/ VVX_cache::__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; CData/*1:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16]; CData/*0:0*/ VVX_cache::__Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16]; @@ -1307,8 +1307,8 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index [vlTOPp->__Vtableidx3]; - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid - = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid [vlTOPp->__Vtableidx3]; vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i @@ -2944,8 +2944,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) : VL_ULL(0)); vlTOPp->core_rsp_valid = 0U; - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) == ((0xa7U >= (0xffU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -2971,115 +2970,100 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { | ((IData)(1U) << (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] - >> 0xaU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) | ((IData)(1U) << (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 2U)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - >> 0x14U))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) | ((IData)(1U) << (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 4U)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] - << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - >> 0x1eU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) | ((IData)(1U) << (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) @@ -3089,8 +3073,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U; - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) == ((0xa7U >= (0xffU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -3116,121 +3099,105 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] - >> 0xaU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - >> 0x14U))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] - << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - >> 0x1eU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); } vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) == ((0xa7U >= (0xffU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -3256,8 +3223,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] @@ -3298,8 +3264,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U)) << 1U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] @@ -3340,8 +3305,7 @@ void VVX_cache::_settle__TOP__3(VVX_cache__Syms* __restrict vlSymsp) { : 0U)) << 2U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] @@ -19351,8 +19315,8 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index [vlTOPp->__Vtableidx3]; - vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid - = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid + vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid + = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid [vlTOPp->__Vtableidx3]; vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = vlTOPp->__Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i @@ -20069,8 +20033,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) : VL_ULL(0)); vlTOPp->core_rsp_valid = 0U; - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) == ((0xa7U >= (0xffU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -20096,115 +20059,100 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | ((IData)(1U) << (3U & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] - >> 0xaU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) | ((IData)(1U) << (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 2U)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - >> 0x14U))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) | ((IData)(1U) << (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 4U)))); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] - << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - >> 0x1eU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { vlTOPp->core_rsp_valid = ((IData)(vlTOPp->core_rsp_valid) | ((IData)(1U) << (3U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) @@ -20214,8 +20162,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[1U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[2U] = 0U; vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data[3U] = 0U; - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + if (((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) == ((0xa7U >= (0xffU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -20241,113 +20188,98 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym << 5U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[0U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 1U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] - >> 0xaU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 1U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] + >> 0xaU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) << 3U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[1U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 2U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] - >> 0x14U))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 2U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] + >> 0x14U))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) << 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[2U]); } - if ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) - >> 3U)) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] - << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] - >> 0x1eU))) - == ((0xa7U >= (0xffU & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? (0xffU & (((0U == (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) - ? 0U : ( - vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - ((IData)(1U) - + - (7U - & (((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U)))] - << - ((IData)(0x20U) - - - (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ - (7U & ( - ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) - >> 5U))] - >> (0x1fU - & ((IData)(0x2aU) - * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) - : 0U)))) { + if ((((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) + >> 3U) & ((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] + << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] + >> 0x1eU))) + == ((0xa7U >= (0xffU & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? (0xffU & (((0U == (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) + ? 0U : (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + ((IData)(1U) + + (7U + & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U)))] + << ((IData)(0x20U) + - + (0x1fU + & ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[ + (7U & (((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)) + >> 5U))] + >> (0x1fU & + ((IData)(0x2aU) + * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))))) + : 0U)))) { VL_ASSIGNSEL_WIII(32,(0x60U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_tid) >> 1U)), vlTOPp->VX_cache__DOT____Vcellout__cache_core_rsp_merge__core_rsp_data, vlTOPp->VX_cache__DOT__per_bank_core_rsp_data[3U]); @@ -20358,8 +20290,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym | ((IData)(1U) << (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((0xeU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & ((0xffU & vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[0U]) == ((0xa7U >= (0xffU & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index)))) @@ -20385,8 +20316,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((0xdU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffffeU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 1U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0xfffffffeU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] << 0x16U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[1U] @@ -20427,8 +20357,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U)) << 1U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((0xbU & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffffcU & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 2U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0xfffffffcU & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] << 0xcU) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[2U] @@ -20469,8 +20398,7 @@ VL_INLINE_OPT void VVX_cache::_sequent__TOP__4(VVX_cache__Syms* __restrict vlSym : 0U)) << 2U)))); vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = ((7U & (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual)) - | (0xfffffff8U & ((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid) - << 3U) & (IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid)) + | (0xfffffff8U & ((IData)(vlTOPp->VX_cache__DOT__per_bank_core_rsp_valid) & (((0xffU & ((vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[4U] << 2U) | (vlTOPp->VX_cache__DOT__per_bank_core_rsp_tag[3U] @@ -27083,9 +27011,9 @@ void VVX_cache::_ctor_var_reset() { VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r = VL_RAND_RESET_I(4); VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i = VL_RAND_RESET_I(32); - VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(4); VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index = VL_RAND_RESET_I(2); - VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid = VL_RAND_RESET_I(1); + VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual = VL_RAND_RESET_I(4); + VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid = VL_RAND_RESET_I(1); VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use = VL_RAND_RESET_I(4); VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value = VL_RAND_RESET_I(4); VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill = VL_RAND_RESET_I(1); @@ -28079,22 +28007,22 @@ void VVX_cache::_ctor_var_reset() { __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[13] = 0U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[14] = 1U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[15] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[0] = 0U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[1] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[2] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[3] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[4] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[5] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[6] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[7] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[8] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[9] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[10] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[11] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[12] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[13] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[14] = 1U; - __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[15] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[0] = 0U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[1] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[2] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[3] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[4] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[5] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[6] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[7] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[8] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[9] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[10] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[11] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[12] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[13] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[14] = 1U; + __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[15] = 1U; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[0] = 0xffffffffU; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[1] = 0xffffffffU; __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[2] = 0xffffffffU; diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache.h b/hw/unit_tests/cache/obj_dir/VVX_cache.h index 8661c1ff..78b800c1 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache.h +++ b/hw/unit_tests/cache/obj_dir/VVX_cache.h @@ -117,9 +117,9 @@ VL_MODULE(VVX_cache) { CData/*0:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__dfqq_queue__DOT__genblk3__DOT__genblk2__DOT__bypass_r; CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__dram_fill_arb__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r; CData/*3:0*/ VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__grant_onehot_r; - CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual; CData/*1:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index; - CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid; + CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual; + CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid; CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use; CData/*3:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__update_value; CData/*0:0*/ VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill; @@ -864,7 +864,7 @@ VL_MODULE(VVX_cache) { static CData/*0:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__dwb_valid[16]; static IData/*31:0*/ __Vtable2_VX_cache__DOT__cache_dram_req_arb__DOT__sel_dwb__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; static CData/*1:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index[16]; - static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid[16]; + static CData/*0:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid[16]; static IData/*31:0*/ __Vtable3_VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__priority_encoder__DOT__i[16]; static CData/*1:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_bank[16]; static CData/*0:0*/ __Vtable4_VX_cache__DOT__snp_rsp_arb__DOT__fsq_valid[16]; diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a b/hw/unit_tests/cache/obj_dir/VVX_cache__ALL.a index 28bb172f13c23e3a0583ae4481f908546ad5a6fe..a6bb36568fe5410685c5f219f57228793184e174 100644 GIT binary patch delta 135555 zcmce<30PIt_y2#nTvQYl4JSZFr7R^y#UVu{B{QKy#k4|2!ZDn2sL+c_rAdm4Y%Nk$ z%pp=#5(hK~EC*CnOf5__GBYX%nhf)|_g(K3=dA1bJ>Spg_x=Cx^WgHl*K6&)*53O} zmvb-I4)jXN>y^^g9@O5?@rtf)u~_;ZN8TO;ZNlM6#P#(F>AA1 zWAVVa|!FSg*#i(0XHC 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a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp index bba93d74..8f72ecc5 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace.cpp @@ -564,10 +564,10 @@ void VVX_cache::traceChgThis__4(VVX_cache__Syms* __restrict vlSymsp, VerilatedVc & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) : VL_ULL(0))),42); - vcdp->chgBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); - vcdp->chgBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); - vcdp->chgBit(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); - vcdp->chgBus(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); + vcdp->chgBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); + vcdp->chgBus(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->chgBit(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid)); vcdp->chgBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp index 7aef5ddd..d54d85df 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__Trace__Slow.cpp @@ -490,28 +490,27 @@ void VVX_cache::traceInitThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV vcdp->declArray(c+2217,"VX_cache cache_core_rsp_merge core_rsp_data", false,-1, 127,0); vcdp->declQuad(c+2249,"VX_cache cache_core_rsp_merge core_rsp_tag", false,-1, 41,0); vcdp->declBit(c+24673,"VX_cache cache_core_rsp_merge core_rsp_ready", false,-1); - vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 3,0); - vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 1,0); - vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge grant_valid", false,-1); + vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge main_bank_index", false,-1, 1,0); + vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge per_bank_core_rsp_pop_unqual", false,-1, 3,0); vcdp->declBus(c+25129,"VX_cache cache_core_rsp_merge i", false,-1, 31,0); vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank N", false,-1, 31,0); vcdp->declBit(c+24489,"VX_cache cache_core_rsp_merge sel_bank clk", false,-1); vcdp->declBit(c+24497,"VX_cache cache_core_rsp_merge sel_bank reset", false,-1); vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank requests", false,-1, 3,0); - vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 1,0); - vcdp->declBus(c+2289,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 3,0); - vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1); + vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge sel_bank grant_index", false,-1, 1,0); + vcdp->declBus(c+2281,"VX_cache cache_core_rsp_merge sel_bank grant_onehot", false,-1, 3,0); + vcdp->declBit(c+2289,"VX_cache cache_core_rsp_merge sel_bank grant_valid", false,-1); vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 requests_use", false,-1, 3,0); vcdp->declBus(c+2297,"VX_cache cache_core_rsp_merge sel_bank genblk2 update_value", false,-1, 3,0); vcdp->declBus(c+2305,"VX_cache cache_core_rsp_merge sel_bank genblk2 late_value", false,-1, 3,0); vcdp->declBit(c+10585,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill", false,-1); vcdp->declBus(c+1097,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_value", false,-1, 3,0); vcdp->declBus(c+10593,"VX_cache cache_core_rsp_merge sel_bank genblk2 refill_original", false,-1, 3,0); - vcdp->declBus(c+2289,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 3,0); + vcdp->declBus(c+2281,"VX_cache cache_core_rsp_merge sel_bank genblk2 grant_onehot_r", false,-1, 3,0); vcdp->declBus(c+25081,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder N", false,-1, 31,0); vcdp->declBus(c+10577,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_in", false,-1, 3,0); - vcdp->declBus(c+2273,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); - vcdp->declBit(c+2281,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1); + vcdp->declBus(c+2265,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder data_out", false,-1, 1,0); + vcdp->declBit(c+2289,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder valid_out", false,-1); vcdp->declBus(c+2313,"VX_cache cache_core_rsp_merge sel_bank genblk2 priority_encoder i", false,-1, 31,0); vcdp->declBus(c+25081,"VX_cache snp_rsp_arb NUM_BANKS", false,-1, 31,0); vcdp->declBus(c+25073,"VX_cache snp_rsp_arb BANK_LINE_SIZE", false,-1, 31,0); @@ -3414,10 +3413,10 @@ void VVX_cache::traceFullThis__1(VVX_cache__Syms* __restrict vlSymsp, VerilatedV & ((IData)(0x2aU) * (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index))))))) : VL_ULL(0))),42); - vcdp->fullBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); - vcdp->fullBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); - vcdp->fullBit(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__grant_valid)); - vcdp->fullBus(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBus(c+2265,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__main_bank_index),2); + vcdp->fullBus(c+2273,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__per_bank_core_rsp_pop_unqual),4); + vcdp->fullBus(c+2281,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r),4); + vcdp->fullBit(c+2289,(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__grant_valid)); vcdp->fullBus(c+2297,((((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__requests_use) & (~ (IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__grant_onehot_r))) | (((IData)(vlTOPp->VX_cache__DOT__cache_core_rsp_merge__DOT__sel_bank__DOT__genblk2__DOT__refill_original) diff --git a/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat b/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat index 74156b70..105011a4 100644 --- a/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat +++ b/hw/unit_tests/cache/obj_dir/VVX_cache__verFiles.dat @@ -1,7 +1,7 @@ # DESCRIPTION: Verilator output: Timestamp data for --skip-identical. Delete at will. C "--language 1800-2009 --assert -Wall --trace -Wno-DECLFILENAME --x-initial unique -exe cachesim.cpp testbench.cpp -I../../rtl/ -I../../rtl/cache -I../../rtl/libs -DNDEBUG -cc VX_cache.v -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 -CFLAGS -std=c++11 -fms-extensions -I../.. -DNDEBUG -DCACHE_SIZE=4096 -DWORD_SIZE=4 -DBANK_LINE_SIZE=16 -DNUM_BANKS=4 -DCREQ_SIZE=4 -DMRVQ_SIZE=16 -DDFPQ_SIZE=16 -DSNRQ_SIZE=16 -DCWBQ_SIZE=4 -DDWBQ_SIZE=4 -DFQQ_SIZE=4 --exe cachesim.cpp testbench.cpp" -S 6992 4983715 1593571269 845187304 1593571269 845187304 "../../rtl//VX_config.vh" -S 8927 4983721 1593571269 845187304 1593571269 845187304 "../../rtl//VX_define.vh" +S 7349 4983714 1594698569 774801969 1594698569 774801969 "../../rtl//VX_config.vh" +S 9046 4983721 1594698569 778802144 1594698569 778802144 "../../rtl//VX_define.vh" S 16028 4983736 1593571269 849188141 1593571269 849188141 "../../rtl//VX_scope.vh" S 147 4980795 1592347024 921834494 1592347024 921834494 "../../rtl//VX_user_config.vh" S 34555 4983741 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_bank.v" @@ -9,29 +9,29 @@ S 6128 4983742 1593571269 849188141 1593571269 849188141 "../../rtl/ S 22942 4985366 1594500482 317211549 1594500482 317211549 "../../rtl/cache/VX_cache.v" S 2842 4983744 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_config.vh" S 1745 4983745 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_req_bank_sel.v" -S 3719 4983746 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_core_rsp_merge.v" +S 3649 4983746 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_core_rsp_merge.v" S 3602 4983747 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_dram_fill_arb.v" S 4396 4985343 1593571951 15994059 1593571951 7993214 "../../rtl/cache/VX_cache_dram_req_arb.v" -S 7305 4983749 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_cache_miss_resrv.v" +S 7304 4983749 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_cache_miss_resrv.v" S 1996 4983748 1593571988 408039126 1593571988 396037801 "../../rtl/cache/VX_prefetcher.v" -S 5064 4983751 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_forwarder.v" +S 5067 4983751 1594698569 778802144 1594698569 778802144 "../../rtl/cache/VX_snp_forwarder.v" S 1210 4983752 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_snp_rsp_arb.v" S 8840 4983753 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_access.v" S 3211 4983754 1593571269 849188141 1593571269 849188141 "../../rtl/cache/VX_tag_data_structure.v" -S 1865 4983777 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fair_arbiter.v" -S 1022 4983778 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_fixed_arbiter.v" -S 5974 4983779 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_queue.v" -S 582 4983780 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_generic_register.v" -S 1552 4983782 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_indexable_queue.v" -S 491 4983785 1593571269 849188141 1593571269 849188141 "../../rtl/libs/VX_priority_encoder.v" +S 1861 4983777 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fair_arbiter.v" +S 1022 4983778 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_fixed_arbiter.v" +S 5977 4983779 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_queue.v" +S 586 4983780 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_generic_register.v" +S 1560 4983782 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_indexable_queue.v" +S 495 4983785 1594698569 778802144 1594698569 778802144 "../../rtl/libs/VX_priority_encoder.v" S 8183216 2503059 1591812755 756668753 1591812755 756668753 "/usr/local/bin/verilator_bin" -T 3001929 4983824 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.cpp" -T 93468 4983825 1594500491 473600112 1594500491 473600112 "obj_dir/VVX_cache.h" -T 2104 4983826 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache.mk" -T 8694 4983827 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.cpp" -T 4866 4983828 1594500491 449599094 1594500491 449599094 "obj_dir/VVX_cache__Syms.h" -T 429460 4983829 1594500491 469599943 1594500491 469599943 "obj_dir/VVX_cache__Trace.cpp" -T 700979 4983830 1594500491 461599603 1594500491 461599603 "obj_dir/VVX_cache__Trace__Slow.cpp" -T 1118 4980960 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__ver.d" -T 0 0 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache__verFiles.dat" -T 1315 4983831 1594500491 517601979 1594500491 517601979 "obj_dir/VVX_cache_classes.mk" +T 2996411 4983824 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.cpp" +T 93498 4983825 1594698591 211740363 1594698591 211740363 "obj_dir/VVX_cache.h" +T 2104 4983826 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache.mk" +T 8694 4983827 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.cpp" +T 4866 4983828 1594698591 179738962 1594698591 179738962 "obj_dir/VVX_cache__Syms.h" +T 429475 4983829 1594698591 207740187 1594698591 207740187 "obj_dir/VVX_cache__Trace.cpp" +T 700909 4983830 1594698591 195739663 1594698591 195739663 "obj_dir/VVX_cache__Trace__Slow.cpp" +T 1118 4980960 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__ver.d" +T 0 0 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache__verFiles.dat" +T 1315 4983831 1594698591 263742640 1594698591 263742640 "obj_dir/VVX_cache_classes.mk" diff --git a/hw/unit_tests/cache/trace.vcd b/hw/unit_tests/cache/trace.vcd index 68a042c1..88157959 100644 --- a/hw/unit_tests/cache/trace.vcd +++ b/hw/unit_tests/cache/trace.vcd @@ -1,5 +1,5 @@ $version Generated by VerilatedVcd $end -$date Mon Jul 13 23:47:52 2020 +$date Mon Jul 13 23:50:00 2020 $end $timescale 1ns $end @@ -161,11 +161,10 @@ $timescale 1ns $end $var wire 1 Oj" core_rsp_ready $end $var wire 42 y7 core_rsp_tag [41:0] $end $var wire 4 ui" core_rsp_valid [3:0] $end - $var wire 1 ;8 grant_valid $end $var wire 32 Ao" i [31:0] $end - $var wire 2 38 main_bank_index [1:0] $end + $var wire 2 +8 main_bank_index [1:0] $end $var wire 128 q+ per_bank_core_rsp_data [127:0] $end - $var wire 4 +8 per_bank_core_rsp_pop_unqual [3:0] $end + $var wire 4 38 per_bank_core_rsp_pop_unqual [3:0] $end $var wire 4 + per_bank_core_rsp_ready [3:0] $end $var wire 168 3, per_bank_core_rsp_tag [167:0] $end $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end @@ -174,13 +173,13 @@ $timescale 1ns $end $scope module sel_bank $end $var wire 32 on" N [31:0] $end $var wire 1 Sh" clk $end - $var wire 2 38 grant_index [1:0] $end - $var wire 4 C8 grant_onehot [3:0] $end - $var wire 1 ;8 grant_valid $end + $var wire 2 +8 grant_index [1:0] $end + $var wire 4 ;8 grant_onehot [3:0] $end + $var wire 1 C8 grant_valid $end $var wire 4 a+ requests [3:0] $end $var wire 1 [h" reset $end $scope module genblk2 $end - $var wire 4 C8 grant_onehot_r [3:0] $end + $var wire 4 ;8 grant_onehot_r [3:0] $end $var wire 4 S8 late_value [3:0] $end $var wire 1 [2! refill $end $var wire 4 c2! refill_original [3:0] $end @@ -190,9 +189,9 @@ $timescale 1ns $end $scope module priority_encoder $end $var wire 32 on" N [31:0] $end $var wire 4 S2! data_in [3:0] $end - $var wire 2 38 data_out [1:0] $end + $var wire 2 +8 data_out [1:0] $end $var wire 32 [8 i [31:0] $end - $var wire 1 ;8 valid_out $end + $var wire 1 C8 valid_out $end $upscope $end $upscope $end $upscope $end @@ -3446,10 +3445,10 @@ b0001 I7 b11111111111111111111111111111111 Q7 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 Y7 b000111000101111011101101101100111010011000 y7 -b0000 +8 -b00 38 -1;8 -b0001 C8 +b00 +8 +b0000 38 +b0001 ;8 +1C8 b0010 K8 b0010 S8 b11111111111111111111111111111111 [8 @@ -4924,7 +4923,7 @@ b0000000000000000000000000000001100000000000000000000000000100000000000000000000 b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 o6 b0001 97 b000000000000000000000000000000000000000000 y7 -0;8 +0C8 b0000 K8 b0000 S8 b00 c8 @@ -10506,6 +10505,10 @@ b0000000000000000001100110100 qk" b00000000000000000011001101 ]m" 07n" #223 +b0001 + +1K +1q# +1?* b0001 a+ b00110010 i+ b01000100010001001101011110101010110000000110000101101111111110011111010011100101011100101110000000000000000000000000000000000000 q+ @@ -10516,6 +10519,7 @@ b00000000000000000000000000000000 i/ b100010100000101101101001001100010000001111 q/ b00000000000000000000000000000011000000000000000000000000001010011010100001000001100111010000000000000000000000000000 O6 b100010100000101101101001001100010000001111 y7 +b0001 38 b0001 K8 b0001 S8 b00000000000000000011001101 M9 @@ -10742,6 +10746,7 @@ b0001 /b" b0000000000000000000000000000000000000000000011110001110001100011111001001110 yc" b00000000000000000000100001011111011000011100011010111010101010111011010101110000111101100101010010100010100000101011011010000110010100110010111100011100011000111110010011100000000000000000000000000000 Yg" 1Sh" +b0100 ui" b100010100000101101101001001100010000001111 ?j" #224 b0000 3 @@ -10755,24 +10760,25 @@ b0000000000000000111000010000000000000000000000000000000000000000000000000000000 b0000000000000000111000010000 qk" b00000000000000001110000100 ]m" #225 -b0011 + -1K -1k -1q# -1u% -1?* -1_* -b0011 a+ -b00111110 i+ -b01000100010001001101011110101010110000000110000101101111111110010000000000000000000000000000000000000000000000000000000000000000 q+ -b011101100110010111111111110110010110010110101111110111000011001100011010100110100000100010100000101101101001001100010000001111100010100000101101101001001100010000001111 3, +b0000 + +0K +0q# +0?* +b0010 a+ +b00111111 i+ +b01000100010001001101011110101010110000000110000101101111111110010000000000000000000000000000000011110010111000110110001111011000 q+ +b011101100110010111111111110110010110010110101111110111000011001100011010100110100000100010100000101101101001001100010000001111101000010011100110110010000100000000001101 3, b1000000011101010100001110011000000000000000000000000001000000000000000000000000000010000000000000000000000000000 k, +b11 a/ +b11110010111000110110001111011000 i/ +b101000010011100110110010000100000000001101 q/ b11 s0 b00000000000000000000000000000000 {0 b100010100000101101101001001100010000001111 %1 b00001000000011101010100001110011000000000000000000000000001000000000000000000000000000010000000000000000000000000000 O6 -b0011 +8 -1;8 +b101000010011100110110010000100000000001101 y7 +b0000 38 +1C8 b0010 K8 b0010 S8 1E9 @@ -10806,6 +10812,7 @@ b0000000000001111 [H b0100000010000000000000000000000000000111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111100 'J 09K b0000000000000000000000000000000000000000000000000000000000000000000000000000 aK +b1110100001001110011011001000010000000000110111110010111000110110001111011000 yK b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ;L 0EU 0MU @@ -10876,6 +10883,7 @@ b0000001111111110 [*! b0110001010000010110110100100110001000000111100000000000000000000000000000000 5+! 1e+! b00000000000000000010000000111010101000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101101001001100010000001111 m+! +01-! 1Y-! b00000000000000000000000000 i-! b10000000111010101000011100 [.! @@ -10890,6 +10898,7 @@ b00100010001000100010001000100010 m3! b00000000000000000000000000000000 )5! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 15! b00000000000000000000 y5! +1[6! b00000000000000000000000000 {6! b00010 c:! b0000000000000000111000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 z:! @@ -10902,8 +10911,11 @@ b1000000000000000000000000000000000000000000000000000000000000000000000000000000 b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 -K! b0001111111110000 9Q! b0010 AQ! -b1010001010000010110110100100110001000000111100000000000000000000000000000000 sR! +b000 iQ! +b1110100001001110011011001000010000000000110111110010111000110110001111011000 sR! b0000000000000000000000000000000000000000000000110111011111100001111011110000 -S! +b01 MS! +b10 US! 0]S! b00000000000000000001010011010010010011000000000101001001111010110111111001011111001101010100010101111100011010010010010101100110001111001011001101110111111000011110111100000000000000000000000000000000 kV! b00 9Y! @@ -10960,7 +10972,8 @@ b0100000011000000011101010100001110001001110011110100111110100111010010000000000 b0000000000000000000000000000000000000000000010000001010010111110010001110100 yc" b00010100111100010001100101010001011101000000111100000101011011111101000010111010001000001010001101101100011111100011010100011010110101100010100000010100101111100100011101000000000000000000000000000000 Yg" 1Sh" -b1100 ui" +b0000 ui" +b101000010011100110110010000100000000001101 ?j" #226 b0001 3 1S @@ -10970,34 +10983,28 @@ b0001 3 0Ik" 0Um" #227 -b0000 + -0K -0k -0q# -0u% -0?* -0_* -b1000 a+ -b01110111 i+ -b00000000000000000000000000000000110000000110000101101111111110010011100110001000000010001010111011110010111000110110001111011000 q+ -b100010100000101101101001001100010000001111101111110111000011001100011010100110100000001101111011110111011001000100010111000000101000010011100110110010000100000000001101 3, +b1010 + +1k +1M! +1u% +1}) +1_* +1A+ +b1010 a+ +b01111111 i+ +b00000000000000000000000000000000110000000110000101101111111110010000000000000000000000000000000011110010111000110110001111011000 q+ +b100010100000101101101001001100010000001111101111110111000011001100011010100110100000100010100000101101101001001100010000001111101000010011100110110010000100000000001101 3, b0000000000000000000010101011000000000000000000000000001000000000000000000000000000010000000000000000000000000000 k, -b11 a/ -b11110010111000110110001111011000 i/ -b101000010011100110110010000100000000001101 q/ -b01 s0 -b00111001100010000000100010101110 {0 -b001101111011110111011001000100010111000000 %1 b01 93 b00000000000000000000000000000000 A3 b100010100000101101101001001100010000001111 I3 b00000000000000000000000010101011000000000000000000000000001000000000000000000000000000010000000000000000000000000000 O6 -b001101111011110111011001000100010111000000 y7 -b0000 +8 -b01 38 -b0010 C8 -b1000 K8 -b1000 S8 +b100010100000101101101001001100010000001111 y7 +b01 +8 +b1010 38 +b0010 ;8 +b1010 K8 +b1010 S8 b00000000000000001110000100 M9 1!; 1Y; @@ -11047,9 +11054,7 @@ b0000100100100100 )K 1IK 1QK b0000000000000000000000000000000000001111111100000000000000000000000000000000 aK -b1110100001001110011011001000010000000000110111110010111000110110001111011000 yK b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111 ;L -b0100110111101111011101100100010001011100000000111001100010000000100010101110 K` 1+x 13x 0Cx @@ -11099,8 +11104,6 @@ b0000000000000000000000000000000000000000000010000111010001010001101010010111 5+ b0110001010000010110110100100110001000000111100000000000000000000000000000000 M+! 0e+! b00000000000000000011101101100011111110101010111011011100110100011110100000000001110000000101101001000111001110100011001111011111001010011101100001110100010100011010100101110000000000000000000000000000 m+! -01-! -0Y-! 1K.! b00000000000000000000101010 [.! b00001000000011101010100001110011000000000000000000000000001000000000000000000000000000010000000000000000000000000000 q1! @@ -11112,7 +11115,6 @@ b1111 _4! b11111111111111111111111111111111 !5! b0000000000000000000000000000000000111111111111100 i5! 1C6! -1[6! b0000000000000000000011111111 %7! b00001 c:! b0000000000000000111000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 YA! @@ -11121,18 +11123,10 @@ b0100 [B! b000110000000000000000001100110100000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 II! b0000000000000000000000000000000000000000000000000000000000000001 +J! b0100000010000000000000000000000000000111111111111111111111111111111110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111100 -K! -b000 iQ! -b1110100001001110011011001000010000000000110111110010111000110110001111011000 sR! b0000000000000000000000000000000000000000000000000000000000000000000000000000 -S! -b01 MS! -b10 US! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 kV! -1U[! -b000 cv! -b0100110111101111011101100100010001011100000000111001100010000000100010101110 mw! +b1110001010000010110110100100110001000000111100000000000000000000000000000000 mw! b0000000000000000000000000000000000000000000001101111001001011100000011101011 'x! -b01 Gx! -b10 Ox! 0Wx! b00010010110111110110110111001111101111000000000101011001101010000100100110110110010110111011110011000011111011011100111101000011110011101101011011110010010111000000111010110000000000000000000000000000 e{! b00 -E" @@ -11165,21 +11159,34 @@ b01 3d" 1Kd" b00000000000000000010000000111010101000011100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001101101001001100010000001111 Yg" 1Sh" -b0000 ui" -b001101111011110111011001000100010111000000 ?j" +b1010 ui" +b100010100000101101101001001100010000001111 ?j" #228 0Sh" #229 -b1000 + -1M! -1}) -1A+ +b0000 + +0k +0M! +0u% +0}) +0_* +0A+ +b0000 a+ +b11110111 i+ +b01111100111000110010100101111101110000000110000101101111111110010011100110001000000010001010111011110010111000110110001111011000 q+ +b111100010110110101110001101001100010100000101111110111000011001100011010100110100000001101111011110111011001000100010111000000101000010011100110110010000100000000001101 3, b0000000000000000000000000011000000000000000000000000001000000000000000000000000000010000000000000000001100110100 k, +b01 s0 +b00111001100010000000100010101110 {0 +b001101111011110111011001000100010111000000 %1 +b11 93 +b01111100111000110010100101111101 A3 +b111100010110110101110001101001100010100000 I3 b00000000000000000000000000000011000000000000000000000000001000000000000000000000000000010000000000000000001100110100 O6 -b100010100000101101101001001100010000001111 y7 -b1000 +8 -b11 38 -b1000 C8 +b001101111011110111011001000100010111000000 y7 +b0000 38 +b1000 K8 +b0000 S8 0E9 b01101111100110011001100110 M9 b00101111110001011111001101101110110000001011111110000010011110000111110111011011001101001101110001100001101010110100100011010110 U9 @@ -11214,6 +11221,7 @@ b0001001001001000 )K 0IK b0000000000000000000000000000000000000000000010011011010101110101101110000101 aK b00000000000000000001100010010001001110001101011010110010000111011010010100100010100000001101010110000110000101100101000001000000010000001110100110110101011101011011100001010000000000000000000000000000 ;L +b0100110111101111011101100100010001011100000000111001100010000000100010101110 K` 1Cx 1=y 1gz @@ -11255,11 +11263,14 @@ b1000000000000000000000000000000000000000000000000000000000000000000000000000000 b0100000010000000000000000000010101000000100010001000100010001000100010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111111101 Y)! b0000001111111110 [*! b0000000000000000000000000000000000000000000010000001010010111110010001110100 5+! +b1111110001011011010111000110100110001010000001111100111000110010100101111101 M+! b00010100111100010001100101010001011101000000111100000101011011111101000010111010001000001010001101101100011111100011010100011010110101100010100000010100101111100100011101000000000000000000000000000000 m+! b00000000000000000011001101 A-! +0Y-! +0K.! b00000000000000000000000000 [.! b00000000000000000000000010101011000000000000000000000000001000000000000000000000000000010000000000000000000000000000 q1! -b1000 S2! +b1010 S2! 1{2! 0M3! b000000000000000000000000000000000000000000 G4! @@ -11289,44 +11300,42 @@ b0010 IQ! b01011 YQ! b0000000000000000000000000000000000001111111100000000000000000000000000000000 -S! b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011111111 kV! +1U[! +b000 cv! +b0100110111101111011101100100010001011100000000111001100010000000100010101110 mw! +b01 Gx! +b10 Ox! 0UE" b10000001010010111110010001110100 uE" b11110000010101101111110100001011101000100000101000110110110001111110001101010001101011010110001010000001010010111110010001110100 }E" b0101001111000100 OF" b01100101010001011101 gF" +1IG" b01100101010001011101000000 iG" b100110000000000000000000010101000000100010001000100010001000100010000000000000000000000000000000000111111111111101000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111001 7Z" b0001010011110001000110010101000101110111110000010101101111110100001011101000100000101000110110110001111110001101010001101011010110001010000001010010111110010001110100 I[" b0000000000000000000000000000000000000000000000000000000000000000000001000000101001011111001000111010011110000010101101111110100001011101000100000101000110110110001111110001101010001101011010110001010000001010010111110010001110100011001010100010111010001010011110001000000000000000000000000000000000000000000000000000 y[" b0000001111111100 'b" b0010 /b" -b0110001010000010110110100100110001000000111100000000000000000000000000000000 ac" +b000 Wb" +b1111110001011011010111000110100110001010000001111100111000110010100101111101 ac" b0000000000000000000000000000000000000000000010000111010001010001101010010111 yc" +b01 ;d" +b10 Cd" 0Kd" b00000000000000000011101101100011111110101010111011011100110100011110100000000001110000000101101001000111001110100011001111011111001010011101100001110100010100011010100101110000000000000000000000000000 Yg" 1Sh" -b0010 ui" -b100010100000101101101001001100010000001111 ?j" +b0000 ui" +b001101111011110111011001000100010111000000 ?j" #230 0Sh" #231 -b0000 + -0M! -0}) -0A+ -b0000 a+ -b11110111 i+ -b01111100111000110010100101111101110000000110000101101111111110010011100110001000000010001010111011110010111000110110001111011000 q+ -b111100010110110101110001101001100010100000101111110111000011001100011010100110100000001101111011110111011001000100010111000000101000010011100110110010000100000000001101 3, b0000000000000000000010101011000000000000000000000000001000000000000000000000000000010000000000000000111000010000 k, -b11 93 -b01111100111000110010100101111101 A3 -b111100010110110101110001101001100010100000 I3 b00000000000000000000000010101011000000000000000000000000001000000000000000000000000000010000000000000000111000010000 O6 b111100010110110101110001101001100010100000 y7 -b0000 +8 +b11 +8 +b1000 ;8 b0000 K8 -b0000 S8 0!; 0Y; 0a; @@ -11392,12 +11401,11 @@ b1100000000000011110000000000000000000000000000000000000000000000000000000000000 b0100000010000000000000000000010101000000100010001000100010001000100010001000100010001000100010001000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010001000100010001000100010001000000000000000000000100000000000011110000000000000000000000000000000000111111111111101 Y)! 1{*! b0100000000000000000000000000000000001111111100000000000000000000000000000000 5+! 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fY{%C}h*iva4bw1_Ue4i`*Wf`B{gQ`4$^Hwk CnZt+x diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp index 4fea8930..c9f4e09f 100644 --- a/hw/unit_tests/cache/testbench.cpp +++ b/hw/unit_tests/cache/testbench.cpp @@ -20,9 +20,9 @@ int main(int argc, char **argv) cachesim.set_core_req(); for (int i = 0; i < 100; ++i){ - /*if(i == 1){ + if(i == 1){ cachesim.clear_req(); - }*/ + } cachesim.step(); cachesim.get_core_rsp(); } @@ -30,11 +30,11 @@ int main(int argc, char **argv) // read block cachesim.set_core_req2(); for (int i = 0; i < 100; ++i){ - /*if(i == 1){ + if(i == 1){ //read block from cache cachesim.clear_req(); - }*/ + } cachesim.step(); cachesim.get_core_rsp(); } diff --git a/hw/unit_tests/cache/trace.vcd b/hw/unit_tests/cache/trace.vcd index 88157959..2b1cba44 100644 --- a/hw/unit_tests/cache/trace.vcd +++ b/hw/unit_tests/cache/trace.vcd @@ -1,5 +1,5 @@ $version Generated by VerilatedVcd $end -$date Mon Jul 13 23:50:00 2020 +$date Mon Jul 13 23:53:11 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z*nZAb;(uE7O*u`tvqk?T1IVLkKj!g8;ag_02Ze9rhG+2Cg>R)VwoLdNdKt^`(JucV zP5IN!VlAfp-NQGy{R~&i&+*vW%$WCd$Xiw)K8_-;cK^hF^ftYfaTJ~umbB>3^tbHt U^Z2Im*YTGf(6NcihlkDoe~#RoMF0Q* literal 0 HcmV?d00001 diff --git a/hw/unit_tests/cache/ram.h b/hw/unit_tests/cache/ram.h new file mode 100644 index 00000000..53df7e0f --- /dev/null +++ b/hw/unit_tests/cache/ram.h @@ -0,0 +1,64 @@ +#pragma once + +#include +#include + +class RAM { +private: + + mutable uint8_t *mem_[(1 << 12)]; + + uint8_t *get(uint32_t address) const { + uint32_t block_addr = address >> 20; + uint32_t block_offset = address & 0x000FFFFF; + if (mem_[block_addr] == NULL) { + mem_[block_addr] = new uint8_t[(1 << 20)]; + } + return mem_[block_addr] + block_offset; + } + +public: + + RAM() { + for (uint32_t i = 0; i < (1 << 12); i++) { + mem_[i] = NULL; + } + } + + ~RAM() { + this->clear(); + } + + size_t size() const { + return (1ull << 32); + } + + void clear() { + for (uint32_t i = 0; i < (1 << 12); i++) { + if (mem_[i]) { + delete mem_[i]; + mem_[i] = NULL; + } + } + } + + void read(uint32_t address, uint32_t length, uint8_t *data) const { + for (unsigned i = 0; i < length; i++) { + data[i] = *this->get(address + i); + } + } + + void write(uint32_t address, uint32_t length, const uint8_t *data) { + for (unsigned i = 0; i < length; i++) { + *this->get(address + i) = data[i]; + } + } + + uint8_t& operator[](uint32_t address) { + return *get(address); + } + + const uint8_t& operator[](uint32_t address) const { + return *get(address); + } +}; \ No newline at end of file diff --git a/hw/unit_tests/cache/simulator.cpp b/hw/unit_tests/cache/simulator.cpp deleted file mode 100644 index 95af8d4f..00000000 --- a/hw/unit_tests/cache/simulator.cpp +++ /dev/null @@ -1,83 +0,0 @@ -#include "simulator.h" -#include -#include -#include - -uint64_t timestamp = 0; - -double sc_time_stamp() { - return timestamp; -} - -Simulator::Simulator() { - // force random values for unitialized signals - Verilated::randReset(1); - - vortex_ = new VVX_priority_encoder(); - -#ifdef VCD_OUTPUT - Verilated::traceEverOn(true); - trace_ = new VerilatedVcdC; - vortex_->trace(trace_, 99); - trace_->open("trace.vcd"); -#endif -} - -Simulator::~Simulator() { -#ifdef VCD_OUTPUT - trace_->close(); -#endif - delete vortex_; -} - - - -void Simulator::step() { - this->eval(); - - this->eval(); -} - - -void Simulator::reset() { -#ifndef NDEBUG - std::cout << timestamp << ": [sim] reset()" << std::endl; -#endif - - this->step(); -} - - -void Simulator::eval() { - vortex_->eval(); -#ifdef VCD_OUTPUT - trace_->dump(timestamp); -#endif - ++timestamp; -} - -void Simulator::wait(uint32_t cycles) { - for (int i = 0; i < cycles; ++i) { - this->step(); - } -} - - - -bool Simulator::run() { - // reset the device - this->reset(); - - // execute program - this->step(); - - - // wait 5 cycles to flush the pipeline - this->wait(5); - - - - return 0; -} - - diff --git a/hw/unit_tests/cache/simulator.h b/hw/unit_tests/cache/simulator.h deleted file mode 100644 index 7aa0f0aa..00000000 --- a/hw/unit_tests/cache/simulator.h +++ /dev/null @@ -1,52 +0,0 @@ -#pragma once - -#include "VVX_priority_encoder.h" -#include "VVX_priority_encoder__Syms.h" -#include "verilated.h" - -#ifdef VCD_OUTPUT -#include -#endif - -//#include - -#include -#include - -class Simulator { -public: - - Simulator(); - virtual ~Simulator(); - - void load_bin(const char* program_file); - void load_ihex(const char* program_file); - - bool is_busy(); - - void reset(); - void step(); - void wait(uint32_t cycles); - void flush_caches(uint32_t mem_addr, uint32_t size); - - - bool run(); - void print_stats(std::ostream& out); - -private: - - void eval(); - - void eval_dram_bus(); - void eval_io_bus(); - void eval_snp_bus(); - - uint32_t snp_req_active_; - uint32_t snp_req_size_; - uint32_t pending_snp_reqs_; - - VVX_priority_encoder *vortex_; -#ifdef VCD_OUTPUT - VerilatedVcdC *trace_; -#endif -}; diff --git a/hw/unit_tests/cache/testbase.cpp b/hw/unit_tests/cache/testbase.cpp deleted file mode 100644 index e0c826c4..00000000 --- a/hw/unit_tests/cache/testbase.cpp +++ /dev/null @@ -1,59 +0,0 @@ -#include "VVX_generic_queue.h" -#include "VVX_generic_queue__Syms.h" -#include "verilated.h" - -#include - -#include -#include - -uint64_t timestamp = 0; - -double sc_time_stamp() { - return timestamp; -} - -int main(int argc, char **argv){ - Verilated::commandArgs(argc, argv); //passes the command args to the object - - VVX_generic_queue *tb = new VVX_generic_queue; - tb->reset = 1; - tb->eval(); - tb->reset = 0; - unsigned int clk; - bool full; - bool empty; - int size; - int data_out; - tb->data_in = 0xff; - - tb->push = 1; - - for (int i = 0; i < 5; ++i){ - //toggle the clock - tb->eval(); - tb->clk = 1; - - tb->eval(); - tb->clk = 0; - tb->eval(); - - - full = tb->full; - empty = tb->empty; - size = tb->size; - data_out = tb->data_out; - clk = tb->clk; - - std::cout << "clk: " << clk << std::endl; - std::cout << "data_out: " << data_out << std::endl; - std::cout << "empty: " << empty << std::endl; - std::cout << "full: " << full << std::endl; - std::cout << "size: " << size << std::endl; - - } - - delete tb; - - exit(0); -} diff --git a/hw/unit_tests/cache/testbench.cpp b/hw/unit_tests/cache/testbench.cpp index 8f8978b3..4fea8930 100644 --- a/hw/unit_tests/cache/testbench.cpp +++ b/hw/unit_tests/cache/testbench.cpp @@ -1,12 +1,53 @@ -#include "simulator.h" +#include "cachesim.h" #include #include #include +#define VCD_OUTPUT 1 + int main(int argc, char **argv) { - Simulator simulator; - bool curr = simulator.run(); + //init + RAM ram; + CacheSim cachesim; + cachesim.attach_ram(&ram); + + + // reset the device + cachesim.reset(); + //write block to cache + cachesim.set_core_req(); + + for (int i = 0; i < 100; ++i){ + /*if(i == 1){ + cachesim.clear_req(); + }*/ + cachesim.step(); + cachesim.get_core_rsp(); + } + + // read block + cachesim.set_core_req2(); + for (int i = 0; i < 100; ++i){ + /*if(i == 1){ + //read block from cache + cachesim.clear_req(); + + }*/ + cachesim.step(); + cachesim.get_core_rsp(); + } + + /* + core_req_t *write; + write->valid = 1; + //write.tag = 0xff; //TODO: make a reasonable tag + //write.addr[0] = 0x11111111; + //write.addr[1] = 0x22222222; + //write.addr[2] = 0x33333333; + //write.addr[3] = 0x44444444; + //write. + */ return 0; -} \ No newline at end of file +} diff --git a/hw/unit_tests/cache/trace.vcd b/hw/unit_tests/cache/trace.vcd new file mode 100644 index 00000000..68a042c1 --- /dev/null +++ b/hw/unit_tests/cache/trace.vcd @@ -0,0 +1,20707 @@ +$version Generated by VerilatedVcd $end +$date Mon Jul 13 23:47:52 2020 + $end +$timescale 1ns $end + + $scope module TOP $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 Cl" snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module VX_cache $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 1o" DRAM_TAG_WIDTH [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 9o" NUM_SNP_REQUESTS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 wn" SNP_FWD_TAG_WIDTH [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 4 Y+ per_bank_core_req_ready [3:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 -- per_bank_dram_fill_rsp_ready [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 4 1/ per_bank_snp_req_ready [3:0] $end + $var wire 4 ; per_bank_snp_rsp_ready [3:0] $end + $var wire 112 A/ per_bank_snp_rsp_tag [111:0] $end + $var wire 4 9/ per_bank_snp_rsp_valid [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 28 +l" snp_req_addr_qual [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 3l" snp_req_invalidate_qual $end + $var wire 1 Cl" snp_req_ready $end + $var wire 1 Mm" snp_req_ready_qual $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 28 ;l" snp_req_tag_qual [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 #l" snp_req_valid_qual $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module cache_core_req_bank_sel $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 32 Ao" i [31:0] $end + $var wire 4 Y+ per_bank_ready [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $scope module genblk2 $end + $var wire 4 e! per_bank_ready_sel [3:0] $end + $upscope $end + $upscope $end + $scope module cache_core_rsp_merge $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 Y7 core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 y7 core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 1 ;8 grant_valid $end + $var wire 32 Ao" i [31:0] $end + $var wire 2 38 main_bank_index [1:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 +8 per_bank_core_rsp_pop_unqual [3:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 1 [h" reset $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 38 grant_index [1:0] $end + $var wire 4 C8 grant_onehot [3:0] $end + $var wire 1 ;8 grant_valid $end + $var wire 4 a+ requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 C8 grant_onehot_r [3:0] $end + $var wire 4 S8 late_value [3:0] $end + $var wire 1 [2! refill $end + $var wire 4 c2! refill_original [3:0] $end + $var wire 4 a+ refill_value [3:0] $end + $var wire 4 S2! requests_use [3:0] $end + $var wire 4 K8 update_value [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 S2! data_in [3:0] $end + $var wire 2 38 data_out [1:0] $end + $var wire 32 [8 i [31:0] $end + $var wire 1 ;8 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cache_dram_req_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 1 Wj" dram_req_valid $end + $var wire 2 s4 dwb_bank [1:0] $end + $var wire 1 K4 dwb_valid $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $scope module dram_fill_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 u/! o_empty $end + $var wire 1 /6 out_empty $end + $var wire 112 =5 out_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 55 out_per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 1 /* pop_qual $end + $var wire 1 76 push_qual $end + $var wire 112 e5 qual_bank_dram_fill_req_addr [111:0] $end + $var wire 1 G6 qual_has_request $end + $var wire 2 ?6 qual_request_index [1:0] $end + $var wire 1 [h" reset $end + $var wire 4 '6 updated_bank_dram_fill_req_valid [3:0] $end + $var wire 1 }/! use_empty $end + $var wire 112 U/! use_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 M/! use_per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 ]5 use_per_bqual_bank_dram_fill_req_valid [3:0] $end + $scope module dfqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Qo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 116 O6 data_in [115:0] $end + $var wire 116 o6 data_out [115:0] $end + $var wire 1 u/! empty $end + $var wire 1 {.! full $end + $var wire 1 /* pop $end + $var wire 1 76 push $end + $var wire 1 u! reading $end + $var wire 1 [h" reset $end + $var wire 3 '0! size [2:0] $end + $var wire 3 '0! size_r [2:0] $end + $var wire 1 17 writing $end + $scope module genblk3 $end + $var wire 116 /0! data(0) [115:0] $end + $var wire 116 30! data(1) [115:0] $end + $var wire 116 70! data(2) [115:0] $end + $var wire 116 ;0! data(3) [115:0] $end + $scope module genblk2 $end + $var wire 1 K2! bypass_r $end + $var wire 116 q1! curr_r [115:0] $end + $var wire 1 u/! empty_r $end + $var wire 1 {.! full_r $end + $var wire 116 Q1! head_r [115:0] $end + $var wire 2 C2! rd_ptr_next_r [1:0] $end + $var wire 2 ;2! rd_ptr_r [1:0] $end + $var wire 2 32! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 ?6 grant_index [1:0] $end + $var wire 4 97 grant_onehot [3:0] $end + $var wire 1 G6 grant_valid $end + $var wire 4 ]5 requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 97 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 ]5 data_in [3:0] $end + $var wire 2 ?6 data_out [1:0] $end + $var wire 32 A7 i [31:0] $end + $var wire 1 G6 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module prfqq $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 5/! current_addr [27:0] $end + $var wire 1 =/! current_empty $end + $var wire 1 -/! current_full $end + $var wire 1 -/! current_valid $end + $var wire 1 Gn" dram_req $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $var wire 1 {4 update_use $end + $var wire 28 s.! use_addr [27:0] $end + $var wire 2 %/! use_valid [1:0] $end + $scope module pfq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 1o" DATAW [31:0] $end + $var wire 32 wn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 oj" data_in [27:0] $end + $var wire 28 5/! data_out [27:0] $end + $var wire 1 =/! empty $end + $var wire 1 -/! full $end + $var wire 1 {4 pop $end + $var wire 1 On" push $end + $var wire 1 %5 reading $end + $var wire 1 [h" reset $end + $var wire 1 E/! size [0:0] $end + $var wire 1 E/! size_r [0:0] $end + $var wire 1 -5 writing $end + $scope module genblk2 $end + $var wire 28 5/! head_r [27:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_dwb $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 s4 grant_index [1:0] $end + $var wire 4 I7 grant_onehot [3:0] $end + $var wire 1 K4 grant_valid $end + $var wire 4 5- requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 I7 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 5- data_in [3:0] $end + $var wire 2 s4 data_out [1:0] $end + $var wire 32 Q7 i [31:0] $end + $var wire 1 K4 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(0) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 Q-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 C curr_bank_core_req_valid [3:0] $end + $var wire 32 i/ curr_bank_core_rsp_data [31:0] $end + $var wire 1 K curr_bank_core_rsp_ready $end + $var wire 42 q/ curr_bank_core_rsp_tag [41:0] $end + $var wire 2 a/ curr_bank_core_rsp_tid [1:0] $end + $var wire 1 1-! curr_bank_core_rsp_valid $end + $var wire 26 A-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 #0 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 9-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 Um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 ;0 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 30 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 C0 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 S curr_bank_dram_wb_req_ready $end + $var wire 1 +0 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 I-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 em" curr_bank_snp_req_valid $end + $var wire 1 [ curr_bank_snp_rsp_ready $end + $var wire 28 k0 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 c0 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 == addr_st1(0) [25:0] $end + $var wire 26 ;@ addr_st1e [25:0] $end + $var wire 26 A-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 Q-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 C core_req_valid [3:0] $end + $var wire 32 i/ core_rsp_data [31:0] $end + $var wire 1 K core_rsp_ready $end + $var wire 42 q/ core_rsp_tag [41:0] $end + $var wire 2 a/ core_rsp_tid [1:0] $end + $var wire 1 1-! core_rsp_valid $end + $var wire 32 )5! cwbq_data [31:0] $end + $var wire 1 [6! cwbq_empty $end + $var wire 1 c6! cwbq_full $end + $var wire 1 ?* cwbq_pop $end + $var wire 1 {@ cwbq_push $end + $var wire 1 9; cwbq_push_stall $end + $var wire 1 %A cwbq_push_unqual $end + $var wire 42 G4! cwbq_tag [41:0] $end + $var wire 2 ?4! cwbq_tid [1:0] $end + $var wire 26 M9 dfpq_addr_st0 [25:0] $end + $var wire 1 {2! dfpq_empty $end + $var wire 128 U9 dfpq_filldata_st0 [127:0] $end + $var wire 1 %3! dfpq_full $end + $var wire 1 E9 dfpq_pop $end + $var wire 1 q; dfpq_pop_unqual $end + $var wire 1 w> dirty_st1e $end + $var wire 1 Y5! dirty_st2 $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 16 a5! dirtyb_st2 [15:0] $end + $var wire 26 A-! dram_fill_req_addr [25:0] $end + $var wire 1 c@ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 I; dram_fill_req_stall $end + $var wire 1 -A dram_fill_req_unqual $end + $var wire 1 #0 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 9-! dram_fill_rsp_ready $end + $var wire 1 Um" dram_fill_rsp_valid $end + $var wire 26 ;0 dram_wb_req_addr [25:0] $end + $var wire 16 30 dram_wb_req_byteen [15:0] $end + $var wire 128 C0 dram_wb_req_data [127:0] $end + $var wire 1 }! dram_wb_req_fire $end + $var wire 1 S dram_wb_req_ready $end + $var wire 1 +0 dram_wb_req_valid $end + $var wire 1 -7! dwbq_dual_valid_sel $end + $var wire 1 k6! dwbq_empty $end + $var wire 1 s6! dwbq_full $end + $var wire 1 =A dwbq_is_dwb_in $end + $var wire 1 MA dwbq_is_dwb_out $end + $var wire 1 EA dwbq_is_snp_in $end + $var wire 1 UA dwbq_is_snp_out $end + $var wire 1 G* dwbq_pop $end + $var wire 1 5A dwbq_push $end + $var wire 1 A; dwbq_push_stall $end + $var wire 1 ]A dwbq_push_unqual $end + $var wire 26 {6! dwbq_req_addr [25:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 #6! fill_saw_dirty_st2 $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 i; going_to_write_st1(0) $end + $var wire 49 U= inst_meta_st1(0) [48:0] $end + $var wire 49 i5! inst_meta_st2 [48:0] $end + $var wire 1 Y; is_fill_in_pipe $end + $var wire 1 a; is_fill_st1(0) $end + $var wire 1 g4! is_fill_st2 $end + $var wire 1 7> is_mrvq_st1(0) $end + $var wire 1 +@ is_mrvq_st1e $end + $var wire 1 +@ is_mrvq_st1e_st2 $end + $var wire 1 C6! is_mrvq_st2 $end + $var wire 1 '> is_snp_st1(0) $end + $var wire 1 Y? is_snp_st1e $end + $var wire 1 +6! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 1 y? miss_add_because_miss $end + $var wire 1 ;6! miss_add_because_pending $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 s@ miss_add_is_mrvq $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 1 c@ miss_add_unqual $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 1 o> miss_st1e $end + $var wire 1 Q5! miss_st2 $end + $var wire 26 ]3! mrvq_addr_st0 [25:0] $end + $var wire 4 '4! mrvq_byteen_st0 [3:0] $end + $var wire 1 E3! mrvq_full $end + $var wire 1 S@ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 [@ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 1 K@ mrvq_init_ready_state_st2 $end + $var wire 1 S6! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 /4! mrvq_is_snp_st0 $end + $var wire 1 o: mrvq_pending_hazard_st1e $end + $var wire 1 W: mrvq_pop $end + $var wire 1 _: mrvq_pop_unqual $end + $var wire 1 1; mrvq_push_stall $end + $var wire 1 3@ mrvq_recover_ready_state_st1e $end + $var wire 1 K6! mrvq_recover_ready_state_st2 $end + $var wire 1 g: mrvq_rw_st0 $end + $var wire 1 74! mrvq_snp_invalidate_st0 $end + $var wire 1 M3! mrvq_stop $end + $var wire 42 u3! mrvq_tag_st0 [41:0] $end + $var wire 2 U3! mrvq_tid_st0 [1:0] $end + $var wire 1 _: mrvq_valid_st0 $end + $var wire 32 m3! mrvq_writeword_st0 [31:0] $end + $var wire 2 e3! mrvq_wsel_st0 [1:0] $end + $var wire 26 3< qual_addr_st0 [25:0] $end + $var wire 1 {< qual_going_to_write_st0 $end + $var wire 49 k< qual_inst_meta_st0 [48:0] $end + $var wire 1 q; qual_is_fill_st0 $end + $var wire 1 _: qual_is_mrvq_st0 $end + $var wire 1 %= qual_is_snp_st0 $end + $var wire 1 -= qual_snp_invalidate_st0 $end + $var wire 1 +< qual_valid_st0 $end + $var wire 1 C@ qual_valid_st1e_2 $end + $var wire 128 K< qual_writedata_st0 [127:0] $end + $var wire 32 C< qual_writeword_st0 [31:0] $end + $var wire 2 ;< qual_wsel_st0 [1:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 128 15! readdata_st2 [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 20 y5! readtag_st2 [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 32 )5! readword_st2 [31:0] $end + $var wire 1 ); recover_mrvq_state_st2 $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 y; reqq_pop_unqual $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 /> snp_invalidate_st1(0) $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 36! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 I-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 em" snp_req_valid $end + $var wire 1 '" snp_rsp_fire $end + $var wire 1 [ snp_rsp_ready $end + $var wire 28 k0 snp_rsp_tag [27:0] $end + $var wire 1 c0 snp_rsp_valid $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 ;6! snp_to_mrvq_st2 $end + $var wire 26 -9 snrq_addr_st0 [25:0] $end + $var wire 1 k2! snrq_empty $end + $var wire 1 s2! snrq_full $end + $var wire 1 59 snrq_invalidate_st0 $end + $var wire 1 %9 snrq_pop $end + $var wire 1 #< snrq_pop_unqual $end + $var wire 28 =9 snrq_tag_st0 [27:0] $end + $var wire 28 %7! snrq_tag_st2 [27:0] $end + $var wire 1 w: st2_pending_hazard_st1e $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 42 )? tag_st1e [41:0] $end + $var wire 2 9? tid_st1e [1:0] $end + $var wire 1 5= valid_st1(0) $end + $var wire 1 #@ valid_st1e $end + $var wire 1 o4! valid_st2 $end + $var wire 128 e= writedata_st1(0) [127:0] $end + $var wire 32 M= writeword_st1(0) [31:0] $end + $var wire 32 !5! writeword_st2 [31:0] $end + $var wire 2 E= wsel_st1(0) [1:0] $end + $var wire 2 w4! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 'P! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 AQ! dequeue_index [3:0] $end + $var wire 1 _: dequeue_possible $end + $var wire 4 QQ! enqueue_index [3:0] $end + $var wire 1 aQ! enqueue_possible $end + $var wire 26 ;@ fill_addr_st1 [25:0] $end + $var wire 4 IQ! head_ptr [3:0] $end + $var wire 1 IK increment_head $end + $var wire 1 eE is_fill_st1 $end + $var wire 1 s@ is_mrvq $end + $var wire 16 wJ make_ready [15:0] $end + $var wire 16 !K make_ready_push [15:0] $end + $var wire 85 }K! metadata_table(0) [84:0] $end + $var wire 85 "L! metadata_table(1) [84:0] $end + $var wire 85 =L! metadata_table(10) [84:0] $end + $var wire 85 @L! metadata_table(11) [84:0] $end + $var wire 85 CL! metadata_table(12) [84:0] $end + $var wire 85 FL! metadata_table(13) [84:0] $end + $var wire 85 IL! metadata_table(14) [84:0] $end + $var wire 85 LL! metadata_table(15) [84:0] $end + $var wire 85 %L! metadata_table(2) [84:0] $end + $var wire 85 (L! metadata_table(3) [84:0] $end + $var wire 85 +L! metadata_table(4) [84:0] $end + $var wire 85 .L! metadata_table(5) [84:0] $end + $var wire 85 1L! metadata_table(6) [84:0] $end + $var wire 85 4L! metadata_table(7) [84:0] $end + $var wire 85 7L! metadata_table(8) [84:0] $end + $var wire 85 :L! metadata_table(9) [84:0] $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 26 ]3! miss_resrv_addr_st0 [25:0] $end + $var wire 4 '4! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 m3! miss_resrv_data_st0 [31:0] $end + $var wire 1 E3! miss_resrv_full $end + $var wire 1 /4! miss_resrv_is_snp_st0 $end + $var wire 1 W: miss_resrv_pop $end + $var wire 1 g: miss_resrv_rw_st0 $end + $var wire 1 74! miss_resrv_snp_invalidate_st0 $end + $var wire 1 M3! miss_resrv_stop $end + $var wire 42 u3! miss_resrv_tag_st0 [41:0] $end + $var wire 2 U3! miss_resrv_tid_st0 [1:0] $end + $var wire 1 _: miss_resrv_valid_st0 $end + $var wire 2 e3! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 K@ mrvq_init_ready_state $end + $var wire 1 9K mrvq_pop $end + $var wire 1 1K mrvq_push $end + $var wire 1 o: pending_hazard $end + $var wire 1 YK qual_mrvq_init $end + $var wire 16 9Q! ready_table [15:0] $end + $var wire 1 AK recover_state $end + $var wire 1 [h" reset $end + $var wire 4 AQ! schedule_ptr [3:0] $end + $var wire 5 YQ! size [4:0] $end + $var wire 4 QQ! tail_ptr [3:0] $end + $var wire 1 QK update_ready $end + $var wire 16 )K valid_address_match [15:0] $end + $var wire 16 1Q! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 C bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 eC! o_empty $end + $var wire 1 YC out_empty $end + $var wire 120 gB out_per_addr [119:0] $end + $var wire 16 _B out_per_byteen [15:0] $end + $var wire 4 WB out_per_rw [3:0] $end + $var wire 42 IC out_per_tag [41:0] $end + $var wire 4 OB out_per_valids [3:0] $end + $var wire 128 )C out_per_writedata [127:0] $end + $var wire 1 aC pop_qual $end + $var wire 1 O* push_qual $end + $var wire 120 %C! qual_addr [119:0] $end + $var wire 16 {B! qual_byteen [15:0] $end + $var wire 1 ': qual_has_request $end + $var wire 2 /: qual_request_index [1:0] $end + $var wire 4 sB! qual_rw [3:0] $end + $var wire 42 53! qual_tag [41:0] $end + $var wire 4 kB! qual_valids [3:0] $end + $var wire 128 EC! qual_writedata [127:0] $end + $var wire 4 iC real_out_per_valids [3:0] $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 mC! use_empty $end + $var wire 120 %C! use_per_addr [119:0] $end + $var wire 16 {B! use_per_byteen [15:0] $end + $var wire 4 sB! use_per_rw [3:0] $end + $var wire 42 53! use_per_tag [41:0] $end + $var wire 4 kB! use_per_valids [3:0] $end + $var wire 128 EC! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 w" data_in [313:0] $end + $var wire 314 qC data_out [313:0] $end + $var wire 1 eC! empty $end + $var wire 1 -3! full $end + $var wire 1 aC pop $end + $var wire 1 O* push $end + $var wire 1 cD reading $end + $var wire 1 [h" reset $end + $var wire 3 uC! size [2:0] $end + $var wire 3 uC! size_r [2:0] $end + $var wire 1 i# writing $end + $scope module genblk3 $end + $var wire 314 }C! data(0) [313:0] $end + $var wire 314 )D! data(1) [313:0] $end + $var wire 314 3D! data(2) [313:0] $end + $var wire 314 =D! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 AI! bypass_r $end + $var wire 314 7H! curr_r [313:0] $end + $var wire 1 eC! empty_r $end + $var wire 1 -3! full_r $end + $var wire 314 EG! head_r [313:0] $end + $var wire 2 9I! rd_ptr_next_r [1:0] $end + $var wire 2 1I! rd_ptr_r [1:0] $end + $var wire 2 )I! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 /: grant_index [1:0] $end + $var wire 4 kD grant_onehot [3:0] $end + $var wire 1 ': grant_valid $end + $var wire 4 kB! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 kD grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 kB! data_in [3:0] $end + $var wire 2 /: data_out [1:0] $end + $var wire 32 sD i [31:0] $end + $var wire 1 ': valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 aK data_in [75:0] $end + $var wire 76 yK data_out [75:0] $end + $var wire 1 [6! empty $end + $var wire 1 c6! full $end + $var wire 1 ?* pop $end + $var wire 1 {@ push $end + $var wire 1 q# reading $end + $var wire 1 [h" reset $end + $var wire 3 iQ! size [2:0] $end + $var wire 3 iQ! size_r [2:0] $end + $var wire 1 3L writing $end + $scope module genblk3 $end + $var wire 76 qQ! data(0) [75:0] $end + $var wire 76 tQ! data(1) [75:0] $end + $var wire 76 wQ! data(2) [75:0] $end + $var wire 76 zQ! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 ]S! bypass_r $end + $var wire 76 -S! curr_r [75:0] $end + $var wire 1 [6! empty_r $end + $var wire 1 c6! full_r $end + $var wire 76 sR! head_r [75:0] $end + $var wire 2 US! rd_ptr_next_r [1:0] $end + $var wire 2 MS! rd_ptr_r [1:0] $end + $var wire 2 ES! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 G" data_in [153:0] $end + $var wire 154 }A data_out [153:0] $end + $var wire 1 {2! empty $end + $var wire 1 %3! full $end + $var wire 1 E9 pop $end + $var wire 1 Um" push $end + $var wire 1 GB reading $end + $var wire 1 [h" reset $end + $var wire 5 c:! size [4:0] $end + $var wire 5 c:! size_r [4:0] $end + $var wire 1 o" writing $end + $scope module genblk3 $end + $var wire 154 k:! data(0) [153:0] $end + $var wire 154 p:! data(1) [153:0] $end + $var wire 154 ?;! data(10) [153:0] $end + $var wire 154 D;! data(11) [153:0] $end + $var wire 154 I;! data(12) [153:0] $end + $var wire 154 N;! data(13) [153:0] $end + $var wire 154 S;! data(14) [153:0] $end + $var wire 154 X;! data(15) [153:0] $end + $var wire 154 u:! data(2) [153:0] $end + $var wire 154 z:! data(3) [153:0] $end + $var wire 154 !;! data(4) [153:0] $end + $var wire 154 &;! data(5) [153:0] $end + $var wire 154 +;! data(6) [153:0] $end + $var wire 154 0;! data(7) [153:0] $end + $var wire 154 5;! data(8) [153:0] $end + $var wire 154 :;! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 cB! bypass_r $end + $var wire 154 #B! curr_r [153:0] $end + $var wire 1 {2! empty_r $end + $var wire 1 %3! full_r $end + $var wire 154 YA! head_r [153:0] $end + $var wire 4 [B! rd_ptr_next_r [3:0] $end + $var wire 4 SB! rd_ptr_r [3:0] $end + $var wire 4 KB! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 ;L data_in [199:0] $end + $var wire 200 sL data_out [199:0] $end + $var wire 1 k6! empty $end + $var wire 1 s6! full $end + $var wire 1 G* pop $end + $var wire 1 5A push $end + $var wire 1 y# reading $end + $var wire 1 [h" reset $end + $var wire 3 eS! size [2:0] $end + $var wire 3 eS! size_r [2:0] $end + $var wire 1 MM writing $end + $scope module genblk3 $end + $var wire 200 mS! data(0) [199:0] $end + $var wire 200 tS! data(1) [199:0] $end + $var wire 200 {S! data(2) [199:0] $end + $var wire 200 $T! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 ]W! bypass_r $end + $var wire 200 kV! curr_r [199:0] $end + $var wire 1 k6! empty_r $end + $var wire 1 s6! full_r $end + $var wire 200 3V! head_r [199:0] $end + $var wire 2 UW! rd_ptr_next_r [1:0] $end + $var wire 2 MW! rd_ptr_r [1:0] $end + $var wire 2 EW! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 {D in [242:0] $end + $var wire 243 II! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 243 II! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 /" data_in [54:0] $end + $var wire 55 eA data_out [54:0] $end + $var wire 1 k2! empty $end + $var wire 1 s2! full $end + $var wire 1 %9 pop $end + $var wire 1 em" push $end + $var wire 1 uA reading $end + $var wire 1 [h" reset $end + $var wire 5 57! size [4:0] $end + $var wire 5 57! size_r [4:0] $end + $var wire 1 ?" writing $end + $scope module genblk3 $end + $var wire 55 =7! data(0) [54:0] $end + $var wire 55 ?7! data(1) [54:0] $end + $var wire 55 Q7! data(10) [54:0] $end + $var wire 55 S7! data(11) [54:0] $end + $var wire 55 U7! data(12) [54:0] $end + $var wire 55 W7! data(13) [54:0] $end + $var wire 55 Y7! data(14) [54:0] $end + $var wire 55 [7! data(15) [54:0] $end + $var wire 55 A7! data(2) [54:0] $end + $var wire 55 C7! data(3) [54:0] $end + $var wire 55 E7! data(4) [54:0] $end + $var wire 55 G7! data(5) [54:0] $end + $var wire 55 I7! data(6) [54:0] $end + $var wire 55 K7! data(7) [54:0] $end + $var wire 55 M7! data(8) [54:0] $end + $var wire 55 O7! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 [:! bypass_r $end + $var wire 55 3:! curr_r [54:0] $end + $var wire 1 k2! empty_r $end + $var wire 1 s2! full_r $end + $var wire 55 #:! head_r [54:0] $end + $var wire 4 S:! rd_ptr_next_r [3:0] $end + $var wire 4 K:! rd_ptr_r [3:0] $end + $var wire 4 C:! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 'J in [315:0] $end + $var wire 316 -K! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 316 -K! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 yG data_write [127:0] $end + $var wire 1 w> dirty_st1e $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 o> fill_sent $end + $var wire 1 %I force_core_miss $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 ;H invalidate_line $end + $var wire 1 Y? is_snp_st1e $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 o> miss_st1e $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 128 AG qual_read_data_st1 [127:0] $end + $var wire 1 )G qual_read_dirty_st1 $end + $var wire 16 1G qual_read_dirtyb_st1 [15:0] $end + $var wire 20 9G qual_read_tag_st1 [19:0] $end + $var wire 1 !G qual_read_valid_st1 $end + $var wire 128 _F read_data_st1c(0) [127:0] $end + $var wire 1 GF read_dirty_st1c(0) $end + $var wire 16 OF read_dirtyb_st1c(0) [15:0] $end + $var wire 20 WF read_tag_st1c(0) [19:0] $end + $var wire 1 ?F read_valid_st1c(0) $end + $var wire 6 ]E readaddr_st10 [5:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 1 {H real_miss $end + $var wire 1 KH real_writefill $end + $var wire 1 kH req_invalid $end + $var wire 1 sH req_miss $end + $var wire 1 [h" reset $end + $var wire 1 cH should_write $end + $var wire 1 ;H snoop_hit_no_pending $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 Q; stall $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 1 CH tags_match $end + $var wire 128 G> use_read_data_st1e [127:0] $end + $var wire 1 iG use_read_dirty_st1e $end + $var wire 16 !? use_read_dirtyb_st1e [15:0] $end + $var wire 20 g> use_read_tag_st1e [19:0] $end + $var wire 1 aG use_read_valid_st1e $end + $var wire 128 yG use_write_data [127:0] $end + $var wire 16 qG use_write_enable [15:0] $end + $var wire 1 #@ valid_req_st1e $end + $var wire 16 [H we [15:0] $end + $var wire 2 7F wordsel_st1e [1:0] $end + $var wire 26 ;@ writeaddr_st1e [25:0] $end + $var wire 128 uE writedata_st1e [127:0] $end + $var wire 1 eE writefill_st1e $end + $var wire 6 ]E writeladdr_st1e [5:0] $end + $var wire 20 SH writetag_st1e [19:0] $end + $var wire 32 mE writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 -I normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 5I normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 =I normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 EI normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 UI in [165:0] $end + $var wire 166 UI out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 166 [J! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 +J! dirty [63:0] $end + $var wire 1 MI do_write $end + $var wire 1 o> fill_sent $end + $var wire 32 KJ! i [31:0] $end + $var wire 1 ;H invalidate $end + $var wire 32 SJ! j [31:0] $end + $var wire 6 ]E read_addr [5:0] $end + $var wire 128 AG read_data [127:0] $end + $var wire 1 )G read_dirty $end + $var wire 16 1G read_dirtyb [15:0] $end + $var wire 20 9G read_tag [19:0] $end + $var wire 1 !G read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 20 SH tag_index [19:0] $end + $var wire 64 ;J! valid [63:0] $end + $var wire 6 ]E write_addr [5:0] $end + $var wire 128 yG write_data [127:0] $end + $var wire 16 qG write_enable [15:0] $end + $var wire 1 KH write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(1) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 y-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 c curr_bank_core_req_valid [3:0] $end + $var wire 32 {0 curr_bank_core_rsp_data [31:0] $end + $var wire 1 k curr_bank_core_rsp_ready $end + $var wire 42 %1 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 s0 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 Y-! curr_bank_core_rsp_valid $end + $var wire 26 i-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 51 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 a-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 M1 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 E1 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 U1 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 s curr_bank_dram_wb_req_ready $end + $var wire 1 =1 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 q-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 }m" curr_bank_snp_req_valid $end + $var wire 1 { curr_bank_snp_rsp_ready $end + $var wire 28 }1 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 u1 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 mQ addr_st1(0) [25:0] $end + $var wire 26 kT addr_st1e [25:0] $end + $var wire 26 i-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 y-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 c core_req_valid [3:0] $end + $var wire 32 {0 core_rsp_data [31:0] $end + $var wire 1 k core_rsp_ready $end + $var wire 42 %1 core_rsp_tag [41:0] $end + $var wire 2 s0 core_rsp_tid [1:0] $end + $var wire 1 Y-! core_rsp_valid $end + $var wire 32 #Z! cwbq_data [31:0] $end + $var wire 1 U[! cwbq_empty $end + $var wire 1 ][! cwbq_full $end + $var wire 1 _* cwbq_pop $end + $var wire 1 MU cwbq_push $end + $var wire 1 iO cwbq_push_stall $end + $var wire 1 UU cwbq_push_unqual $end + $var wire 42 AY! cwbq_tag [41:0] $end + $var wire 2 9Y! cwbq_tid [1:0] $end + $var wire 26 }M dfpq_addr_st0 [25:0] $end + $var wire 1 uW! dfpq_empty $end + $var wire 128 'N dfpq_filldata_st0 [127:0] $end + $var wire 1 }W! dfpq_full $end + $var wire 1 uM dfpq_pop $end + $var wire 1 CP dfpq_pop_unqual $end + $var wire 1 IS dirty_st1e $end + $var wire 1 SZ! dirty_st2 $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 16 [Z! dirtyb_st2 [15:0] $end + $var wire 26 i-! dram_fill_req_addr [25:0] $end + $var wire 1 5U dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 yO dram_fill_req_stall $end + $var wire 1 ]U dram_fill_req_unqual $end + $var wire 1 51 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 a-! dram_fill_rsp_ready $end + $var wire 1 um" dram_fill_rsp_valid $end + $var wire 26 M1 dram_wb_req_addr [25:0] $end + $var wire 16 E1 dram_wb_req_byteen [15:0] $end + $var wire 128 U1 dram_wb_req_data [127:0] $end + $var wire 1 #$ dram_wb_req_fire $end + $var wire 1 s dram_wb_req_ready $end + $var wire 1 =1 dram_wb_req_valid $end + $var wire 1 '\! dwbq_dual_valid_sel $end + $var wire 1 e[! dwbq_empty $end + $var wire 1 m[! dwbq_full $end + $var wire 1 mU dwbq_is_dwb_in $end + $var wire 1 }U dwbq_is_dwb_out $end + $var wire 1 uU dwbq_is_snp_in $end + $var wire 1 'V dwbq_is_snp_out $end + $var wire 1 g* dwbq_pop $end + $var wire 1 eU dwbq_push $end + $var wire 1 qO dwbq_push_stall $end + $var wire 1 /V dwbq_push_unqual $end + $var wire 26 u[! dwbq_req_addr [25:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 {Z! fill_saw_dirty_st2 $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 ;P going_to_write_st1(0) $end + $var wire 49 'R inst_meta_st1(0) [48:0] $end + $var wire 49 cZ! inst_meta_st2 [48:0] $end + $var wire 1 +P is_fill_in_pipe $end + $var wire 1 3P is_fill_st1(0) $end + $var wire 1 aY! is_fill_st2 $end + $var wire 1 gR is_mrvq_st1(0) $end + $var wire 1 [T is_mrvq_st1e $end + $var wire 1 [T is_mrvq_st1e_st2 $end + $var wire 1 =[! is_mrvq_st2 $end + $var wire 1 WR is_snp_st1(0) $end + $var wire 1 +T is_snp_st1e $end + $var wire 1 %[! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 1 KT miss_add_because_miss $end + $var wire 1 5[! miss_add_because_pending $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 EU miss_add_is_mrvq $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 1 5U miss_add_unqual $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 1 AS miss_st1e $end + $var wire 1 KZ! miss_st2 $end + $var wire 26 WX! mrvq_addr_st0 [25:0] $end + $var wire 4 !Y! mrvq_byteen_st0 [3:0] $end + $var wire 1 ?X! mrvq_full $end + $var wire 1 %U mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 -U mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 1 {T mrvq_init_ready_state_st2 $end + $var wire 1 M[! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 )Y! mrvq_is_snp_st0 $end + $var wire 1 AO mrvq_pending_hazard_st1e $end + $var wire 1 )O mrvq_pop $end + $var wire 1 1O mrvq_pop_unqual $end + $var wire 1 aO mrvq_push_stall $end + $var wire 1 cT mrvq_recover_ready_state_st1e $end + $var wire 1 E[! mrvq_recover_ready_state_st2 $end + $var wire 1 9O mrvq_rw_st0 $end + $var wire 1 1Y! mrvq_snp_invalidate_st0 $end + $var wire 1 GX! mrvq_stop $end + $var wire 42 oX! mrvq_tag_st0 [41:0] $end + $var wire 2 OX! mrvq_tid_st0 [1:0] $end + $var wire 1 1O mrvq_valid_st0 $end + $var wire 32 gX! mrvq_writeword_st0 [31:0] $end + $var wire 2 _X! mrvq_wsel_st0 [1:0] $end + $var wire 26 cP qual_addr_st0 [25:0] $end + $var wire 1 MQ qual_going_to_write_st0 $end + $var wire 49 =Q qual_inst_meta_st0 [48:0] $end + $var wire 1 CP qual_is_fill_st0 $end + $var wire 1 1O qual_is_mrvq_st0 $end + $var wire 1 UQ qual_is_snp_st0 $end + $var wire 1 ]Q qual_snp_invalidate_st0 $end + $var wire 1 [P qual_valid_st0 $end + $var wire 1 sT qual_valid_st1e_2 $end + $var wire 128 {P qual_writedata_st0 [127:0] $end + $var wire 32 sP qual_writeword_st0 [31:0] $end + $var wire 2 kP qual_wsel_st0 [1:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 128 +Z! readdata_st2 [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 20 sZ! readtag_st2 [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 32 #Z! readword_st2 [31:0] $end + $var wire 1 YO recover_mrvq_state_st2 $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 KP reqq_pop_unqual $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 _R snp_invalidate_st1(0) $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 -[! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 q-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 }m" snp_req_valid $end + $var wire 1 +$ snp_rsp_fire $end + $var wire 1 { snp_rsp_ready $end + $var wire 28 }1 snp_rsp_tag [27:0] $end + $var wire 1 u1 snp_rsp_valid $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 5[! snp_to_mrvq_st2 $end + $var wire 26 ]M snrq_addr_st0 [25:0] $end + $var wire 1 eW! snrq_empty $end + $var wire 1 mW! snrq_full $end + $var wire 1 eM snrq_invalidate_st0 $end + $var wire 1 UM snrq_pop $end + $var wire 1 SP snrq_pop_unqual $end + $var wire 28 mM snrq_tag_st0 [27:0] $end + $var wire 28 }[! snrq_tag_st2 [27:0] $end + $var wire 1 IO st2_pending_hazard_st1e $end + $var wire 1 #P stall_bank_pipe $end + $var wire 42 YS tag_st1e [41:0] $end + $var wire 2 iS tid_st1e [1:0] $end + $var wire 1 eQ valid_st1(0) $end + $var wire 1 ST valid_st1e $end + $var wire 1 iY! valid_st2 $end + $var wire 128 7R writedata_st1(0) [127:0] $end + $var wire 32 }Q writeword_st1(0) [31:0] $end + $var wire 32 yY! writeword_st2 [31:0] $end + $var wire 2 uQ wsel_st1(0) [1:0] $end + $var wire 2 qY! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 !u! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 ;v! dequeue_index [3:0] $end + $var wire 1 1O dequeue_possible $end + $var wire 4 Kv! enqueue_index [3:0] $end + $var wire 1 [v! enqueue_possible $end + $var wire 26 kT fill_addr_st1 [25:0] $end + $var wire 4 Cv! head_ptr [3:0] $end + $var wire 1 y_ increment_head $end + $var wire 1 7Z is_fill_st1 $end + $var wire 1 EU is_mrvq $end + $var wire 16 I_ make_ready [15:0] $end + $var wire 16 Q_ make_ready_push [15:0] $end + $var wire 85 wp! metadata_table(0) [84:0] $end + $var wire 85 zp! metadata_table(1) [84:0] $end + $var wire 85 7q! metadata_table(10) [84:0] $end + $var wire 85 :q! metadata_table(11) [84:0] $end + $var wire 85 =q! metadata_table(12) [84:0] $end + $var wire 85 @q! metadata_table(13) [84:0] $end + $var wire 85 Cq! metadata_table(14) [84:0] $end + $var wire 85 Fq! metadata_table(15) [84:0] $end + $var wire 85 }p! metadata_table(2) [84:0] $end + $var wire 85 "q! metadata_table(3) [84:0] $end + $var wire 85 %q! metadata_table(4) [84:0] $end + $var wire 85 (q! metadata_table(5) [84:0] $end + $var wire 85 +q! metadata_table(6) [84:0] $end + $var wire 85 .q! metadata_table(7) [84:0] $end + $var wire 85 1q! metadata_table(8) [84:0] $end + $var wire 85 4q! metadata_table(9) [84:0] $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 26 WX! miss_resrv_addr_st0 [25:0] $end + $var wire 4 !Y! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 gX! miss_resrv_data_st0 [31:0] $end + $var wire 1 ?X! miss_resrv_full $end + $var wire 1 )Y! miss_resrv_is_snp_st0 $end + $var wire 1 )O miss_resrv_pop $end + $var wire 1 9O miss_resrv_rw_st0 $end + $var wire 1 1Y! miss_resrv_snp_invalidate_st0 $end + $var wire 1 GX! miss_resrv_stop $end + $var wire 42 oX! miss_resrv_tag_st0 [41:0] $end + $var wire 2 OX! miss_resrv_tid_st0 [1:0] $end + $var wire 1 1O miss_resrv_valid_st0 $end + $var wire 2 _X! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 {T mrvq_init_ready_state $end + $var wire 1 i_ mrvq_pop $end + $var wire 1 a_ mrvq_push $end + $var wire 1 AO pending_hazard $end + $var wire 1 +` qual_mrvq_init $end + $var wire 16 3v! ready_table [15:0] $end + $var wire 1 q_ recover_state $end + $var wire 1 [h" reset $end + $var wire 4 ;v! schedule_ptr [3:0] $end + $var wire 5 Sv! size [4:0] $end + $var wire 4 Kv! tail_ptr [3:0] $end + $var wire 1 #` update_ready $end + $var wire 16 Y_ valid_address_match [15:0] $end + $var wire 16 +v! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 c bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 _h! o_empty $end + $var wire 1 +X out_empty $end + $var wire 120 9W out_per_addr [119:0] $end + $var wire 16 1W out_per_byteen [15:0] $end + $var wire 4 )W out_per_rw [3:0] $end + $var wire 42 yW out_per_tag [41:0] $end + $var wire 4 !W out_per_valids [3:0] $end + $var wire 128 YW out_per_writedata [127:0] $end + $var wire 1 3X pop_qual $end + $var wire 1 o* push_qual $end + $var wire 120 }g! qual_addr [119:0] $end + $var wire 16 ug! qual_byteen [15:0] $end + $var wire 1 WN qual_has_request $end + $var wire 2 _N qual_request_index [1:0] $end + $var wire 4 mg! qual_rw [3:0] $end + $var wire 42 /X! qual_tag [41:0] $end + $var wire 4 eg! qual_valids [3:0] $end + $var wire 128 ?h! qual_writedata [127:0] $end + $var wire 4 ;X real_out_per_valids [3:0] $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 gh! use_empty $end + $var wire 120 }g! use_per_addr [119:0] $end + $var wire 16 ug! use_per_byteen [15:0] $end + $var wire 4 mg! use_per_rw [3:0] $end + $var wire 42 /X! use_per_tag [41:0] $end + $var wire 4 eg! use_per_valids [3:0] $end + $var wire 128 ?h! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 {$ data_in [313:0] $end + $var wire 314 CX data_out [313:0] $end + $var wire 1 _h! empty $end + $var wire 1 'X! full $end + $var wire 1 3X pop $end + $var wire 1 o* push $end + $var wire 1 5Y reading $end + $var wire 1 [h" reset $end + $var wire 3 oh! size [2:0] $end + $var wire 3 oh! size_r [2:0] $end + $var wire 1 m% writing $end + $scope module genblk3 $end + $var wire 314 wh! data(0) [313:0] $end + $var wire 314 #i! data(1) [313:0] $end + $var wire 314 -i! data(2) [313:0] $end + $var wire 314 7i! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 ;n! bypass_r $end + $var wire 314 1m! curr_r [313:0] $end + $var wire 1 _h! empty_r $end + $var wire 1 'X! full_r $end + $var wire 314 ?l! head_r [313:0] $end + $var wire 2 3n! rd_ptr_next_r [1:0] $end + $var wire 2 +n! rd_ptr_r [1:0] $end + $var wire 2 #n! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 _N grant_index [1:0] $end + $var wire 4 =Y grant_onehot [3:0] $end + $var wire 1 WN grant_valid $end + $var wire 4 eg! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 =Y grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 eg! data_in [3:0] $end + $var wire 2 _N data_out [1:0] $end + $var wire 32 EY i [31:0] $end + $var wire 1 WN valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 3` data_in [75:0] $end + $var wire 76 K` data_out [75:0] $end + $var wire 1 U[! empty $end + $var wire 1 ][! full $end + $var wire 1 _* pop $end + $var wire 1 MU push $end + $var wire 1 u% reading $end + $var wire 1 [h" reset $end + $var wire 3 cv! size [2:0] $end + $var wire 3 cv! size_r [2:0] $end + $var wire 1 c` writing $end + $scope module genblk3 $end + $var wire 76 kv! data(0) [75:0] $end + $var wire 76 nv! data(1) [75:0] $end + $var wire 76 qv! data(2) [75:0] $end + $var wire 76 tv! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Wx! bypass_r $end + $var wire 76 'x! curr_r [75:0] $end + $var wire 1 U[! empty_r $end + $var wire 1 ][! full_r $end + $var wire 76 mw! head_r [75:0] $end + $var wire 2 Ox! rd_ptr_next_r [1:0] $end + $var wire 2 Gx! rd_ptr_r [1:0] $end + $var wire 2 ?x! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 K$ data_in [153:0] $end + $var wire 154 OV data_out [153:0] $end + $var wire 1 uW! empty $end + $var wire 1 }W! full $end + $var wire 1 uM pop $end + $var wire 1 um" push $end + $var wire 1 wV reading $end + $var wire 1 [h" reset $end + $var wire 5 ]_! size [4:0] $end + $var wire 5 ]_! size_r [4:0] $end + $var wire 1 s$ writing $end + $scope module genblk3 $end + $var wire 154 e_! data(0) [153:0] $end + $var wire 154 j_! data(1) [153:0] $end + $var wire 154 9`! data(10) [153:0] $end + $var wire 154 >`! data(11) [153:0] $end + $var wire 154 C`! data(12) [153:0] $end + $var wire 154 H`! data(13) [153:0] $end + $var wire 154 M`! data(14) [153:0] $end + $var wire 154 R`! data(15) [153:0] $end + $var wire 154 o_! data(2) [153:0] $end + $var wire 154 t_! data(3) [153:0] $end + $var wire 154 y_! data(4) [153:0] $end + $var wire 154 ~_! data(5) [153:0] $end + $var wire 154 %`! data(6) [153:0] $end + $var wire 154 *`! data(7) [153:0] $end + $var wire 154 /`! data(8) [153:0] $end + $var wire 154 4`! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 ]g! bypass_r $end + $var wire 154 {f! curr_r [153:0] $end + $var wire 1 uW! empty_r $end + $var wire 1 }W! full_r $end + $var wire 154 Sf! head_r [153:0] $end + $var wire 4 Ug! rd_ptr_next_r [3:0] $end + $var wire 4 Mg! rd_ptr_r [3:0] $end + $var wire 4 Eg! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 k` data_in [199:0] $end + $var wire 200 Ea data_out [199:0] $end + $var wire 1 e[! empty $end + $var wire 1 m[! full $end + $var wire 1 g* pop $end + $var wire 1 eU push $end + $var wire 1 }% reading $end + $var wire 1 [h" reset $end + $var wire 3 _x! size [2:0] $end + $var wire 3 _x! size_r [2:0] $end + $var wire 1 }a writing $end + $scope module genblk3 $end + $var wire 200 gx! data(0) [199:0] $end + $var wire 200 nx! data(1) [199:0] $end + $var wire 200 ux! data(2) [199:0] $end + $var wire 200 |x! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 W|! bypass_r $end + $var wire 200 e{! curr_r [199:0] $end + $var wire 1 e[! empty_r $end + $var wire 1 m[! full_r $end + $var wire 200 -{! head_r [199:0] $end + $var wire 2 O|! rd_ptr_next_r [1:0] $end + $var wire 2 G|! rd_ptr_r [1:0] $end + $var wire 2 ?|! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 MY in [242:0] $end + $var wire 243 Cn! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 243 Cn! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 3$ data_in [54:0] $end + $var wire 55 7V data_out [54:0] $end + $var wire 1 eW! empty $end + $var wire 1 mW! full $end + $var wire 1 UM pop $end + $var wire 1 }m" push $end + $var wire 1 GV reading $end + $var wire 1 [h" reset $end + $var wire 5 /\! size [4:0] $end + $var wire 5 /\! size_r [4:0] $end + $var wire 1 C$ writing $end + $scope module genblk3 $end + $var wire 55 7\! data(0) [54:0] $end + $var wire 55 9\! data(1) [54:0] $end + $var wire 55 K\! data(10) [54:0] $end + $var wire 55 M\! data(11) [54:0] $end + $var wire 55 O\! data(12) [54:0] $end + $var wire 55 Q\! data(13) [54:0] $end + $var wire 55 S\! data(14) [54:0] $end + $var wire 55 U\! data(15) [54:0] $end + $var wire 55 ;\! data(2) [54:0] $end + $var wire 55 =\! data(3) [54:0] $end + $var wire 55 ?\! data(4) [54:0] $end + $var wire 55 A\! data(5) [54:0] $end + $var wire 55 C\! data(6) [54:0] $end + $var wire 55 E\! data(7) [54:0] $end + $var wire 55 G\! data(8) [54:0] $end + $var wire 55 I\! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 U_! bypass_r $end + $var wire 55 -_! curr_r [54:0] $end + $var wire 1 eW! empty_r $end + $var wire 1 mW! full_r $end + $var wire 55 {^! head_r [54:0] $end + $var wire 4 M_! rd_ptr_next_r [3:0] $end + $var wire 4 E_! rd_ptr_r [3:0] $end + $var wire 4 =_! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 W^ in [315:0] $end + $var wire 316 'p! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 316 'p! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 K\ data_write [127:0] $end + $var wire 1 IS dirty_st1e $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 AS fill_sent $end + $var wire 1 U] force_core_miss $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 k\ invalidate_line $end + $var wire 1 +T is_snp_st1e $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 AS miss_st1e $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 128 q[ qual_read_data_st1 [127:0] $end + $var wire 1 Y[ qual_read_dirty_st1 $end + $var wire 16 a[ qual_read_dirtyb_st1 [15:0] $end + $var wire 20 i[ qual_read_tag_st1 [19:0] $end + $var wire 1 Q[ qual_read_valid_st1 $end + $var wire 128 1[ read_data_st1c(0) [127:0] $end + $var wire 1 wZ read_dirty_st1c(0) $end + $var wire 16 ![ read_dirtyb_st1c(0) [15:0] $end + $var wire 20 )[ read_tag_st1c(0) [19:0] $end + $var wire 1 oZ read_valid_st1c(0) $end + $var wire 6 /Z readaddr_st10 [5:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 1 M] real_miss $end + $var wire 1 {\ real_writefill $end + $var wire 1 =] req_invalid $end + $var wire 1 E] req_miss $end + $var wire 1 [h" reset $end + $var wire 1 5] should_write $end + $var wire 1 k\ snoop_hit_no_pending $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 #P stall $end + $var wire 1 #P stall_bank_pipe $end + $var wire 1 s\ tags_match $end + $var wire 128 wR use_read_data_st1e [127:0] $end + $var wire 1 ;\ use_read_dirty_st1e $end + $var wire 16 QS use_read_dirtyb_st1e [15:0] $end + $var wire 20 9S use_read_tag_st1e [19:0] $end + $var wire 1 3\ use_read_valid_st1e $end + $var wire 128 K\ use_write_data [127:0] $end + $var wire 16 C\ use_write_enable [15:0] $end + $var wire 1 ST valid_req_st1e $end + $var wire 16 -] we [15:0] $end + $var wire 2 gZ wordsel_st1e [1:0] $end + $var wire 26 kT writeaddr_st1e [25:0] $end + $var wire 128 GZ writedata_st1e [127:0] $end + $var wire 1 7Z writefill_st1e $end + $var wire 6 /Z writeladdr_st1e [5:0] $end + $var wire 20 %] writetag_st1e [19:0] $end + $var wire 32 ?Z writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 ]] normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 e] normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 m] normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 u] normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 '^ in [165:0] $end + $var wire 166 '^ out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 166 Uo! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 %o! dirty [63:0] $end + $var wire 1 }] do_write $end + $var wire 1 AS fill_sent $end + $var wire 32 Eo! i [31:0] $end + $var wire 1 k\ invalidate $end + $var wire 32 Mo! j [31:0] $end + $var wire 6 /Z read_addr [5:0] $end + $var wire 128 q[ read_data [127:0] $end + $var wire 1 Y[ read_dirty $end + $var wire 16 a[ read_dirtyb [15:0] $end + $var wire 20 i[ read_tag [19:0] $end + $var wire 1 Q[ read_valid $end + $var wire 1 [h" reset $end + $var wire 1 #P stall_bank_pipe $end + $var wire 20 %] tag_index [19:0] $end + $var wire 64 5o! valid [63:0] $end + $var wire 6 /Z write_addr [5:0] $end + $var wire 128 K\ write_data [127:0] $end + $var wire 16 C\ write_enable [15:0] $end + $var wire 1 {\ write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(2) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 C.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 %! curr_bank_core_req_valid [3:0] $end + $var wire 32 /2 curr_bank_core_rsp_data [31:0] $end + $var wire 1 -! curr_bank_core_rsp_ready $end + $var wire 42 72 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 '2 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 #.! curr_bank_core_rsp_valid $end + $var wire 26 3.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 G2 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 +.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 'n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 _2 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 W2 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 g2 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 5! curr_bank_dram_wb_req_ready $end + $var wire 1 O2 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 ;.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 /n" curr_bank_snp_req_valid $end + $var wire 1 =! curr_bank_snp_rsp_ready $end + $var wire 28 13 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 )3 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 ?f addr_st1(0) [25:0] $end + $var wire 26 =i addr_st1e [25:0] $end + $var wire 26 3.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 C.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 %! core_req_valid [3:0] $end + $var wire 32 /2 core_rsp_data [31:0] $end + $var wire 1 -! core_rsp_ready $end + $var wire 42 72 core_rsp_tag [41:0] $end + $var wire 2 '2 core_rsp_tid [1:0] $end + $var wire 1 #.! core_rsp_valid $end + $var wire 32 {~! cwbq_data [31:0] $end + $var wire 1 O"" cwbq_empty $end + $var wire 1 W"" cwbq_full $end + $var wire 1 !+ cwbq_pop $end + $var wire 1 }i cwbq_push $end + $var wire 1 ;d cwbq_push_stall $end + $var wire 1 'j cwbq_push_unqual $end + $var wire 42 ;~! cwbq_tag [41:0] $end + $var wire 2 3~! cwbq_tid [1:0] $end + $var wire 26 Ob dfpq_addr_st0 [25:0] $end + $var wire 1 o|! dfpq_empty $end + $var wire 128 Wb dfpq_filldata_st0 [127:0] $end + $var wire 1 w|! dfpq_full $end + $var wire 1 Gb dfpq_pop $end + $var wire 1 sd dfpq_pop_unqual $end + $var wire 1 yg dirty_st1e $end + $var wire 1 M!" dirty_st2 $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 16 U!" dirtyb_st2 [15:0] $end + $var wire 26 3.! dram_fill_req_addr [25:0] $end + $var wire 1 ei dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 Kd dram_fill_req_stall $end + $var wire 1 /j dram_fill_req_unqual $end + $var wire 1 G2 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 +.! dram_fill_rsp_ready $end + $var wire 1 'n" dram_fill_rsp_valid $end + $var wire 26 _2 dram_wb_req_addr [25:0] $end + $var wire 16 W2 dram_wb_req_byteen [15:0] $end + $var wire 128 g2 dram_wb_req_data [127:0] $end + $var wire 1 '& dram_wb_req_fire $end + $var wire 1 5! dram_wb_req_ready $end + $var wire 1 O2 dram_wb_req_valid $end + $var wire 1 !#" dwbq_dual_valid_sel $end + $var wire 1 _"" dwbq_empty $end + $var wire 1 g"" dwbq_full $end + $var wire 1 ?j dwbq_is_dwb_in $end + $var wire 1 Oj dwbq_is_dwb_out $end + $var wire 1 Gj dwbq_is_snp_in $end + $var wire 1 Wj dwbq_is_snp_out $end + $var wire 1 )+ dwbq_pop $end + $var wire 1 7j dwbq_push $end + $var wire 1 Cd dwbq_push_stall $end + $var wire 1 _j dwbq_push_unqual $end + $var wire 26 o"" dwbq_req_addr [25:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 u!" fill_saw_dirty_st2 $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 kd going_to_write_st1(0) $end + $var wire 49 Wf inst_meta_st1(0) [48:0] $end + $var wire 49 ]!" inst_meta_st2 [48:0] $end + $var wire 1 [d is_fill_in_pipe $end + $var wire 1 cd is_fill_st1(0) $end + $var wire 1 [~! is_fill_st2 $end + $var wire 1 9g is_mrvq_st1(0) $end + $var wire 1 -i is_mrvq_st1e $end + $var wire 1 -i is_mrvq_st1e_st2 $end + $var wire 1 7"" is_mrvq_st2 $end + $var wire 1 )g is_snp_st1(0) $end + $var wire 1 [h is_snp_st1e $end + $var wire 1 }!" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 1 {h miss_add_because_miss $end + $var wire 1 /"" miss_add_because_pending $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 ui miss_add_is_mrvq $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 1 ei miss_add_unqual $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 1 qg miss_st1e $end + $var wire 1 E!" miss_st2 $end + $var wire 26 Q}! mrvq_addr_st0 [25:0] $end + $var wire 4 y}! mrvq_byteen_st0 [3:0] $end + $var wire 1 9}! mrvq_full $end + $var wire 1 Ui mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 ]i mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 1 Mi mrvq_init_ready_state_st2 $end + $var wire 1 G"" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 #~! mrvq_is_snp_st0 $end + $var wire 1 qc mrvq_pending_hazard_st1e $end + $var wire 1 Yc mrvq_pop $end + $var wire 1 ac mrvq_pop_unqual $end + $var wire 1 3d mrvq_push_stall $end + $var wire 1 5i mrvq_recover_ready_state_st1e $end + $var wire 1 ?"" mrvq_recover_ready_state_st2 $end + $var wire 1 ic mrvq_rw_st0 $end + $var wire 1 +~! mrvq_snp_invalidate_st0 $end + $var wire 1 A}! mrvq_stop $end + $var wire 42 i}! mrvq_tag_st0 [41:0] $end + $var wire 2 I}! mrvq_tid_st0 [1:0] $end + $var wire 1 ac mrvq_valid_st0 $end + $var wire 32 a}! mrvq_writeword_st0 [31:0] $end + $var wire 2 Y}! mrvq_wsel_st0 [1:0] $end + $var wire 26 5e qual_addr_st0 [25:0] $end + $var wire 1 }e qual_going_to_write_st0 $end + $var wire 49 me qual_inst_meta_st0 [48:0] $end + $var wire 1 sd qual_is_fill_st0 $end + $var wire 1 ac qual_is_mrvq_st0 $end + $var wire 1 'f qual_is_snp_st0 $end + $var wire 1 /f qual_snp_invalidate_st0 $end + $var wire 1 -e qual_valid_st0 $end + $var wire 1 Ei qual_valid_st1e_2 $end + $var wire 128 Me qual_writedata_st0 [127:0] $end + $var wire 32 Ee qual_writeword_st0 [31:0] $end + $var wire 2 =e qual_wsel_st0 [1:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 128 %!" readdata_st2 [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 20 m!" readtag_st2 [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 32 {~! readword_st2 [31:0] $end + $var wire 1 +d recover_mrvq_state_st2 $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 {d reqq_pop_unqual $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 1g snp_invalidate_st1(0) $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 '"" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 ;.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 /n" snp_req_valid $end + $var wire 1 /& snp_rsp_fire $end + $var wire 1 =! snp_rsp_ready $end + $var wire 28 13 snp_rsp_tag [27:0] $end + $var wire 1 )3 snp_rsp_valid $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 /"" snp_to_mrvq_st2 $end + $var wire 26 /b snrq_addr_st0 [25:0] $end + $var wire 1 _|! snrq_empty $end + $var wire 1 g|! snrq_full $end + $var wire 1 7b snrq_invalidate_st0 $end + $var wire 1 'b snrq_pop $end + $var wire 1 %e snrq_pop_unqual $end + $var wire 28 ?b snrq_tag_st0 [27:0] $end + $var wire 28 w"" snrq_tag_st2 [27:0] $end + $var wire 1 yc st2_pending_hazard_st1e $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 42 +h tag_st1e [41:0] $end + $var wire 2 ;h tid_st1e [1:0] $end + $var wire 1 7f valid_st1(0) $end + $var wire 1 %i valid_st1e $end + $var wire 1 c~! valid_st2 $end + $var wire 128 gf writedata_st1(0) [127:0] $end + $var wire 32 Of writeword_st1(0) [31:0] $end + $var wire 32 s~! writeword_st2 [31:0] $end + $var wire 2 Gf wsel_st1(0) [1:0] $end + $var wire 2 k~! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 y;" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 5=" dequeue_index [3:0] $end + $var wire 1 ac dequeue_possible $end + $var wire 4 E=" enqueue_index [3:0] $end + $var wire 1 U=" enqueue_possible $end + $var wire 26 =i fill_addr_st1 [25:0] $end + $var wire 4 ==" head_ptr [3:0] $end + $var wire 1 Kt increment_head $end + $var wire 1 gn is_fill_st1 $end + $var wire 1 ui is_mrvq $end + $var wire 16 ys make_ready [15:0] $end + $var wire 16 #t make_ready_push [15:0] $end + $var wire 85 q7" metadata_table(0) [84:0] $end + $var wire 85 t7" metadata_table(1) [84:0] $end + $var wire 85 18" metadata_table(10) [84:0] $end + $var wire 85 48" metadata_table(11) [84:0] $end + $var wire 85 78" metadata_table(12) [84:0] $end + $var wire 85 :8" metadata_table(13) [84:0] $end + $var wire 85 =8" metadata_table(14) [84:0] $end + $var wire 85 @8" metadata_table(15) [84:0] $end + $var wire 85 w7" metadata_table(2) [84:0] $end + $var wire 85 z7" metadata_table(3) [84:0] $end + $var wire 85 }7" metadata_table(4) [84:0] $end + $var wire 85 "8" metadata_table(5) [84:0] $end + $var wire 85 %8" metadata_table(6) [84:0] $end + $var wire 85 (8" metadata_table(7) [84:0] $end + $var wire 85 +8" metadata_table(8) [84:0] $end + $var wire 85 .8" metadata_table(9) [84:0] $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 26 Q}! miss_resrv_addr_st0 [25:0] $end + $var wire 4 y}! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 a}! miss_resrv_data_st0 [31:0] $end + $var wire 1 9}! miss_resrv_full $end + $var wire 1 #~! miss_resrv_is_snp_st0 $end + $var wire 1 Yc miss_resrv_pop $end + $var wire 1 ic miss_resrv_rw_st0 $end + $var wire 1 +~! miss_resrv_snp_invalidate_st0 $end + $var wire 1 A}! miss_resrv_stop $end + $var wire 42 i}! miss_resrv_tag_st0 [41:0] $end + $var wire 2 I}! miss_resrv_tid_st0 [1:0] $end + $var wire 1 ac miss_resrv_valid_st0 $end + $var wire 2 Y}! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 Mi mrvq_init_ready_state $end + $var wire 1 ;t mrvq_pop $end + $var wire 1 3t mrvq_push $end + $var wire 1 qc pending_hazard $end + $var wire 1 [t qual_mrvq_init $end + $var wire 16 -=" ready_table [15:0] $end + $var wire 1 Ct recover_state $end + $var wire 1 [h" reset $end + $var wire 4 5=" schedule_ptr [3:0] $end + $var wire 5 M=" size [4:0] $end + $var wire 4 E=" tail_ptr [3:0] $end + $var wire 1 St update_ready $end + $var wire 16 +t valid_address_match [15:0] $end + $var wire 16 %=" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 %! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Y/" o_empty $end + $var wire 1 [l out_empty $end + $var wire 120 ik out_per_addr [119:0] $end + $var wire 16 ak out_per_byteen [15:0] $end + $var wire 4 Yk out_per_rw [3:0] $end + $var wire 42 Kl out_per_tag [41:0] $end + $var wire 4 Qk out_per_valids [3:0] $end + $var wire 128 +l out_per_writedata [127:0] $end + $var wire 1 cl pop_qual $end + $var wire 1 1+ push_qual $end + $var wire 120 w." qual_addr [119:0] $end + $var wire 16 o." qual_byteen [15:0] $end + $var wire 1 )c qual_has_request $end + $var wire 2 1c qual_request_index [1:0] $end + $var wire 4 g." qual_rw [3:0] $end + $var wire 42 )}! qual_tag [41:0] $end + $var wire 4 _." qual_valids [3:0] $end + $var wire 128 9/" qual_writedata [127:0] $end + $var wire 4 kl real_out_per_valids [3:0] $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a/" use_empty $end + $var wire 120 w." use_per_addr [119:0] $end + $var wire 16 o." use_per_byteen [15:0] $end + $var wire 4 g." use_per_rw [3:0] $end + $var wire 42 )}! use_per_tag [41:0] $end + $var wire 4 _." use_per_valids [3:0] $end + $var wire 128 9/" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 !' data_in [313:0] $end + $var wire 314 sl data_out [313:0] $end + $var wire 1 Y/" empty $end + $var wire 1 !}! full $end + $var wire 1 cl pop $end + $var wire 1 1+ push $end + $var wire 1 em reading $end + $var wire 1 [h" reset $end + $var wire 3 i/" size [2:0] $end + $var wire 3 i/" size_r [2:0] $end + $var wire 1 q' writing $end + $scope module genblk3 $end + $var wire 314 q/" data(0) [313:0] $end + $var wire 314 {/" data(1) [313:0] $end + $var wire 314 '0" data(2) [313:0] $end + $var wire 314 10" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 55" bypass_r $end + $var wire 314 +4" curr_r [313:0] $end + $var wire 1 Y/" empty_r $end + $var wire 1 !}! full_r $end + $var wire 314 93" head_r [313:0] $end + $var wire 2 -5" rd_ptr_next_r [1:0] $end + $var wire 2 %5" rd_ptr_r [1:0] $end + $var wire 2 {4" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 1c grant_index [1:0] $end + $var wire 4 mm grant_onehot [3:0] $end + $var wire 1 )c grant_valid $end + $var wire 4 _." requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 mm grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 _." data_in [3:0] $end + $var wire 2 1c data_out [1:0] $end + $var wire 32 um i [31:0] $end + $var wire 1 )c valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 ct data_in [75:0] $end + $var wire 76 {t data_out [75:0] $end + $var wire 1 O"" empty $end + $var wire 1 W"" full $end + $var wire 1 !+ pop $end + $var wire 1 }i push $end + $var wire 1 y' reading $end + $var wire 1 [h" reset $end + $var wire 3 ]=" size [2:0] $end + $var wire 3 ]=" size_r [2:0] $end + $var wire 1 5u writing $end + $scope module genblk3 $end + $var wire 76 e=" data(0) [75:0] $end + $var wire 76 h=" data(1) [75:0] $end + $var wire 76 k=" data(2) [75:0] $end + $var wire 76 n=" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Q?" bypass_r $end + $var wire 76 !?" curr_r [75:0] $end + $var wire 1 O"" empty_r $end + $var wire 1 W"" full_r $end + $var wire 76 g>" head_r [75:0] $end + $var wire 2 I?" rd_ptr_next_r [1:0] $end + $var wire 2 A?" rd_ptr_r [1:0] $end + $var wire 2 9?" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 O& data_in [153:0] $end + $var wire 154 !k data_out [153:0] $end + $var wire 1 o|! empty $end + $var wire 1 w|! full $end + $var wire 1 Gb pop $end + $var wire 1 'n" push $end + $var wire 1 Ik reading $end + $var wire 1 [h" reset $end + $var wire 5 W&" size [4:0] $end + $var wire 5 W&" size_r [4:0] $end + $var wire 1 w& writing $end + $scope module genblk3 $end + $var wire 154 _&" data(0) [153:0] $end + $var wire 154 d&" data(1) [153:0] $end + $var wire 154 3'" data(10) [153:0] $end + $var wire 154 8'" data(11) [153:0] $end + $var wire 154 ='" data(12) [153:0] $end + $var wire 154 B'" data(13) [153:0] $end + $var wire 154 G'" data(14) [153:0] $end + $var wire 154 L'" data(15) [153:0] $end + $var wire 154 i&" data(2) [153:0] $end + $var wire 154 n&" data(3) [153:0] $end + $var wire 154 s&" data(4) [153:0] $end + $var wire 154 x&" data(5) [153:0] $end + $var wire 154 }&" data(6) [153:0] $end + $var wire 154 $'" data(7) [153:0] $end + $var wire 154 )'" data(8) [153:0] $end + $var wire 154 .'" data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 W." bypass_r $end + $var wire 154 u-" curr_r [153:0] $end + $var wire 1 o|! empty_r $end + $var wire 1 w|! full_r $end + $var wire 154 M-" head_r [153:0] $end + $var wire 4 O." rd_ptr_next_r [3:0] $end + $var wire 4 G." rd_ptr_r [3:0] $end + $var wire 4 ?." wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 =u data_in [199:0] $end + $var wire 200 uu data_out [199:0] $end + $var wire 1 _"" empty $end + $var wire 1 g"" full $end + $var wire 1 )+ pop $end + $var wire 1 7j push $end + $var wire 1 #( reading $end + $var wire 1 [h" reset $end + $var wire 3 Y?" size [2:0] $end + $var wire 3 Y?" size_r [2:0] $end + $var wire 1 Ov writing $end + $scope module genblk3 $end + $var wire 200 a?" data(0) [199:0] $end + $var wire 200 h?" data(1) [199:0] $end + $var wire 200 o?" data(2) [199:0] $end + $var wire 200 v?" data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 QC" bypass_r $end + $var wire 200 _B" curr_r [199:0] $end + $var wire 1 _"" empty_r $end + $var wire 1 g"" full_r $end + $var wire 200 'B" head_r [199:0] $end + $var wire 2 IC" rd_ptr_next_r [1:0] $end + $var wire 2 AC" rd_ptr_r [1:0] $end + $var wire 2 9C" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 }m in [242:0] $end + $var wire 243 =5" out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 243 =5" value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 7& data_in [54:0] $end + $var wire 55 gj data_out [54:0] $end + $var wire 1 _|! empty $end + $var wire 1 g|! full $end + $var wire 1 'b pop $end + $var wire 1 /n" push $end + $var wire 1 wj reading $end + $var wire 1 [h" reset $end + $var wire 5 )#" size [4:0] $end + $var wire 5 )#" size_r [4:0] $end + $var wire 1 G& writing $end + $scope module genblk3 $end + $var wire 55 1#" data(0) [54:0] $end + $var wire 55 3#" data(1) [54:0] $end + $var wire 55 E#" data(10) [54:0] $end + $var wire 55 G#" data(11) [54:0] $end + $var wire 55 I#" data(12) [54:0] $end + $var wire 55 K#" data(13) [54:0] $end + $var wire 55 M#" data(14) [54:0] $end + $var wire 55 O#" data(15) [54:0] $end + $var wire 55 5#" data(2) [54:0] $end + $var wire 55 7#" data(3) [54:0] $end + $var wire 55 9#" data(4) [54:0] $end + $var wire 55 ;#" data(5) [54:0] $end + $var wire 55 =#" data(6) [54:0] $end + $var wire 55 ?#" data(7) [54:0] $end + $var wire 55 A#" data(8) [54:0] $end + $var wire 55 C#" data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 O&" bypass_r $end + $var wire 55 '&" curr_r [54:0] $end + $var wire 1 _|! empty_r $end + $var wire 1 g|! full_r $end + $var wire 55 u%" head_r [54:0] $end + $var wire 4 G&" rd_ptr_next_r [3:0] $end + $var wire 4 ?&" rd_ptr_r [3:0] $end + $var wire 4 7&" wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 )s in [315:0] $end + $var wire 316 !7" out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 316 !7" value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 {p data_write [127:0] $end + $var wire 1 yg dirty_st1e $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 qg fill_sent $end + $var wire 1 'r force_core_miss $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 =q invalidate_line $end + $var wire 1 [h is_snp_st1e $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 qg miss_st1e $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 128 Cp qual_read_data_st1 [127:0] $end + $var wire 1 +p qual_read_dirty_st1 $end + $var wire 16 3p qual_read_dirtyb_st1 [15:0] $end + $var wire 20 ;p qual_read_tag_st1 [19:0] $end + $var wire 1 #p qual_read_valid_st1 $end + $var wire 128 ao read_data_st1c(0) [127:0] $end + $var wire 1 Io read_dirty_st1c(0) $end + $var wire 16 Qo read_dirtyb_st1c(0) [15:0] $end + $var wire 20 Yo read_tag_st1c(0) [19:0] $end + $var wire 1 Ao read_valid_st1c(0) $end + $var wire 6 _n readaddr_st10 [5:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 1 }q real_miss $end + $var wire 1 Mq real_writefill $end + $var wire 1 mq req_invalid $end + $var wire 1 uq req_miss $end + $var wire 1 [h" reset $end + $var wire 1 eq should_write $end + $var wire 1 =q snoop_hit_no_pending $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 Sd stall $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 1 Eq tags_match $end + $var wire 128 Ig use_read_data_st1e [127:0] $end + $var wire 1 kp use_read_dirty_st1e $end + $var wire 16 #h use_read_dirtyb_st1e [15:0] $end + $var wire 20 ig use_read_tag_st1e [19:0] $end + $var wire 1 cp use_read_valid_st1e $end + $var wire 128 {p use_write_data [127:0] $end + $var wire 16 sp use_write_enable [15:0] $end + $var wire 1 %i valid_req_st1e $end + $var wire 16 ]q we [15:0] $end + $var wire 2 9o wordsel_st1e [1:0] $end + $var wire 26 =i writeaddr_st1e [25:0] $end + $var wire 128 wn writedata_st1e [127:0] $end + $var wire 1 gn writefill_st1e $end + $var wire 6 _n writeladdr_st1e [5:0] $end + $var wire 20 Uq writetag_st1e [19:0] $end + $var wire 32 on writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 /r normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 7r normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 ?r normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 Gr normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 Wr in [165:0] $end + $var wire 166 Wr out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 166 O6" value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 }5" dirty [63:0] $end + $var wire 1 Or do_write $end + $var wire 1 qg fill_sent $end + $var wire 32 ?6" i [31:0] $end + $var wire 1 =q invalidate $end + $var wire 32 G6" j [31:0] $end + $var wire 6 _n read_addr [5:0] $end + $var wire 128 Cp read_data [127:0] $end + $var wire 1 +p read_dirty $end + $var wire 16 3p read_dirtyb [15:0] $end + $var wire 20 ;p read_tag [19:0] $end + $var wire 1 #p read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 20 Uq tag_index [19:0] $end + $var wire 64 /6" valid [63:0] $end + $var wire 6 _n write_addr [5:0] $end + $var wire 128 {p write_data [127:0] $end + $var wire 16 sp write_enable [15:0] $end + $var wire 1 Mq write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(3) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 k.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 E! curr_bank_core_req_valid [3:0] $end + $var wire 32 A3 curr_bank_core_rsp_data [31:0] $end + $var wire 1 M! curr_bank_core_rsp_ready $end + $var wire 42 I3 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 93 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 K.! curr_bank_core_rsp_valid $end + $var wire 26 [.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 Y3 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 S.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 7n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 q3 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 i3 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 y3 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 U! curr_bank_dram_wb_req_ready $end + $var wire 1 a3 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 c.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 ?n" curr_bank_snp_req_valid $end + $var wire 1 ]! curr_bank_snp_rsp_ready $end + $var wire 28 C4 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 ;4 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 oz addr_st1(0) [25:0] $end + $var wire 26 m} addr_st1e [25:0] $end + $var wire 26 [.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 k.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 E! core_req_valid [3:0] $end + $var wire 32 A3 core_rsp_data [31:0] $end + $var wire 1 M! core_rsp_ready $end + $var wire 42 I3 core_rsp_tag [41:0] $end + $var wire 2 93 core_rsp_tid [1:0] $end + $var wire 1 K.! core_rsp_valid $end + $var wire 32 uE" cwbq_data [31:0] $end + $var wire 1 IG" cwbq_empty $end + $var wire 1 QG" cwbq_full $end + $var wire 1 A+ cwbq_pop $end + $var wire 1 O~ cwbq_push $end + $var wire 1 kx cwbq_push_stall $end + $var wire 1 W~ cwbq_push_unqual $end + $var wire 42 5E" cwbq_tag [41:0] $end + $var wire 2 -E" cwbq_tid [1:0] $end + $var wire 26 !w dfpq_addr_st0 [25:0] $end + $var wire 1 iC" dfpq_empty $end + $var wire 128 )w dfpq_filldata_st0 [127:0] $end + $var wire 1 qC" dfpq_full $end + $var wire 1 wv dfpq_pop $end + $var wire 1 Ey dfpq_pop_unqual $end + $var wire 1 K| dirty_st1e $end + $var wire 1 GF" dirty_st2 $end + $var wire 16 S| dirtyb_st1e [15:0] $end + $var wire 16 OF" dirtyb_st2 [15:0] $end + $var wire 26 [.! dram_fill_req_addr [25:0] $end + $var wire 1 7~ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 {x dram_fill_req_stall $end + $var wire 1 _~ dram_fill_req_unqual $end + $var wire 1 Y3 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 S.! dram_fill_rsp_ready $end + $var wire 1 7n" dram_fill_rsp_valid $end + $var wire 26 q3 dram_wb_req_addr [25:0] $end + $var wire 16 i3 dram_wb_req_byteen [15:0] $end + $var wire 128 y3 dram_wb_req_data [127:0] $end + $var wire 1 +( dram_wb_req_fire $end + $var wire 1 U! dram_wb_req_ready $end + $var wire 1 a3 dram_wb_req_valid $end + $var wire 1 yG" dwbq_dual_valid_sel $end + $var wire 1 YG" dwbq_empty $end + $var wire 1 aG" dwbq_full $end + $var wire 1 o~ dwbq_is_dwb_in $end + $var wire 1 !!! dwbq_is_dwb_out $end + $var wire 1 w~ dwbq_is_snp_in $end + $var wire 1 )!! dwbq_is_snp_out $end + $var wire 1 I+ dwbq_pop $end + $var wire 1 g~ dwbq_push $end + $var wire 1 sx dwbq_push_stall $end + $var wire 1 1!! dwbq_push_unqual $end + $var wire 26 iG" dwbq_req_addr [25:0] $end + $var wire 1 %} fill_saw_dirty_st1e $end + $var wire 1 oF" fill_saw_dirty_st2 $end + $var wire 1 Sx force_request_miss_st1e $end + $var wire 1 =y going_to_write_st1(0) $end + $var wire 49 ){ inst_meta_st1(0) [48:0] $end + $var wire 49 WF" inst_meta_st2 [48:0] $end + $var wire 1 -y is_fill_in_pipe $end + $var wire 1 5y is_fill_st1(0) $end + $var wire 1 UE" is_fill_st2 $end + $var wire 1 i{ is_mrvq_st1(0) $end + $var wire 1 ]} is_mrvq_st1e $end + $var wire 1 ]} is_mrvq_st1e_st2 $end + $var wire 1 1G" is_mrvq_st2 $end + $var wire 1 Y{ is_snp_st1(0) $end + $var wire 1 -} is_snp_st1e $end + $var wire 1 wF" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 {| mem_byteen_st1e [3:0] $end + $var wire 1 s| mem_rw_st1e $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 1 M} miss_add_because_miss $end + $var wire 1 )G" miss_add_because_pending $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 G~ miss_add_is_mrvq $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 1 7~ miss_add_unqual $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 1 C| miss_st1e $end + $var wire 1 ?F" miss_st2 $end + $var wire 26 KD" mrvq_addr_st0 [25:0] $end + $var wire 4 sD" mrvq_byteen_st0 [3:0] $end + $var wire 1 3D" mrvq_full $end + $var wire 1 '~ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 /~ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 E} mrvq_init_ready_state_st1e $end + $var wire 1 }} mrvq_init_ready_state_st2 $end + $var wire 1 AG" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 {D" mrvq_is_snp_st0 $end + $var wire 1 Cx mrvq_pending_hazard_st1e $end + $var wire 1 +x mrvq_pop $end + $var wire 1 3x mrvq_pop_unqual $end + $var wire 1 cx mrvq_push_stall $end + $var wire 1 e} mrvq_recover_ready_state_st1e $end + $var wire 1 9G" mrvq_recover_ready_state_st2 $end + $var wire 1 ;x mrvq_rw_st0 $end + $var wire 1 %E" mrvq_snp_invalidate_st0 $end + $var wire 1 ;D" mrvq_stop $end + $var wire 42 cD" mrvq_tag_st0 [41:0] $end + $var wire 2 CD" mrvq_tid_st0 [1:0] $end + $var wire 1 3x mrvq_valid_st0 $end + $var wire 32 [D" mrvq_writeword_st0 [31:0] $end + $var wire 2 SD" mrvq_wsel_st0 [1:0] $end + $var wire 26 ey qual_addr_st0 [25:0] $end + $var wire 1 Oz qual_going_to_write_st0 $end + $var wire 49 ?z qual_inst_meta_st0 [48:0] $end + $var wire 1 Ey qual_is_fill_st0 $end + $var wire 1 3x qual_is_mrvq_st0 $end + $var wire 1 Wz qual_is_snp_st0 $end + $var wire 1 _z qual_snp_invalidate_st0 $end + $var wire 1 ]y qual_valid_st0 $end + $var wire 1 u} qual_valid_st1e_2 $end + $var wire 128 }y qual_writedata_st0 [127:0] $end + $var wire 32 uy qual_writeword_st0 [31:0] $end + $var wire 2 my qual_wsel_st0 [1:0] $end + $var wire 128 y{ readdata_st1e [127:0] $end + $var wire 128 }E" readdata_st2 [127:0] $end + $var wire 20 ;| readtag_st1e [19:0] $end + $var wire 20 gF" readtag_st2 [19:0] $end + $var wire 32 q{ readword_st1e [31:0] $end + $var wire 32 uE" readword_st2 [31:0] $end + $var wire 1 [x recover_mrvq_state_st2 $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 My reqq_pop_unqual $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a{ snp_invalidate_st1(0) $end + $var wire 1 5} snp_invalidate_st1e $end + $var wire 1 !G" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 c.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 ?n" snp_req_valid $end + $var wire 1 3( snp_rsp_fire $end + $var wire 1 ]! snp_rsp_ready $end + $var wire 28 C4 snp_rsp_tag [27:0] $end + $var wire 1 ;4 snp_rsp_valid $end + $var wire 1 =} snp_to_mrvq_st1e $end + $var wire 1 )G" snp_to_mrvq_st2 $end + $var wire 26 _v snrq_addr_st0 [25:0] $end + $var wire 1 YC" snrq_empty $end + $var wire 1 aC" snrq_full $end + $var wire 1 gv snrq_invalidate_st0 $end + $var wire 1 Wv snrq_pop $end + $var wire 1 Uy snrq_pop_unqual $end + $var wire 28 ov snrq_tag_st0 [27:0] $end + $var wire 28 qG" snrq_tag_st2 [27:0] $end + $var wire 1 Kx st2_pending_hazard_st1e $end + $var wire 1 %y stall_bank_pipe $end + $var wire 42 [| tag_st1e [41:0] $end + $var wire 2 k| tid_st1e [1:0] $end + $var wire 1 gz valid_st1(0) $end + $var wire 1 U} valid_st1e $end + $var wire 1 ]E" valid_st2 $end + $var wire 128 9{ writedata_st1(0) [127:0] $end + $var wire 32 !{ writeword_st1(0) [31:0] $end + $var wire 32 mE" writeword_st2 [31:0] $end + $var wire 2 wz wsel_st1(0) [1:0] $end + $var wire 2 eE" wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 s`" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 /b" dequeue_index [3:0] $end + $var wire 1 3x dequeue_possible $end + $var wire 4 ?b" enqueue_index [3:0] $end + $var wire 1 Ob" enqueue_possible $end + $var wire 26 m} fill_addr_st1 [25:0] $end + $var wire 4 7b" head_ptr [3:0] $end + $var wire 1 {*! increment_head $end + $var wire 1 9%! is_fill_st1 $end + $var wire 1 G~ is_mrvq $end + $var wire 16 K*! make_ready [15:0] $end + $var wire 16 S*! make_ready_push [15:0] $end + $var wire 85 k\" metadata_table(0) [84:0] $end + $var wire 85 n\" metadata_table(1) [84:0] $end + $var wire 85 +]" metadata_table(10) [84:0] $end + $var wire 85 .]" metadata_table(11) [84:0] $end + $var wire 85 1]" metadata_table(12) [84:0] $end + $var wire 85 4]" metadata_table(13) [84:0] $end + $var wire 85 7]" metadata_table(14) [84:0] $end + $var wire 85 :]" metadata_table(15) [84:0] $end + $var wire 85 q\" metadata_table(2) [84:0] $end + $var wire 85 t\" metadata_table(3) [84:0] $end + $var wire 85 w\" metadata_table(4) [84:0] $end + $var wire 85 z\" metadata_table(5) [84:0] $end + $var wire 85 }\" metadata_table(6) [84:0] $end + $var wire 85 "]" metadata_table(7) [84:0] $end + $var wire 85 %]" metadata_table(8) [84:0] $end + $var wire 85 (]" metadata_table(9) [84:0] $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 26 KD" miss_resrv_addr_st0 [25:0] $end + $var wire 4 sD" miss_resrv_byteen_st0 [3:0] $end + $var wire 32 [D" miss_resrv_data_st0 [31:0] $end + $var wire 1 3D" miss_resrv_full $end + $var wire 1 {D" miss_resrv_is_snp_st0 $end + $var wire 1 +x miss_resrv_pop $end + $var wire 1 ;x miss_resrv_rw_st0 $end + $var wire 1 %E" miss_resrv_snp_invalidate_st0 $end + $var wire 1 ;D" miss_resrv_stop $end + $var wire 42 cD" miss_resrv_tag_st0 [41:0] $end + $var wire 2 CD" miss_resrv_tid_st0 [1:0] $end + $var wire 1 3x miss_resrv_valid_st0 $end + $var wire 2 SD" miss_resrv_wsel_st0 [1:0] $end + $var wire 1 }} mrvq_init_ready_state $end + $var wire 1 k*! mrvq_pop $end + $var wire 1 c*! mrvq_push $end + $var wire 1 Cx pending_hazard $end + $var wire 1 -+! qual_mrvq_init $end + $var wire 16 'b" ready_table [15:0] $end + $var wire 1 s*! recover_state $end + $var wire 1 [h" reset $end + $var wire 4 /b" schedule_ptr [3:0] $end + $var wire 5 Gb" size [4:0] $end + $var wire 4 ?b" tail_ptr [3:0] $end + $var wire 1 %+! update_ready $end + $var wire 16 [*! valid_address_match [15:0] $end + $var wire 16 }a" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 E! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 ST" o_empty $end + $var wire 1 -#! out_empty $end + $var wire 120 ;"! out_per_addr [119:0] $end + $var wire 16 3"! out_per_byteen [15:0] $end + $var wire 4 +"! out_per_rw [3:0] $end + $var wire 42 {"! out_per_tag [41:0] $end + $var wire 4 #"! out_per_valids [3:0] $end + $var wire 128 ["! out_per_writedata [127:0] $end + $var wire 1 5#! pop_qual $end + $var wire 1 Q+ push_qual $end + $var wire 120 qS" qual_addr [119:0] $end + $var wire 16 iS" qual_byteen [15:0] $end + $var wire 1 Yw qual_has_request $end + $var wire 2 aw qual_request_index [1:0] $end + $var wire 4 aS" qual_rw [3:0] $end + $var wire 42 #D" qual_tag [41:0] $end + $var wire 4 YS" qual_valids [3:0] $end + $var wire 128 3T" qual_writedata [127:0] $end + $var wire 4 =#! real_out_per_valids [3:0] $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 [T" use_empty $end + $var wire 120 qS" use_per_addr [119:0] $end + $var wire 16 iS" use_per_byteen [15:0] $end + $var wire 4 aS" use_per_rw [3:0] $end + $var wire 42 #D" use_per_tag [41:0] $end + $var wire 4 YS" use_per_valids [3:0] $end + $var wire 128 3T" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 %) data_in [313:0] $end + $var wire 314 E#! data_out [313:0] $end + $var wire 1 ST" empty $end + $var wire 1 yC" full $end + $var wire 1 5#! pop $end + $var wire 1 Q+ push $end + $var wire 1 7$! reading $end + $var wire 1 [h" reset $end + $var wire 3 cT" size [2:0] $end + $var wire 3 cT" size_r [2:0] $end + $var wire 1 u) writing $end + $scope module genblk3 $end + $var wire 314 kT" data(0) [313:0] $end + $var wire 314 uT" data(1) [313:0] $end + $var wire 314 !U" data(2) [313:0] $end + $var wire 314 +U" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 /Z" bypass_r $end + $var wire 314 %Y" curr_r [313:0] $end + $var wire 1 ST" empty_r $end + $var wire 1 yC" full_r $end + $var wire 314 3X" head_r [313:0] $end + $var wire 2 'Z" rd_ptr_next_r [1:0] $end + $var wire 2 }Y" rd_ptr_r [1:0] $end + $var wire 2 uY" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 aw grant_index [1:0] $end + $var wire 4 ?$! grant_onehot [3:0] $end + $var wire 1 Yw grant_valid $end + $var wire 4 YS" requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 ?$! grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 YS" data_in [3:0] $end + $var wire 2 aw data_out [1:0] $end + $var wire 32 G$! i [31:0] $end + $var wire 1 Yw valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 5+! data_in [75:0] $end + $var wire 76 M+! data_out [75:0] $end + $var wire 1 IG" empty $end + $var wire 1 QG" full $end + $var wire 1 A+ pop $end + $var wire 1 O~ push $end + $var wire 1 }) reading $end + $var wire 1 [h" reset $end + $var wire 3 Wb" size [2:0] $end + $var wire 3 Wb" size_r [2:0] $end + $var wire 1 e+! writing $end + $scope module genblk3 $end + $var wire 76 _b" data(0) [75:0] $end + $var wire 76 bb" data(1) [75:0] $end + $var wire 76 eb" data(2) [75:0] $end + $var wire 76 hb" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Kd" bypass_r $end + $var wire 76 yc" curr_r [75:0] $end + $var wire 1 IG" empty_r $end + $var wire 1 QG" full_r $end + $var wire 76 ac" head_r [75:0] $end + $var wire 2 Cd" rd_ptr_next_r [1:0] $end + $var wire 2 ;d" rd_ptr_r [1:0] $end + $var wire 2 3d" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 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+1,9265 @@ +$version Generated by VerilatedVcd $end +$date Mon Jul 13 23:43:12 2020 + $end +$timescale 1ns $end + + $scope module TOP $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 Cl" snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module VX_cache $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 1o" DRAM_TAG_WIDTH [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 9o" NUM_SNP_REQUESTS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 wn" SNP_FWD_TAG_WIDTH [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 128 }i" core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 ?j" core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 28 9k" dram_req_tag [27:0] $end + $var wire 1 Wj" dram_req_valid $end + $var wire 128 Qk" dram_rsp_data [127:0] $end + $var wire 1 yk" dram_rsp_ready $end + $var wire 28 qk" dram_rsp_tag [27:0] $end + $var wire 1 Ik" dram_rsp_valid $end + $var wire 4 Y+ per_bank_core_req_ready [3:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 -- per_bank_dram_fill_rsp_ready [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 4 1/ per_bank_snp_req_ready [3:0] $end + $var wire 4 ; per_bank_snp_rsp_ready [3:0] $end + $var wire 112 A/ per_bank_snp_rsp_tag [111:0] $end + $var wire 4 9/ per_bank_snp_rsp_valid [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $var wire 1 [h" reset $end + $var wire 2 Em" snp_fwdin_ready [1:0] $end + $var wire 2 =m" snp_fwdin_tag [1:0] $end + $var wire 2 5m" snp_fwdin_valid [1:0] $end + $var wire 56 kl" snp_fwdout_addr [55:0] $end + $var wire 2 {l" snp_fwdout_invalidate [1:0] $end + $var wire 2 -m" snp_fwdout_ready [1:0] $end + $var wire 2 %m" snp_fwdout_tag [1:0] $end + $var wire 2 cl" snp_fwdout_valid [1:0] $end + $var wire 28 +l" snp_req_addr [27:0] $end + $var wire 28 +l" snp_req_addr_qual [27:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 3l" snp_req_invalidate_qual $end + $var wire 1 Cl" snp_req_ready $end + $var wire 1 Mm" snp_req_ready_qual $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 28 ;l" snp_req_tag_qual [27:0] $end + $var wire 1 #l" snp_req_valid $end + $var wire 1 #l" snp_req_valid_qual $end + $var wire 1 [l" snp_rsp_ready $end + $var wire 28 Sl" snp_rsp_tag [27:0] $end + $var wire 1 Kl" snp_rsp_valid $end + $scope module cache_core_req_bank_sel $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 1 mi" core_req_ready $end + $var wire 4 ch" core_req_valid [3:0] $end + $var wire 32 Ao" i [31:0] $end + $var wire 4 Y+ per_bank_ready [3:0] $end + $var wire 16 # per_bank_valid [15:0] $end + $scope module genblk2 $end + $var wire 4 e! per_bank_ready_sel [3:0] $end + $upscope $end + $upscope $end + $scope module cache_core_rsp_merge $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 Y7 core_rsp_data [127:0] $end + $var wire 1 Oj" core_rsp_ready $end + $var wire 42 y7 core_rsp_tag [41:0] $end + $var wire 4 ui" core_rsp_valid [3:0] $end + $var wire 1 ;8 grant_valid $end + $var wire 32 Ao" i [31:0] $end + $var wire 2 38 main_bank_index [1:0] $end + $var wire 128 q+ per_bank_core_rsp_data [127:0] $end + $var wire 4 +8 per_bank_core_rsp_pop_unqual [3:0] $end + $var wire 4 + per_bank_core_rsp_ready [3:0] $end + $var wire 168 3, per_bank_core_rsp_tag [167:0] $end + $var wire 8 i+ per_bank_core_rsp_tid [7:0] $end + $var wire 4 a+ per_bank_core_rsp_valid [3:0] $end + $var wire 1 [h" reset $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 38 grant_index [1:0] $end + $var wire 4 C8 grant_onehot [3:0] $end + $var wire 1 ;8 grant_valid $end + $var wire 4 a+ requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 C8 grant_onehot_r [3:0] $end + $var wire 4 S8 late_value [3:0] $end + $var wire 1 [2! refill $end + $var wire 4 c2! refill_original [3:0] $end + $var wire 4 a+ refill_value [3:0] $end + $var wire 4 S2! requests_use [3:0] $end + $var wire 4 K8 update_value [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 S2! data_in [3:0] $end + $var wire 2 38 data_out [1:0] $end + $var wire 32 [8 i [31:0] $end + $var wire 1 ;8 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cache_dram_req_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 16 gj" dram_req_byteen [15:0] $end + $var wire 128 wj" dram_req_data [127:0] $end + $var wire 1 Ak" dram_req_ready $end + $var wire 1 _j" dram_req_rw $end + $var wire 1 Wj" dram_req_valid $end + $var wire 2 s4 dwb_bank [1:0] $end + $var wire 1 K4 dwb_valid $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 M- per_bank_dram_wb_req_addr [111:0] $end + $var wire 64 =- per_bank_dram_wb_req_byteen [63:0] $end + $var wire 512 m- per_bank_dram_wb_req_data [511:0] $end + $var wire 4 3 per_bank_dram_wb_req_ready [3:0] $end + $var wire 4 5- per_bank_dram_wb_req_valid [3:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $scope module dram_fill_arb $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 c4 dfqq_empty $end + $var wire 1 {.! dfqq_full $end + $var wire 1 m! dfqq_pop $end + $var wire 1 k4 dfqq_push $end + $var wire 1 S4 dfqq_req $end + $var wire 28 [4 dfqq_req_addr [27:0] $end + $var wire 1 u/! o_empty $end + $var wire 1 /6 out_empty $end + $var wire 112 =5 out_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 55 out_per_bank_dram_fill_req_valid [3:0] $end + $var wire 112 k, per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 c, per_bank_dram_fill_req_valid [3:0] $end + $var wire 1 /* pop_qual $end + $var wire 1 76 push_qual $end + $var wire 112 e5 qual_bank_dram_fill_req_addr [111:0] $end + $var wire 1 G6 qual_has_request $end + $var wire 2 ?6 qual_request_index [1:0] $end + $var wire 1 [h" reset $end + $var wire 4 '6 updated_bank_dram_fill_req_valid [3:0] $end + $var wire 1 }/! use_empty $end + $var wire 112 U/! use_per_bank_dram_fill_req_addr [111:0] $end + $var wire 4 M/! use_per_bank_dram_fill_req_valid [3:0] $end + $var wire 4 ]5 use_per_bqual_bank_dram_fill_req_valid [3:0] $end + $scope module dfqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Qo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 116 O6 data_in [115:0] $end + $var wire 116 o6 data_out [115:0] $end + $var wire 1 u/! empty $end + $var wire 1 {.! full $end + $var wire 1 /* pop $end + $var wire 1 76 push $end + $var wire 1 u! reading $end + $var wire 1 [h" reset $end + $var wire 3 '0! size [2:0] $end + $var wire 3 '0! size_r [2:0] $end + $var wire 1 17 writing $end + $scope module genblk3 $end + $var wire 116 /0! data(0) [115:0] $end + $var wire 116 30! data(1) [115:0] $end + $var wire 116 70! data(2) [115:0] $end + $var wire 116 ;0! data(3) [115:0] $end + $scope module genblk2 $end + $var wire 1 K2! bypass_r $end + $var wire 116 q1! curr_r [115:0] $end + $var wire 1 u/! empty_r $end + $var wire 1 {.! full_r $end + $var wire 116 Q1! head_r [115:0] $end + $var wire 2 C2! rd_ptr_next_r [1:0] $end + $var wire 2 ;2! rd_ptr_r [1:0] $end + $var wire 2 32! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 ?6 grant_index [1:0] $end + $var wire 4 97 grant_onehot [3:0] $end + $var wire 1 G6 grant_valid $end + $var wire 4 ]5 requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 97 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 ]5 data_in [3:0] $end + $var wire 2 ?6 data_out [1:0] $end + $var wire 32 A7 i [31:0] $end + $var wire 1 G6 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module prfqq $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 wn" PRFQ_SIZE [31:0] $end + $var wire 32 Wn" PRFQ_STRIDE [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 5/! current_addr [27:0] $end + $var wire 1 =/! current_empty $end + $var wire 1 -/! current_full $end + $var wire 1 -/! current_valid $end + $var wire 1 Gn" dram_req $end + $var wire 28 oj" dram_req_addr [27:0] $end + $var wire 28 s.! pref_addr [27:0] $end + $var wire 1 Io" pref_pop $end + $var wire 1 Io" pref_valid $end + $var wire 1 [h" reset $end + $var wire 1 {4 update_use $end + $var wire 28 s.! use_addr [27:0] $end + $var wire 2 %/! use_valid [1:0] $end + $scope module pfq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 1o" DATAW [31:0] $end + $var wire 32 wn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 28 oj" data_in [27:0] $end + $var wire 28 5/! data_out [27:0] $end + $var wire 1 =/! empty $end + $var wire 1 -/! full $end + $var wire 1 {4 pop $end + $var wire 1 On" push $end + $var wire 1 %5 reading $end + $var wire 1 [h" reset $end + $var wire 1 E/! size [0:0] $end + $var wire 1 E/! size_r [0:0] $end + $var wire 1 -5 writing $end + $scope module genblk2 $end + $var wire 28 5/! head_r [27:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_dwb $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 s4 grant_index [1:0] $end + $var wire 4 I7 grant_onehot [3:0] $end + $var wire 1 K4 grant_valid $end + $var wire 4 5- requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 I7 grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 5- data_in [3:0] $end + $var wire 2 s4 data_out [1:0] $end + $var wire 32 Q7 i [31:0] $end + $var wire 1 K4 valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(0) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 Q-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 C curr_bank_core_req_valid [3:0] $end + $var wire 32 i/ curr_bank_core_rsp_data [31:0] $end + $var wire 1 K curr_bank_core_rsp_ready $end + $var wire 42 q/ curr_bank_core_rsp_tag [41:0] $end + $var wire 2 a/ curr_bank_core_rsp_tid [1:0] $end + $var wire 1 1-! curr_bank_core_rsp_valid $end + $var wire 26 A-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 #0 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 9-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 Um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 ;0 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 30 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 C0 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 S curr_bank_dram_wb_req_ready $end + $var wire 1 +0 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 I-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 em" curr_bank_snp_req_valid $end + $var wire 1 [ curr_bank_snp_rsp_ready $end + $var wire 28 k0 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 c0 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 == addr_st1(0) [25:0] $end + $var wire 26 ;@ addr_st1e [25:0] $end + $var wire 26 A-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 Q-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 C core_req_valid [3:0] $end + $var wire 32 i/ core_rsp_data [31:0] $end + $var wire 1 K core_rsp_ready $end + $var wire 42 q/ core_rsp_tag [41:0] $end + $var wire 2 a/ core_rsp_tid [1:0] $end + $var wire 1 1-! core_rsp_valid $end + $var wire 32 )5! cwbq_data [31:0] $end + $var wire 1 [6! cwbq_empty $end + $var wire 1 c6! cwbq_full $end + $var wire 1 ?* cwbq_pop $end + $var wire 1 {@ cwbq_push $end + $var wire 1 9; cwbq_push_stall $end + $var wire 1 %A cwbq_push_unqual $end + $var wire 42 G4! cwbq_tag [41:0] $end + $var wire 2 ?4! cwbq_tid [1:0] $end + $var wire 26 M9 dfpq_addr_st0 [25:0] $end + $var wire 1 {2! dfpq_empty $end + $var wire 128 U9 dfpq_filldata_st0 [127:0] $end + $var wire 1 %3! dfpq_full $end + $var wire 1 E9 dfpq_pop $end + $var wire 1 q; dfpq_pop_unqual $end + $var wire 1 w> dirty_st1e $end + $var wire 1 Y5! dirty_st2 $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 16 a5! dirtyb_st2 [15:0] $end + $var wire 26 A-! dram_fill_req_addr [25:0] $end + $var wire 1 c@ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 I; dram_fill_req_stall $end + $var wire 1 -A dram_fill_req_unqual $end + $var wire 1 #0 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 9-! dram_fill_rsp_ready $end + $var wire 1 Um" dram_fill_rsp_valid $end + $var wire 26 ;0 dram_wb_req_addr [25:0] $end + $var wire 16 30 dram_wb_req_byteen [15:0] $end + $var wire 128 C0 dram_wb_req_data [127:0] $end + $var wire 1 }! dram_wb_req_fire $end + $var wire 1 S dram_wb_req_ready $end + $var wire 1 +0 dram_wb_req_valid $end + $var wire 1 -7! dwbq_dual_valid_sel $end + $var wire 1 k6! dwbq_empty $end + $var wire 1 s6! dwbq_full $end + $var wire 1 =A dwbq_is_dwb_in $end + $var wire 1 MA dwbq_is_dwb_out $end + $var wire 1 EA dwbq_is_snp_in $end + $var wire 1 UA dwbq_is_snp_out $end + $var wire 1 G* dwbq_pop $end + $var wire 1 5A dwbq_push $end + $var wire 1 A; dwbq_push_stall $end + $var wire 1 ]A dwbq_push_unqual $end + $var wire 26 {6! dwbq_req_addr [25:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 #6! fill_saw_dirty_st2 $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 i; going_to_write_st1(0) $end + $var wire 49 U= inst_meta_st1(0) [48:0] $end + $var wire 49 i5! inst_meta_st2 [48:0] $end + $var wire 1 Y; is_fill_in_pipe $end + $var wire 1 a; is_fill_st1(0) $end + $var wire 1 g4! is_fill_st2 $end + $var wire 1 7> is_mrvq_st1(0) $end + $var wire 1 +@ is_mrvq_st1e $end + $var wire 1 +@ is_mrvq_st1e_st2 $end + $var wire 1 C6! is_mrvq_st2 $end + $var wire 1 '> is_snp_st1(0) $end + $var wire 1 Y? is_snp_st1e $end + $var wire 1 +6! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 1 y? miss_add_because_miss $end + $var wire 1 ;6! miss_add_because_pending $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 s@ miss_add_is_mrvq $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 1 c@ miss_add_unqual $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 1 o> miss_st1e $end + $var wire 1 Q5! miss_st2 $end + $var wire 26 ]3! mrvq_addr_st0 [25:0] $end + $var wire 4 '4! mrvq_byteen_st0 [3:0] $end + $var wire 1 E3! mrvq_full $end + $var wire 1 S@ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 [@ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 1 K@ mrvq_init_ready_state_st2 $end + $var wire 1 S6! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 /4! mrvq_is_snp_st0 $end + $var wire 1 o: mrvq_pending_hazard_st1e $end + $var wire 1 W: mrvq_pop $end + $var wire 1 _: mrvq_pop_unqual $end + $var wire 1 1; mrvq_push_stall $end + $var wire 1 3@ mrvq_recover_ready_state_st1e $end + $var wire 1 K6! mrvq_recover_ready_state_st2 $end + $var wire 1 g: mrvq_rw_st0 $end + $var wire 1 74! mrvq_snp_invalidate_st0 $end + $var wire 1 M3! mrvq_stop $end + $var wire 42 u3! mrvq_tag_st0 [41:0] $end + $var wire 2 U3! mrvq_tid_st0 [1:0] $end + $var wire 1 _: mrvq_valid_st0 $end + $var wire 32 m3! mrvq_writeword_st0 [31:0] $end + $var wire 2 e3! mrvq_wsel_st0 [1:0] $end + $var wire 26 3< qual_addr_st0 [25:0] $end + $var wire 1 {< qual_going_to_write_st0 $end + $var wire 49 k< qual_inst_meta_st0 [48:0] $end + $var wire 1 q; qual_is_fill_st0 $end + $var wire 1 _: qual_is_mrvq_st0 $end + $var wire 1 %= qual_is_snp_st0 $end + $var wire 1 -= qual_snp_invalidate_st0 $end + $var wire 1 +< qual_valid_st0 $end + $var wire 1 C@ qual_valid_st1e_2 $end + $var wire 128 K< qual_writedata_st0 [127:0] $end + $var wire 32 C< qual_writeword_st0 [31:0] $end + $var wire 2 ;< qual_wsel_st0 [1:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 128 15! readdata_st2 [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 20 y5! readtag_st2 [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 32 )5! readword_st2 [31:0] $end + $var wire 1 ); recover_mrvq_state_st2 $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 y; reqq_pop_unqual $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 /> snp_invalidate_st1(0) $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 36! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 I-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 em" snp_req_valid $end + $var wire 1 '" snp_rsp_fire $end + $var wire 1 [ snp_rsp_ready $end + $var wire 28 k0 snp_rsp_tag [27:0] $end + $var wire 1 c0 snp_rsp_valid $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 ;6! snp_to_mrvq_st2 $end + $var wire 26 -9 snrq_addr_st0 [25:0] $end + $var wire 1 k2! snrq_empty $end + $var wire 1 s2! snrq_full $end + $var wire 1 59 snrq_invalidate_st0 $end + $var wire 1 %9 snrq_pop $end + $var wire 1 #< snrq_pop_unqual $end + $var wire 28 =9 snrq_tag_st0 [27:0] $end + $var wire 28 %7! snrq_tag_st2 [27:0] $end + $var wire 1 w: st2_pending_hazard_st1e $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 42 )? tag_st1e [41:0] $end + $var wire 2 9? tid_st1e [1:0] $end + $var wire 1 5= valid_st1(0) $end + $var wire 1 #@ valid_st1e $end + $var wire 1 o4! valid_st2 $end + $var wire 128 e= writedata_st1(0) [127:0] $end + $var wire 32 M= writeword_st1(0) [31:0] $end + $var wire 32 !5! writeword_st2 [31:0] $end + $var wire 2 E= wsel_st1(0) [1:0] $end + $var wire 2 w4! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Yo" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 'P! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 AQ! dequeue_index [3:0] $end + $var wire 1 _: dequeue_possible $end + $var wire 4 QQ! enqueue_index [3:0] $end + $var wire 1 aQ! enqueue_possible $end + $var wire 26 ;@ fill_addr_st1 [25:0] $end + $var wire 4 IQ! head_ptr [3:0] $end + $var wire 1 IK increment_head $end + $var wire 1 eE is_fill_st1 $end + $var wire 1 s@ is_mrvq $end + $var wire 16 wJ make_ready [15:0] $end + $var wire 16 !K make_ready_push [15:0] $end + $var wire 85 }K! metadata_table(0) [84:0] $end + $var wire 85 "L! metadata_table(1) [84:0] $end + $var wire 85 =L! metadata_table(10) [84:0] $end + $var wire 85 @L! metadata_table(11) [84:0] $end + $var wire 85 CL! metadata_table(12) [84:0] $end + $var wire 85 FL! metadata_table(13) [84:0] $end + $var wire 85 IL! metadata_table(14) [84:0] $end + $var wire 85 LL! metadata_table(15) [84:0] $end + $var wire 85 %L! metadata_table(2) [84:0] $end + $var wire 85 (L! metadata_table(3) [84:0] $end + $var wire 85 +L! metadata_table(4) [84:0] $end + $var wire 85 .L! metadata_table(5) [84:0] $end + $var wire 85 1L! metadata_table(6) [84:0] $end + $var wire 85 4L! metadata_table(7) [84:0] $end + $var wire 85 7L! metadata_table(8) [84:0] $end + $var wire 85 :L! metadata_table(9) [84:0] $end + $var wire 1 k@ miss_add $end + $var wire 26 A-! miss_add_addr [25:0] $end + $var wire 4 _4! miss_add_byteen [3:0] $end + $var wire 32 !5! miss_add_data [31:0] $end + $var wire 1 +6! miss_add_is_snp $end + $var wire 1 W4! miss_add_rw $end + $var wire 1 36! miss_add_snp_invalidate $end + $var wire 42 G4! miss_add_tag [41:0] $end + $var wire 2 ?4! miss_add_tid [1:0] $end + $var wire 2 w4! miss_add_wsel [1:0] $end + $var wire 26 ]3! miss_resrv_addr_st0 [25:0] $end + $var wire 4 '4! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 m3! miss_resrv_data_st0 [31:0] $end + $var wire 1 E3! miss_resrv_full $end + $var wire 1 /4! miss_resrv_is_snp_st0 $end + $var wire 1 W: miss_resrv_pop $end + $var wire 1 g: miss_resrv_rw_st0 $end + $var wire 1 74! miss_resrv_snp_invalidate_st0 $end + $var wire 1 M3! miss_resrv_stop $end + $var wire 42 u3! miss_resrv_tag_st0 [41:0] $end + $var wire 2 U3! miss_resrv_tid_st0 [1:0] $end + $var wire 1 _: miss_resrv_valid_st0 $end + $var wire 2 e3! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 K@ mrvq_init_ready_state $end + $var wire 1 9K mrvq_pop $end + $var wire 1 1K mrvq_push $end + $var wire 1 o: pending_hazard $end + $var wire 1 YK qual_mrvq_init $end + $var wire 16 9Q! ready_table [15:0] $end + $var wire 1 AK recover_state $end + $var wire 1 [h" reset $end + $var wire 4 AQ! schedule_ptr [3:0] $end + $var wire 5 YQ! size [4:0] $end + $var wire 4 QQ! tail_ptr [3:0] $end + $var wire 1 QK update_ready $end + $var wire 16 )K valid_address_match [15:0] $end + $var wire 16 1Q! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 C bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 eC! o_empty $end + $var wire 1 YC out_empty $end + $var wire 120 gB out_per_addr [119:0] $end + $var wire 16 _B out_per_byteen [15:0] $end + $var wire 4 WB out_per_rw [3:0] $end + $var wire 42 IC out_per_tag [41:0] $end + $var wire 4 OB out_per_valids [3:0] $end + $var wire 128 )C out_per_writedata [127:0] $end + $var wire 1 aC pop_qual $end + $var wire 1 O* push_qual $end + $var wire 120 %C! qual_addr [119:0] $end + $var wire 16 {B! qual_byteen [15:0] $end + $var wire 1 ': qual_has_request $end + $var wire 2 /: qual_request_index [1:0] $end + $var wire 4 sB! qual_rw [3:0] $end + $var wire 42 53! qual_tag [41:0] $end + $var wire 4 kB! qual_valids [3:0] $end + $var wire 128 EC! qual_writedata [127:0] $end + $var wire 4 iC real_out_per_valids [3:0] $end + $var wire 1 }9 reqq_empty $end + $var wire 1 -3! reqq_full $end + $var wire 1 u9 reqq_pop $end + $var wire 1 7* reqq_push $end + $var wire 30 G: reqq_req_addr_st0 [29:0] $end + $var wire 4 ?: reqq_req_byteen_st0 [3:0] $end + $var wire 1 7: reqq_req_rw_st0 $end + $var wire 1 ': reqq_req_st0 $end + $var wire 42 53! reqq_req_tag_st0 [41:0] $end + $var wire 2 /: reqq_req_tid_st0 [1:0] $end + $var wire 32 O: reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 mC! use_empty $end + $var wire 120 %C! use_per_addr [119:0] $end + $var wire 16 {B! use_per_byteen [15:0] $end + $var wire 4 sB! use_per_rw [3:0] $end + $var wire 42 53! use_per_tag [41:0] $end + $var wire 4 kB! use_per_valids [3:0] $end + $var wire 128 EC! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 w" data_in [313:0] $end + $var wire 314 qC data_out [313:0] $end + $var wire 1 eC! empty $end + $var wire 1 -3! full $end + $var wire 1 aC pop $end + $var wire 1 O* push $end + $var wire 1 cD reading $end + $var wire 1 [h" reset $end + $var wire 3 uC! size [2:0] $end + $var wire 3 uC! size_r [2:0] $end + $var wire 1 i# writing $end + $scope module genblk3 $end + $var wire 314 }C! data(0) [313:0] $end + $var wire 314 )D! data(1) [313:0] $end + $var wire 314 3D! data(2) [313:0] $end + $var wire 314 =D! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 AI! bypass_r $end + $var wire 314 7H! curr_r [313:0] $end + $var wire 1 eC! empty_r $end + $var wire 1 -3! full_r $end + $var wire 314 EG! head_r [313:0] $end + $var wire 2 9I! rd_ptr_next_r [1:0] $end + $var wire 2 1I! rd_ptr_r [1:0] $end + $var wire 2 )I! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 /: grant_index [1:0] $end + $var wire 4 kD grant_onehot [3:0] $end + $var wire 1 ': grant_valid $end + $var wire 4 kB! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 kD grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 kB! data_in [3:0] $end + $var wire 2 /: data_out [1:0] $end + $var wire 32 sD i [31:0] $end + $var wire 1 ': valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 aK data_in [75:0] $end + $var wire 76 yK data_out [75:0] $end + $var wire 1 [6! empty $end + $var wire 1 c6! full $end + $var wire 1 ?* pop $end + $var wire 1 {@ push $end + $var wire 1 q# reading $end + $var wire 1 [h" reset $end + $var wire 3 iQ! size [2:0] $end + $var wire 3 iQ! size_r [2:0] $end + $var wire 1 3L writing $end + $scope module genblk3 $end + $var wire 76 qQ! data(0) [75:0] $end + $var wire 76 tQ! data(1) [75:0] $end + $var wire 76 wQ! data(2) [75:0] $end + $var wire 76 zQ! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 ]S! bypass_r $end + $var wire 76 -S! curr_r [75:0] $end + $var wire 1 [6! empty_r $end + $var wire 1 c6! full_r $end + $var wire 76 sR! head_r [75:0] $end + $var wire 2 US! rd_ptr_next_r [1:0] $end + $var wire 2 MS! rd_ptr_r [1:0] $end + $var wire 2 ES! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 G" data_in [153:0] $end + $var wire 154 }A data_out [153:0] $end + $var wire 1 {2! empty $end + $var wire 1 %3! full $end + $var wire 1 E9 pop $end + $var wire 1 Um" push $end + $var wire 1 GB reading $end + $var wire 1 [h" reset $end + $var wire 5 c:! size [4:0] $end + $var wire 5 c:! size_r [4:0] $end + $var wire 1 o" writing $end + $scope module genblk3 $end + $var wire 154 k:! data(0) [153:0] $end + $var wire 154 p:! data(1) [153:0] $end + $var wire 154 ?;! data(10) [153:0] $end + $var wire 154 D;! data(11) [153:0] $end + $var wire 154 I;! data(12) [153:0] $end + $var wire 154 N;! data(13) [153:0] $end + $var wire 154 S;! data(14) [153:0] $end + $var wire 154 X;! data(15) [153:0] $end + $var wire 154 u:! data(2) [153:0] $end + $var wire 154 z:! data(3) [153:0] $end + $var wire 154 !;! data(4) [153:0] $end + $var wire 154 &;! data(5) [153:0] $end + $var wire 154 +;! data(6) [153:0] $end + $var wire 154 0;! data(7) [153:0] $end + $var wire 154 5;! data(8) [153:0] $end + $var wire 154 :;! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 cB! bypass_r $end + $var wire 154 #B! curr_r [153:0] $end + $var wire 1 {2! empty_r $end + $var wire 1 %3! full_r $end + $var wire 154 YA! head_r [153:0] $end + $var wire 4 [B! rd_ptr_next_r [3:0] $end + $var wire 4 SB! rd_ptr_r [3:0] $end + $var wire 4 KB! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 ;L data_in [199:0] $end + $var wire 200 sL data_out [199:0] $end + $var wire 1 k6! empty $end + $var wire 1 s6! full $end + $var wire 1 G* pop $end + $var wire 1 5A push $end + $var wire 1 y# reading $end + $var wire 1 [h" reset $end + $var wire 3 eS! size [2:0] $end + $var wire 3 eS! size_r [2:0] $end + $var wire 1 MM writing $end + $scope module genblk3 $end + $var wire 200 mS! data(0) [199:0] $end + $var wire 200 tS! data(1) [199:0] $end + $var wire 200 {S! data(2) [199:0] $end + $var wire 200 $T! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 ]W! bypass_r $end + $var wire 200 kV! curr_r [199:0] $end + $var wire 1 k6! empty_r $end + $var wire 1 s6! full_r $end + $var wire 200 3V! head_r [199:0] $end + $var wire 2 UW! rd_ptr_next_r [1:0] $end + $var wire 2 MW! rd_ptr_r [1:0] $end + $var wire 2 EW! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 {D in [242:0] $end + $var wire 243 II! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 243 II! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 /" data_in [54:0] $end + $var wire 55 eA data_out [54:0] $end + $var wire 1 k2! empty $end + $var wire 1 s2! full $end + $var wire 1 %9 pop $end + $var wire 1 em" push $end + $var wire 1 uA reading $end + $var wire 1 [h" reset $end + $var wire 5 57! size [4:0] $end + $var wire 5 57! size_r [4:0] $end + $var wire 1 ?" writing $end + $scope module genblk3 $end + $var wire 55 =7! data(0) [54:0] $end + $var wire 55 ?7! data(1) [54:0] $end + $var wire 55 Q7! data(10) [54:0] $end + $var wire 55 S7! data(11) [54:0] $end + $var wire 55 U7! data(12) [54:0] $end + $var wire 55 W7! data(13) [54:0] $end + $var wire 55 Y7! data(14) [54:0] $end + $var wire 55 [7! data(15) [54:0] $end + $var wire 55 A7! data(2) [54:0] $end + $var wire 55 C7! data(3) [54:0] $end + $var wire 55 E7! data(4) [54:0] $end + $var wire 55 G7! data(5) [54:0] $end + $var wire 55 I7! data(6) [54:0] $end + $var wire 55 K7! data(7) [54:0] $end + $var wire 55 M7! data(8) [54:0] $end + $var wire 55 O7! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 [:! bypass_r $end + $var wire 55 3:! curr_r [54:0] $end + $var wire 1 k2! empty_r $end + $var wire 1 s2! full_r $end + $var wire 55 #:! head_r [54:0] $end + $var wire 4 S:! rd_ptr_next_r [3:0] $end + $var wire 4 K:! rd_ptr_r [3:0] $end + $var wire 4 C:! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 'J in [315:0] $end + $var wire 316 -K! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 316 -K! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 yG data_write [127:0] $end + $var wire 1 w> dirty_st1e $end + $var wire 16 !? dirtyb_st1e [15:0] $end + $var wire 1 Q? fill_saw_dirty_st1e $end + $var wire 1 o> fill_sent $end + $var wire 1 %I force_core_miss $end + $var wire 1 !; force_request_miss_st1e $end + $var wire 1 ;H invalidate_line $end + $var wire 1 Y? is_snp_st1e $end + $var wire 4 I? mem_byteen_st1e [3:0] $end + $var wire 1 A? mem_rw_st1e $end + $var wire 1 o> miss_st1e $end + $var wire 1 q? mrvq_init_ready_state_st1e $end + $var wire 128 AG qual_read_data_st1 [127:0] $end + $var wire 1 )G qual_read_dirty_st1 $end + $var wire 16 1G qual_read_dirtyb_st1 [15:0] $end + $var wire 20 9G qual_read_tag_st1 [19:0] $end + $var wire 1 !G qual_read_valid_st1 $end + $var wire 128 _F read_data_st1c(0) [127:0] $end + $var wire 1 GF read_dirty_st1c(0) $end + $var wire 16 OF read_dirtyb_st1c(0) [15:0] $end + $var wire 20 WF read_tag_st1c(0) [19:0] $end + $var wire 1 ?F read_valid_st1c(0) $end + $var wire 6 ]E readaddr_st10 [5:0] $end + $var wire 128 G> readdata_st1e [127:0] $end + $var wire 20 g> readtag_st1e [19:0] $end + $var wire 32 ?> readword_st1e [31:0] $end + $var wire 1 {H real_miss $end + $var wire 1 KH real_writefill $end + $var wire 1 kH req_invalid $end + $var wire 1 sH req_miss $end + $var wire 1 [h" reset $end + $var wire 1 cH should_write $end + $var wire 1 ;H snoop_hit_no_pending $end + $var wire 1 a? snp_invalidate_st1e $end + $var wire 1 i? snp_to_mrvq_st1e $end + $var wire 1 Q; stall $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 1 CH tags_match $end + $var wire 128 G> use_read_data_st1e [127:0] $end + $var wire 1 iG use_read_dirty_st1e $end + $var wire 16 !? use_read_dirtyb_st1e [15:0] $end + $var wire 20 g> use_read_tag_st1e [19:0] $end + $var wire 1 aG use_read_valid_st1e $end + $var wire 128 yG use_write_data [127:0] $end + $var wire 16 qG use_write_enable [15:0] $end + $var wire 1 #@ valid_req_st1e $end + $var wire 16 [H we [15:0] $end + $var wire 2 7F wordsel_st1e [1:0] $end + $var wire 26 ;@ writeaddr_st1e [25:0] $end + $var wire 128 uE writedata_st1e [127:0] $end + $var wire 1 eE writefill_st1e $end + $var wire 6 ]E writeladdr_st1e [5:0] $end + $var wire 20 SH writetag_st1e [19:0] $end + $var wire 32 mE writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 -I normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 5I normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 =I normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 EI normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 UI in [165:0] $end + $var wire 166 UI out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall $end + $var wire 166 [J! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 +J! dirty [63:0] $end + $var wire 1 MI do_write $end + $var wire 1 o> fill_sent $end + $var wire 32 KJ! i [31:0] $end + $var wire 1 ;H invalidate $end + $var wire 32 SJ! j [31:0] $end + $var wire 6 ]E read_addr [5:0] $end + $var wire 128 AG read_data [127:0] $end + $var wire 1 )G read_dirty $end + $var wire 16 1G read_dirtyb [15:0] $end + $var wire 20 9G read_tag [19:0] $end + $var wire 1 !G read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Q; stall_bank_pipe $end + $var wire 20 SH tag_index [19:0] $end + $var wire 64 ;J! valid [63:0] $end + $var wire 6 ]E write_addr [5:0] $end + $var wire 128 yG write_data [127:0] $end + $var wire 16 qG write_enable [15:0] $end + $var wire 1 KH write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(1) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 y-! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 c curr_bank_core_req_valid [3:0] $end + $var wire 32 {0 curr_bank_core_rsp_data [31:0] $end + $var wire 1 k curr_bank_core_rsp_ready $end + $var wire 42 %1 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 s0 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 Y-! curr_bank_core_rsp_valid $end + $var wire 26 i-! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 51 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 a-! curr_bank_dram_fill_rsp_ready $end + $var wire 1 um" curr_bank_dram_fill_rsp_valid $end + $var wire 26 M1 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 E1 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 U1 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 s curr_bank_dram_wb_req_ready $end + $var wire 1 =1 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 q-! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 }m" curr_bank_snp_req_valid $end + $var wire 1 { curr_bank_snp_rsp_ready $end + $var wire 28 }1 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 u1 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 mQ addr_st1(0) [25:0] $end + $var wire 26 kT addr_st1e [25:0] $end + $var wire 26 i-! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 y-! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 c core_req_valid [3:0] $end + $var wire 32 {0 core_rsp_data [31:0] $end + $var wire 1 k core_rsp_ready $end + $var wire 42 %1 core_rsp_tag [41:0] $end + $var wire 2 s0 core_rsp_tid [1:0] $end + $var wire 1 Y-! core_rsp_valid $end + $var wire 32 #Z! cwbq_data [31:0] $end + $var wire 1 U[! cwbq_empty $end + $var wire 1 ][! cwbq_full $end + $var wire 1 _* cwbq_pop $end + $var wire 1 MU cwbq_push $end + $var wire 1 iO cwbq_push_stall $end + $var wire 1 UU cwbq_push_unqual $end + $var wire 42 AY! cwbq_tag [41:0] $end + $var wire 2 9Y! cwbq_tid [1:0] $end + $var wire 26 }M dfpq_addr_st0 [25:0] $end + $var wire 1 uW! dfpq_empty $end + $var wire 128 'N dfpq_filldata_st0 [127:0] $end + $var wire 1 }W! dfpq_full $end + $var wire 1 uM dfpq_pop $end + $var wire 1 CP dfpq_pop_unqual $end + $var wire 1 IS dirty_st1e $end + $var wire 1 SZ! dirty_st2 $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 16 [Z! dirtyb_st2 [15:0] $end + $var wire 26 i-! dram_fill_req_addr [25:0] $end + $var wire 1 5U dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 yO dram_fill_req_stall $end + $var wire 1 ]U dram_fill_req_unqual $end + $var wire 1 51 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 a-! dram_fill_rsp_ready $end + $var wire 1 um" dram_fill_rsp_valid $end + $var wire 26 M1 dram_wb_req_addr [25:0] $end + $var wire 16 E1 dram_wb_req_byteen [15:0] $end + $var wire 128 U1 dram_wb_req_data [127:0] $end + $var wire 1 #$ dram_wb_req_fire $end + $var wire 1 s dram_wb_req_ready $end + $var wire 1 =1 dram_wb_req_valid $end + $var wire 1 '\! dwbq_dual_valid_sel $end + $var wire 1 e[! dwbq_empty $end + $var wire 1 m[! dwbq_full $end + $var wire 1 mU dwbq_is_dwb_in $end + $var wire 1 }U dwbq_is_dwb_out $end + $var wire 1 uU dwbq_is_snp_in $end + $var wire 1 'V dwbq_is_snp_out $end + $var wire 1 g* dwbq_pop $end + $var wire 1 eU dwbq_push $end + $var wire 1 qO dwbq_push_stall $end + $var wire 1 /V dwbq_push_unqual $end + $var wire 26 u[! dwbq_req_addr [25:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 {Z! fill_saw_dirty_st2 $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 ;P going_to_write_st1(0) $end + $var wire 49 'R inst_meta_st1(0) [48:0] $end + $var wire 49 cZ! inst_meta_st2 [48:0] $end + $var wire 1 +P is_fill_in_pipe $end + $var wire 1 3P is_fill_st1(0) $end + $var wire 1 aY! is_fill_st2 $end + $var wire 1 gR is_mrvq_st1(0) $end + $var wire 1 [T is_mrvq_st1e $end + $var wire 1 [T is_mrvq_st1e_st2 $end + $var wire 1 =[! is_mrvq_st2 $end + $var wire 1 WR is_snp_st1(0) $end + $var wire 1 +T is_snp_st1e $end + $var wire 1 %[! is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 1 KT miss_add_because_miss $end + $var wire 1 5[! miss_add_because_pending $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 EU miss_add_is_mrvq $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 1 5U miss_add_unqual $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 1 AS miss_st1e $end + $var wire 1 KZ! miss_st2 $end + $var wire 26 WX! mrvq_addr_st0 [25:0] $end + $var wire 4 !Y! mrvq_byteen_st0 [3:0] $end + $var wire 1 ?X! mrvq_full $end + $var wire 1 %U mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 -U mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 1 {T mrvq_init_ready_state_st2 $end + $var wire 1 M[! mrvq_init_ready_state_unqual_st2 $end + $var wire 1 )Y! mrvq_is_snp_st0 $end + $var wire 1 AO mrvq_pending_hazard_st1e $end + $var wire 1 )O mrvq_pop $end + $var wire 1 1O mrvq_pop_unqual $end + $var wire 1 aO mrvq_push_stall $end + $var wire 1 cT mrvq_recover_ready_state_st1e $end + $var wire 1 E[! mrvq_recover_ready_state_st2 $end + $var wire 1 9O mrvq_rw_st0 $end + $var wire 1 1Y! mrvq_snp_invalidate_st0 $end + $var wire 1 GX! mrvq_stop $end + $var wire 42 oX! mrvq_tag_st0 [41:0] $end + $var wire 2 OX! mrvq_tid_st0 [1:0] $end + $var wire 1 1O mrvq_valid_st0 $end + $var wire 32 gX! mrvq_writeword_st0 [31:0] $end + $var wire 2 _X! mrvq_wsel_st0 [1:0] $end + $var wire 26 cP qual_addr_st0 [25:0] $end + $var wire 1 MQ qual_going_to_write_st0 $end + $var wire 49 =Q qual_inst_meta_st0 [48:0] $end + $var wire 1 CP qual_is_fill_st0 $end + $var wire 1 1O qual_is_mrvq_st0 $end + $var wire 1 UQ qual_is_snp_st0 $end + $var wire 1 ]Q qual_snp_invalidate_st0 $end + $var wire 1 [P qual_valid_st0 $end + $var wire 1 sT qual_valid_st1e_2 $end + $var wire 128 {P qual_writedata_st0 [127:0] $end + $var wire 32 sP qual_writeword_st0 [31:0] $end + $var wire 2 kP qual_wsel_st0 [1:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 128 +Z! readdata_st2 [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 20 sZ! readtag_st2 [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 32 #Z! readword_st2 [31:0] $end + $var wire 1 YO recover_mrvq_state_st2 $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 KP reqq_pop_unqual $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 _R snp_invalidate_st1(0) $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 -[! snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 q-! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 }m" snp_req_valid $end + $var wire 1 +$ snp_rsp_fire $end + $var wire 1 { snp_rsp_ready $end + $var wire 28 }1 snp_rsp_tag [27:0] $end + $var wire 1 u1 snp_rsp_valid $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 5[! snp_to_mrvq_st2 $end + $var wire 26 ]M snrq_addr_st0 [25:0] $end + $var wire 1 eW! snrq_empty $end + $var wire 1 mW! snrq_full $end + $var wire 1 eM snrq_invalidate_st0 $end + $var wire 1 UM snrq_pop $end + $var wire 1 SP snrq_pop_unqual $end + $var wire 28 mM snrq_tag_st0 [27:0] $end + $var wire 28 }[! snrq_tag_st2 [27:0] $end + $var wire 1 IO st2_pending_hazard_st1e $end + $var wire 1 #P stall_bank_pipe $end + $var wire 42 YS tag_st1e [41:0] $end + $var wire 2 iS tid_st1e [1:0] $end + $var wire 1 eQ valid_st1(0) $end + $var wire 1 ST valid_st1e $end + $var wire 1 iY! valid_st2 $end + $var wire 128 7R writedata_st1(0) [127:0] $end + $var wire 32 }Q writeword_st1(0) [31:0] $end + $var wire 32 yY! writeword_st2 [31:0] $end + $var wire 2 uQ wsel_st1(0) [1:0] $end + $var wire 2 qY! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 ao" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 !u! addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 ;v! dequeue_index [3:0] $end + $var wire 1 1O dequeue_possible $end + $var wire 4 Kv! enqueue_index [3:0] $end + $var wire 1 [v! enqueue_possible $end + $var wire 26 kT fill_addr_st1 [25:0] $end + $var wire 4 Cv! head_ptr [3:0] $end + $var wire 1 y_ increment_head $end + $var wire 1 7Z is_fill_st1 $end + $var wire 1 EU is_mrvq $end + $var wire 16 I_ make_ready [15:0] $end + $var wire 16 Q_ make_ready_push [15:0] $end + $var wire 85 wp! metadata_table(0) [84:0] $end + $var wire 85 zp! metadata_table(1) [84:0] $end + $var wire 85 7q! metadata_table(10) [84:0] $end + $var wire 85 :q! metadata_table(11) [84:0] $end + $var wire 85 =q! metadata_table(12) [84:0] $end + $var wire 85 @q! metadata_table(13) [84:0] $end + $var wire 85 Cq! metadata_table(14) [84:0] $end + $var wire 85 Fq! metadata_table(15) [84:0] $end + $var wire 85 }p! metadata_table(2) [84:0] $end + $var wire 85 "q! metadata_table(3) [84:0] $end + $var wire 85 %q! metadata_table(4) [84:0] $end + $var wire 85 (q! metadata_table(5) [84:0] $end + $var wire 85 +q! metadata_table(6) [84:0] $end + $var wire 85 .q! metadata_table(7) [84:0] $end + $var wire 85 1q! metadata_table(8) [84:0] $end + $var wire 85 4q! metadata_table(9) [84:0] $end + $var wire 1 =U miss_add $end + $var wire 26 i-! miss_add_addr [25:0] $end + $var wire 4 YY! miss_add_byteen [3:0] $end + $var wire 32 yY! miss_add_data [31:0] $end + $var wire 1 %[! miss_add_is_snp $end + $var wire 1 QY! miss_add_rw $end + $var wire 1 -[! miss_add_snp_invalidate $end + $var wire 42 AY! miss_add_tag [41:0] $end + $var wire 2 9Y! miss_add_tid [1:0] $end + $var wire 2 qY! miss_add_wsel [1:0] $end + $var wire 26 WX! miss_resrv_addr_st0 [25:0] $end + $var wire 4 !Y! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 gX! miss_resrv_data_st0 [31:0] $end + $var wire 1 ?X! miss_resrv_full $end + $var wire 1 )Y! miss_resrv_is_snp_st0 $end + $var wire 1 )O miss_resrv_pop $end + $var wire 1 9O miss_resrv_rw_st0 $end + $var wire 1 1Y! miss_resrv_snp_invalidate_st0 $end + $var wire 1 GX! miss_resrv_stop $end + $var wire 42 oX! miss_resrv_tag_st0 [41:0] $end + $var wire 2 OX! miss_resrv_tid_st0 [1:0] $end + $var wire 1 1O miss_resrv_valid_st0 $end + $var wire 2 _X! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 {T mrvq_init_ready_state $end + $var wire 1 i_ mrvq_pop $end + $var wire 1 a_ mrvq_push $end + $var wire 1 AO pending_hazard $end + $var wire 1 +` qual_mrvq_init $end + $var wire 16 3v! ready_table [15:0] $end + $var wire 1 q_ recover_state $end + $var wire 1 [h" reset $end + $var wire 4 ;v! schedule_ptr [3:0] $end + $var wire 5 Sv! size [4:0] $end + $var wire 4 Kv! tail_ptr [3:0] $end + $var wire 1 #` update_ready $end + $var wire 16 Y_ valid_address_match [15:0] $end + $var wire 16 +v! valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 c bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 _h! o_empty $end + $var wire 1 +X out_empty $end + $var wire 120 9W out_per_addr [119:0] $end + $var wire 16 1W out_per_byteen [15:0] $end + $var wire 4 )W out_per_rw [3:0] $end + $var wire 42 yW out_per_tag [41:0] $end + $var wire 4 !W out_per_valids [3:0] $end + $var wire 128 YW out_per_writedata [127:0] $end + $var wire 1 3X pop_qual $end + $var wire 1 o* push_qual $end + $var wire 120 }g! qual_addr [119:0] $end + $var wire 16 ug! qual_byteen [15:0] $end + $var wire 1 WN qual_has_request $end + $var wire 2 _N qual_request_index [1:0] $end + $var wire 4 mg! qual_rw [3:0] $end + $var wire 42 /X! qual_tag [41:0] $end + $var wire 4 eg! qual_valids [3:0] $end + $var wire 128 ?h! qual_writedata [127:0] $end + $var wire 4 ;X real_out_per_valids [3:0] $end + $var wire 1 ON reqq_empty $end + $var wire 1 'X! reqq_full $end + $var wire 1 GN reqq_pop $end + $var wire 1 W* reqq_push $end + $var wire 30 wN reqq_req_addr_st0 [29:0] $end + $var wire 4 oN reqq_req_byteen_st0 [3:0] $end + $var wire 1 gN reqq_req_rw_st0 $end + $var wire 1 WN reqq_req_st0 $end + $var wire 42 /X! reqq_req_tag_st0 [41:0] $end + $var wire 2 _N reqq_req_tid_st0 [1:0] $end + $var wire 32 !O reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 gh! use_empty $end + $var wire 120 }g! use_per_addr [119:0] $end + $var wire 16 ug! use_per_byteen [15:0] $end + $var wire 4 mg! use_per_rw [3:0] $end + $var wire 42 /X! use_per_tag [41:0] $end + $var wire 4 eg! use_per_valids [3:0] $end + $var wire 128 ?h! use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 {$ data_in [313:0] $end + $var wire 314 CX data_out [313:0] $end + $var wire 1 _h! empty $end + $var wire 1 'X! full $end + $var wire 1 3X pop $end + $var wire 1 o* push $end + $var wire 1 5Y reading $end + $var wire 1 [h" reset $end + $var wire 3 oh! size [2:0] $end + $var wire 3 oh! size_r [2:0] $end + $var wire 1 m% writing $end + $scope module genblk3 $end + $var wire 314 wh! data(0) [313:0] $end + $var wire 314 #i! data(1) [313:0] $end + $var wire 314 -i! data(2) [313:0] $end + $var wire 314 7i! data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 ;n! bypass_r $end + $var wire 314 1m! curr_r [313:0] $end + $var wire 1 _h! empty_r $end + $var wire 1 'X! full_r $end + $var wire 314 ?l! head_r [313:0] $end + $var wire 2 3n! rd_ptr_next_r [1:0] $end + $var wire 2 +n! rd_ptr_r [1:0] $end + $var wire 2 #n! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 _N grant_index [1:0] $end + $var wire 4 =Y grant_onehot [3:0] $end + $var wire 1 WN grant_valid $end + $var wire 4 eg! requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 =Y grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 eg! data_in [3:0] $end + $var wire 2 _N data_out [1:0] $end + $var wire 32 EY i [31:0] $end + $var wire 1 WN valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 3` data_in [75:0] $end + $var wire 76 K` data_out [75:0] $end + $var wire 1 U[! empty $end + $var wire 1 ][! full $end + $var wire 1 _* pop $end + $var wire 1 MU push $end + $var wire 1 u% reading $end + $var wire 1 [h" reset $end + $var wire 3 cv! size [2:0] $end + $var wire 3 cv! size_r [2:0] $end + $var wire 1 c` writing $end + $scope module genblk3 $end + $var wire 76 kv! data(0) [75:0] $end + $var wire 76 nv! data(1) [75:0] $end + $var wire 76 qv! data(2) [75:0] $end + $var wire 76 tv! data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Wx! bypass_r $end + $var wire 76 'x! curr_r [75:0] $end + $var wire 1 U[! empty_r $end + $var wire 1 ][! full_r $end + $var wire 76 mw! head_r [75:0] $end + $var wire 2 Ox! rd_ptr_next_r [1:0] $end + $var wire 2 Gx! rd_ptr_r [1:0] $end + $var wire 2 ?x! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 K$ data_in [153:0] $end + $var wire 154 OV data_out [153:0] $end + $var wire 1 uW! empty $end + $var wire 1 }W! full $end + $var wire 1 uM pop $end + $var wire 1 um" push $end + $var wire 1 wV reading $end + $var wire 1 [h" reset $end + $var wire 5 ]_! size [4:0] $end + $var wire 5 ]_! size_r [4:0] $end + $var wire 1 s$ writing $end + $scope module genblk3 $end + $var wire 154 e_! data(0) [153:0] $end + $var wire 154 j_! data(1) [153:0] $end + $var wire 154 9`! data(10) [153:0] $end + $var wire 154 >`! data(11) [153:0] $end + $var wire 154 C`! data(12) [153:0] $end + $var wire 154 H`! data(13) [153:0] $end + $var wire 154 M`! data(14) [153:0] $end + $var wire 154 R`! data(15) [153:0] $end + $var wire 154 o_! data(2) [153:0] $end + $var wire 154 t_! data(3) [153:0] $end + $var wire 154 y_! data(4) [153:0] $end + $var wire 154 ~_! data(5) [153:0] $end + $var wire 154 %`! data(6) [153:0] $end + $var wire 154 *`! data(7) [153:0] $end + $var wire 154 /`! data(8) [153:0] $end + $var wire 154 4`! data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 ]g! bypass_r $end + $var wire 154 {f! curr_r [153:0] $end + $var wire 1 uW! empty_r $end + $var wire 1 }W! full_r $end + $var wire 154 Sf! head_r [153:0] $end + $var wire 4 Ug! rd_ptr_next_r [3:0] $end + $var wire 4 Mg! rd_ptr_r [3:0] $end + $var wire 4 Eg! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 k` data_in [199:0] $end + $var wire 200 Ea data_out [199:0] $end + $var wire 1 e[! empty $end + $var wire 1 m[! full $end + $var wire 1 g* pop $end + $var wire 1 eU push $end + $var wire 1 }% reading $end + $var wire 1 [h" reset $end + $var wire 3 _x! size [2:0] $end + $var wire 3 _x! size_r [2:0] $end + $var wire 1 }a writing $end + $scope module genblk3 $end + $var wire 200 gx! data(0) [199:0] $end + $var wire 200 nx! data(1) [199:0] $end + $var wire 200 ux! data(2) [199:0] $end + $var wire 200 |x! data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 W|! bypass_r $end + $var wire 200 e{! curr_r [199:0] $end + $var wire 1 e[! empty_r $end + $var wire 1 m[! full_r $end + $var wire 200 -{! head_r [199:0] $end + $var wire 2 O|! rd_ptr_next_r [1:0] $end + $var wire 2 G|! rd_ptr_r [1:0] $end + $var wire 2 ?|! wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 MY in [242:0] $end + $var wire 243 Cn! out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 243 Cn! value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 3$ data_in [54:0] $end + $var wire 55 7V data_out [54:0] $end + $var wire 1 eW! empty $end + $var wire 1 mW! full $end + $var wire 1 UM pop $end + $var wire 1 }m" push $end + $var wire 1 GV reading $end + $var wire 1 [h" reset $end + $var wire 5 /\! size [4:0] $end + $var wire 5 /\! size_r [4:0] $end + $var wire 1 C$ writing $end + $scope module genblk3 $end + $var wire 55 7\! data(0) [54:0] $end + $var wire 55 9\! data(1) [54:0] $end + $var wire 55 K\! data(10) [54:0] $end + $var wire 55 M\! data(11) [54:0] $end + $var wire 55 O\! data(12) [54:0] $end + $var wire 55 Q\! data(13) [54:0] $end + $var wire 55 S\! data(14) [54:0] $end + $var wire 55 U\! data(15) [54:0] $end + $var wire 55 ;\! data(2) [54:0] $end + $var wire 55 =\! data(3) [54:0] $end + $var wire 55 ?\! data(4) [54:0] $end + $var wire 55 A\! data(5) [54:0] $end + $var wire 55 C\! data(6) [54:0] $end + $var wire 55 E\! data(7) [54:0] $end + $var wire 55 G\! data(8) [54:0] $end + $var wire 55 I\! data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 U_! bypass_r $end + $var wire 55 -_! curr_r [54:0] $end + $var wire 1 eW! empty_r $end + $var wire 1 mW! full_r $end + $var wire 55 {^! head_r [54:0] $end + $var wire 4 M_! rd_ptr_next_r [3:0] $end + $var wire 4 E_! rd_ptr_r [3:0] $end + $var wire 4 =_! wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 W^ in [315:0] $end + $var wire 316 'p! out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 316 'p! value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 K\ data_write [127:0] $end + $var wire 1 IS dirty_st1e $end + $var wire 16 QS dirtyb_st1e [15:0] $end + $var wire 1 #T fill_saw_dirty_st1e $end + $var wire 1 AS fill_sent $end + $var wire 1 U] force_core_miss $end + $var wire 1 QO force_request_miss_st1e $end + $var wire 1 k\ invalidate_line $end + $var wire 1 +T is_snp_st1e $end + $var wire 4 yS mem_byteen_st1e [3:0] $end + $var wire 1 qS mem_rw_st1e $end + $var wire 1 AS miss_st1e $end + $var wire 1 CT mrvq_init_ready_state_st1e $end + $var wire 128 q[ qual_read_data_st1 [127:0] $end + $var wire 1 Y[ qual_read_dirty_st1 $end + $var wire 16 a[ qual_read_dirtyb_st1 [15:0] $end + $var wire 20 i[ qual_read_tag_st1 [19:0] $end + $var wire 1 Q[ qual_read_valid_st1 $end + $var wire 128 1[ read_data_st1c(0) [127:0] $end + $var wire 1 wZ read_dirty_st1c(0) $end + $var wire 16 ![ read_dirtyb_st1c(0) [15:0] $end + $var wire 20 )[ read_tag_st1c(0) [19:0] $end + $var wire 1 oZ read_valid_st1c(0) $end + $var wire 6 /Z readaddr_st10 [5:0] $end + $var wire 128 wR readdata_st1e [127:0] $end + $var wire 20 9S readtag_st1e [19:0] $end + $var wire 32 oR readword_st1e [31:0] $end + $var wire 1 M] real_miss $end + $var wire 1 {\ real_writefill $end + $var wire 1 =] req_invalid $end + $var wire 1 E] req_miss $end + $var wire 1 [h" reset $end + $var wire 1 5] should_write $end + $var wire 1 k\ snoop_hit_no_pending $end + $var wire 1 3T snp_invalidate_st1e $end + $var wire 1 ;T snp_to_mrvq_st1e $end + $var wire 1 #P stall $end + $var wire 1 #P stall_bank_pipe $end + $var wire 1 s\ tags_match $end + $var wire 128 wR use_read_data_st1e [127:0] $end + $var wire 1 ;\ use_read_dirty_st1e $end + $var wire 16 QS use_read_dirtyb_st1e [15:0] $end + $var wire 20 9S use_read_tag_st1e [19:0] $end + $var wire 1 3\ use_read_valid_st1e $end + $var wire 128 K\ use_write_data [127:0] $end + $var wire 16 C\ use_write_enable [15:0] $end + $var wire 1 ST valid_req_st1e $end + $var wire 16 -] we [15:0] $end + $var wire 2 gZ wordsel_st1e [1:0] $end + $var wire 26 kT writeaddr_st1e [25:0] $end + $var wire 128 GZ writedata_st1e [127:0] $end + $var wire 1 7Z writefill_st1e $end + $var wire 6 /Z writeladdr_st1e [5:0] $end + $var wire 20 %] writetag_st1e [19:0] $end + $var wire 32 ?Z writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 ]] normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 e] normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 m] normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 u] normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 '^ in [165:0] $end + $var wire 166 '^ out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 #P stall $end + $var wire 166 Uo! value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 %o! dirty [63:0] $end + $var wire 1 }] do_write $end + $var wire 1 AS fill_sent $end + $var wire 32 Eo! i [31:0] $end + $var wire 1 k\ invalidate $end + $var wire 32 Mo! j [31:0] $end + $var wire 6 /Z read_addr [5:0] $end + $var wire 128 q[ read_data [127:0] $end + $var wire 1 Y[ read_dirty $end + $var wire 16 a[ read_dirtyb [15:0] $end + $var wire 20 i[ read_tag [19:0] $end + $var wire 1 Q[ read_valid $end + $var wire 1 [h" reset $end + $var wire 1 #P stall_bank_pipe $end + $var wire 20 %] tag_index [19:0] $end + $var wire 64 5o! valid [63:0] $end + $var wire 6 /Z write_addr [5:0] $end + $var wire 128 K\ write_data [127:0] $end + $var wire 16 C\ write_enable [15:0] $end + $var wire 1 {\ write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(2) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 C.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 %! curr_bank_core_req_valid [3:0] $end + $var wire 32 /2 curr_bank_core_rsp_data [31:0] $end + $var wire 1 -! curr_bank_core_rsp_ready $end + $var wire 42 72 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 '2 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 #.! curr_bank_core_rsp_valid $end + $var wire 26 3.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 G2 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 +.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 'n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 _2 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 W2 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 g2 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 5! curr_bank_dram_wb_req_ready $end + $var wire 1 O2 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 ;.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 /n" curr_bank_snp_req_valid $end + $var wire 1 =! curr_bank_snp_rsp_ready $end + $var wire 28 13 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 )3 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 ?f addr_st1(0) [25:0] $end + $var wire 26 =i addr_st1e [25:0] $end + $var wire 26 3.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 C.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 %! core_req_valid [3:0] $end + $var wire 32 /2 core_rsp_data [31:0] $end + $var wire 1 -! core_rsp_ready $end + $var wire 42 72 core_rsp_tag [41:0] $end + $var wire 2 '2 core_rsp_tid [1:0] $end + $var wire 1 #.! core_rsp_valid $end + $var wire 32 {~! cwbq_data [31:0] $end + $var wire 1 O"" cwbq_empty $end + $var wire 1 W"" cwbq_full $end + $var wire 1 !+ cwbq_pop $end + $var wire 1 }i cwbq_push $end + $var wire 1 ;d cwbq_push_stall $end + $var wire 1 'j cwbq_push_unqual $end + $var wire 42 ;~! cwbq_tag [41:0] $end + $var wire 2 3~! cwbq_tid [1:0] $end + $var wire 26 Ob dfpq_addr_st0 [25:0] $end + $var wire 1 o|! dfpq_empty $end + $var wire 128 Wb dfpq_filldata_st0 [127:0] $end + $var wire 1 w|! dfpq_full $end + $var wire 1 Gb dfpq_pop $end + $var wire 1 sd dfpq_pop_unqual $end + $var wire 1 yg dirty_st1e $end + $var wire 1 M!" dirty_st2 $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 16 U!" dirtyb_st2 [15:0] $end + $var wire 26 3.! dram_fill_req_addr [25:0] $end + $var wire 1 ei dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 Kd dram_fill_req_stall $end + $var wire 1 /j dram_fill_req_unqual $end + $var wire 1 G2 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 +.! dram_fill_rsp_ready $end + $var wire 1 'n" dram_fill_rsp_valid $end + $var wire 26 _2 dram_wb_req_addr [25:0] $end + $var wire 16 W2 dram_wb_req_byteen [15:0] $end + $var wire 128 g2 dram_wb_req_data [127:0] $end + $var wire 1 '& dram_wb_req_fire $end + $var wire 1 5! dram_wb_req_ready $end + $var wire 1 O2 dram_wb_req_valid $end + $var wire 1 !#" dwbq_dual_valid_sel $end + $var wire 1 _"" dwbq_empty $end + $var wire 1 g"" dwbq_full $end + $var wire 1 ?j dwbq_is_dwb_in $end + $var wire 1 Oj dwbq_is_dwb_out $end + $var wire 1 Gj dwbq_is_snp_in $end + $var wire 1 Wj dwbq_is_snp_out $end + $var wire 1 )+ dwbq_pop $end + $var wire 1 7j dwbq_push $end + $var wire 1 Cd dwbq_push_stall $end + $var wire 1 _j dwbq_push_unqual $end + $var wire 26 o"" dwbq_req_addr [25:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 u!" fill_saw_dirty_st2 $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 kd going_to_write_st1(0) $end + $var wire 49 Wf inst_meta_st1(0) [48:0] $end + $var wire 49 ]!" inst_meta_st2 [48:0] $end + $var wire 1 [d is_fill_in_pipe $end + $var wire 1 cd is_fill_st1(0) $end + $var wire 1 [~! is_fill_st2 $end + $var wire 1 9g is_mrvq_st1(0) $end + $var wire 1 -i is_mrvq_st1e $end + $var wire 1 -i is_mrvq_st1e_st2 $end + $var wire 1 7"" is_mrvq_st2 $end + $var wire 1 )g is_snp_st1(0) $end + $var wire 1 [h is_snp_st1e $end + $var wire 1 }!" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 1 {h miss_add_because_miss $end + $var wire 1 /"" miss_add_because_pending $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 ui miss_add_is_mrvq $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 1 ei miss_add_unqual $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 1 qg miss_st1e $end + $var wire 1 E!" miss_st2 $end + $var wire 26 Q}! mrvq_addr_st0 [25:0] $end + $var wire 4 y}! mrvq_byteen_st0 [3:0] $end + $var wire 1 9}! mrvq_full $end + $var wire 1 Ui mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 ]i mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 1 Mi mrvq_init_ready_state_st2 $end + $var wire 1 G"" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 #~! mrvq_is_snp_st0 $end + $var wire 1 qc mrvq_pending_hazard_st1e $end + $var wire 1 Yc mrvq_pop $end + $var wire 1 ac mrvq_pop_unqual $end + $var wire 1 3d mrvq_push_stall $end + $var wire 1 5i mrvq_recover_ready_state_st1e $end + $var wire 1 ?"" mrvq_recover_ready_state_st2 $end + $var wire 1 ic mrvq_rw_st0 $end + $var wire 1 +~! mrvq_snp_invalidate_st0 $end + $var wire 1 A}! mrvq_stop $end + $var wire 42 i}! mrvq_tag_st0 [41:0] $end + $var wire 2 I}! mrvq_tid_st0 [1:0] $end + $var wire 1 ac mrvq_valid_st0 $end + $var wire 32 a}! mrvq_writeword_st0 [31:0] $end + $var wire 2 Y}! mrvq_wsel_st0 [1:0] $end + $var wire 26 5e qual_addr_st0 [25:0] $end + $var wire 1 }e qual_going_to_write_st0 $end + $var wire 49 me qual_inst_meta_st0 [48:0] $end + $var wire 1 sd qual_is_fill_st0 $end + $var wire 1 ac qual_is_mrvq_st0 $end + $var wire 1 'f qual_is_snp_st0 $end + $var wire 1 /f qual_snp_invalidate_st0 $end + $var wire 1 -e qual_valid_st0 $end + $var wire 1 Ei qual_valid_st1e_2 $end + $var wire 128 Me qual_writedata_st0 [127:0] $end + $var wire 32 Ee qual_writeword_st0 [31:0] $end + $var wire 2 =e qual_wsel_st0 [1:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 128 %!" readdata_st2 [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 20 m!" readtag_st2 [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 32 {~! readword_st2 [31:0] $end + $var wire 1 +d recover_mrvq_state_st2 $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 {d reqq_pop_unqual $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 1g snp_invalidate_st1(0) $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 '"" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 ;.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 /n" snp_req_valid $end + $var wire 1 /& snp_rsp_fire $end + $var wire 1 =! snp_rsp_ready $end + $var wire 28 13 snp_rsp_tag [27:0] $end + $var wire 1 )3 snp_rsp_valid $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 /"" snp_to_mrvq_st2 $end + $var wire 26 /b snrq_addr_st0 [25:0] $end + $var wire 1 _|! snrq_empty $end + $var wire 1 g|! snrq_full $end + $var wire 1 7b snrq_invalidate_st0 $end + $var wire 1 'b snrq_pop $end + $var wire 1 %e snrq_pop_unqual $end + $var wire 28 ?b snrq_tag_st0 [27:0] $end + $var wire 28 w"" snrq_tag_st2 [27:0] $end + $var wire 1 yc st2_pending_hazard_st1e $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 42 +h tag_st1e [41:0] $end + $var wire 2 ;h tid_st1e [1:0] $end + $var wire 1 7f valid_st1(0) $end + $var wire 1 %i valid_st1e $end + $var wire 1 c~! valid_st2 $end + $var wire 128 gf writedata_st1(0) [127:0] $end + $var wire 32 Of writeword_st1(0) [31:0] $end + $var wire 32 s~! writeword_st2 [31:0] $end + $var wire 2 Gf wsel_st1(0) [1:0] $end + $var wire 2 k~! wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Kp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 y;" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 5=" dequeue_index [3:0] $end + $var wire 1 ac dequeue_possible $end + $var wire 4 E=" enqueue_index [3:0] $end + $var wire 1 U=" enqueue_possible $end + $var wire 26 =i fill_addr_st1 [25:0] $end + $var wire 4 ==" head_ptr [3:0] $end + $var wire 1 Kt increment_head $end + $var wire 1 gn is_fill_st1 $end + $var wire 1 ui is_mrvq $end + $var wire 16 ys make_ready [15:0] $end + $var wire 16 #t make_ready_push [15:0] $end + $var wire 85 q7" metadata_table(0) [84:0] $end + $var wire 85 t7" metadata_table(1) [84:0] $end + $var wire 85 18" metadata_table(10) [84:0] $end + $var wire 85 48" metadata_table(11) [84:0] $end + $var wire 85 78" metadata_table(12) [84:0] $end + $var wire 85 :8" metadata_table(13) [84:0] $end + $var wire 85 =8" metadata_table(14) [84:0] $end + $var wire 85 @8" metadata_table(15) [84:0] $end + $var wire 85 w7" metadata_table(2) [84:0] $end + $var wire 85 z7" metadata_table(3) [84:0] $end + $var wire 85 }7" metadata_table(4) [84:0] $end + $var wire 85 "8" metadata_table(5) [84:0] $end + $var wire 85 %8" metadata_table(6) [84:0] $end + $var wire 85 (8" metadata_table(7) [84:0] $end + $var wire 85 +8" metadata_table(8) [84:0] $end + $var wire 85 .8" metadata_table(9) [84:0] $end + $var wire 1 mi miss_add $end + $var wire 26 3.! miss_add_addr [25:0] $end + $var wire 4 S~! miss_add_byteen [3:0] $end + $var wire 32 s~! miss_add_data [31:0] $end + $var wire 1 }!" miss_add_is_snp $end + $var wire 1 K~! miss_add_rw $end + $var wire 1 '"" miss_add_snp_invalidate $end + $var wire 42 ;~! miss_add_tag [41:0] $end + $var wire 2 3~! miss_add_tid [1:0] $end + $var wire 2 k~! miss_add_wsel [1:0] $end + $var wire 26 Q}! miss_resrv_addr_st0 [25:0] $end + $var wire 4 y}! miss_resrv_byteen_st0 [3:0] $end + $var wire 32 a}! miss_resrv_data_st0 [31:0] $end + $var wire 1 9}! miss_resrv_full $end + $var wire 1 #~! miss_resrv_is_snp_st0 $end + $var wire 1 Yc miss_resrv_pop $end + $var wire 1 ic miss_resrv_rw_st0 $end + $var wire 1 +~! miss_resrv_snp_invalidate_st0 $end + $var wire 1 A}! miss_resrv_stop $end + $var wire 42 i}! miss_resrv_tag_st0 [41:0] $end + $var wire 2 I}! miss_resrv_tid_st0 [1:0] $end + $var wire 1 ac miss_resrv_valid_st0 $end + $var wire 2 Y}! miss_resrv_wsel_st0 [1:0] $end + $var wire 1 Mi mrvq_init_ready_state $end + $var wire 1 ;t mrvq_pop $end + $var wire 1 3t mrvq_push $end + $var wire 1 qc pending_hazard $end + $var wire 1 [t qual_mrvq_init $end + $var wire 16 -=" ready_table [15:0] $end + $var wire 1 Ct recover_state $end + $var wire 1 [h" reset $end + $var wire 4 5=" schedule_ptr [3:0] $end + $var wire 5 M=" size [4:0] $end + $var wire 4 E=" tail_ptr [3:0] $end + $var wire 1 St update_ready $end + $var wire 16 +t valid_address_match [15:0] $end + $var wire 16 %=" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 %! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Y/" o_empty $end + $var wire 1 [l out_empty $end + $var wire 120 ik out_per_addr [119:0] $end + $var wire 16 ak out_per_byteen [15:0] $end + $var wire 4 Yk out_per_rw [3:0] $end + $var wire 42 Kl out_per_tag [41:0] $end + $var wire 4 Qk out_per_valids [3:0] $end + $var wire 128 +l out_per_writedata [127:0] $end + $var wire 1 cl pop_qual $end + $var wire 1 1+ push_qual $end + $var wire 120 w." qual_addr [119:0] $end + $var wire 16 o." qual_byteen [15:0] $end + $var wire 1 )c qual_has_request $end + $var wire 2 1c qual_request_index [1:0] $end + $var wire 4 g." qual_rw [3:0] $end + $var wire 42 )}! qual_tag [41:0] $end + $var wire 4 _." qual_valids [3:0] $end + $var wire 128 9/" qual_writedata [127:0] $end + $var wire 4 kl real_out_per_valids [3:0] $end + $var wire 1 !c reqq_empty $end + $var wire 1 !}! reqq_full $end + $var wire 1 wb reqq_pop $end + $var wire 1 w* reqq_push $end + $var wire 30 Ic reqq_req_addr_st0 [29:0] $end + $var wire 4 Ac reqq_req_byteen_st0 [3:0] $end + $var wire 1 9c reqq_req_rw_st0 $end + $var wire 1 )c reqq_req_st0 $end + $var wire 42 )}! reqq_req_tag_st0 [41:0] $end + $var wire 2 1c reqq_req_tid_st0 [1:0] $end + $var wire 32 Qc reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a/" use_empty $end + $var wire 120 w." use_per_addr [119:0] $end + $var wire 16 o." use_per_byteen [15:0] $end + $var wire 4 g." use_per_rw [3:0] $end + $var wire 42 )}! use_per_tag [41:0] $end + $var wire 4 _." use_per_valids [3:0] $end + $var wire 128 9/" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 !' data_in [313:0] $end + $var wire 314 sl data_out [313:0] $end + $var wire 1 Y/" empty $end + $var wire 1 !}! full $end + $var wire 1 cl pop $end + $var wire 1 1+ push $end + $var wire 1 em reading $end + $var wire 1 [h" reset $end + $var wire 3 i/" size [2:0] $end + $var wire 3 i/" size_r [2:0] $end + $var wire 1 q' writing $end + $scope module genblk3 $end + $var wire 314 q/" data(0) [313:0] $end + $var wire 314 {/" data(1) [313:0] $end + $var wire 314 '0" data(2) [313:0] $end + $var wire 314 10" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 55" bypass_r $end + $var wire 314 +4" curr_r [313:0] $end + $var wire 1 Y/" empty_r $end + $var wire 1 !}! full_r $end + $var wire 314 93" head_r [313:0] $end + $var wire 2 -5" rd_ptr_next_r [1:0] $end + $var wire 2 %5" rd_ptr_r [1:0] $end + $var wire 2 {4" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 1c grant_index [1:0] $end + $var wire 4 mm grant_onehot [3:0] $end + $var wire 1 )c grant_valid $end + $var wire 4 _." requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 mm grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 _." data_in [3:0] $end + $var wire 2 1c data_out [1:0] $end + $var wire 32 um i [31:0] $end + $var wire 1 )c valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 ct data_in [75:0] $end + $var wire 76 {t data_out [75:0] $end + $var wire 1 O"" empty $end + $var wire 1 W"" full $end + $var wire 1 !+ pop $end + $var wire 1 }i push $end + $var wire 1 y' reading $end + $var wire 1 [h" reset $end + $var wire 3 ]=" size [2:0] $end + $var wire 3 ]=" size_r [2:0] $end + $var wire 1 5u writing $end + $scope module genblk3 $end + $var wire 76 e=" data(0) [75:0] $end + $var wire 76 h=" data(1) [75:0] $end + $var wire 76 k=" data(2) [75:0] $end + $var wire 76 n=" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Q?" bypass_r $end + $var wire 76 !?" curr_r [75:0] $end + $var wire 1 O"" empty_r $end + $var wire 1 W"" full_r $end + $var wire 76 g>" head_r [75:0] $end + $var wire 2 I?" rd_ptr_next_r [1:0] $end + $var wire 2 A?" rd_ptr_r [1:0] $end + $var wire 2 9?" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 O& data_in [153:0] $end + $var wire 154 !k data_out [153:0] $end + $var wire 1 o|! empty $end + $var wire 1 w|! full $end + $var wire 1 Gb pop $end + $var wire 1 'n" push $end + $var wire 1 Ik reading $end + $var wire 1 [h" reset $end + $var wire 5 W&" size [4:0] $end + $var wire 5 W&" size_r [4:0] $end + $var wire 1 w& writing $end + $scope module genblk3 $end + $var wire 154 _&" data(0) [153:0] $end + $var wire 154 d&" data(1) [153:0] $end + $var wire 154 3'" data(10) [153:0] $end + $var wire 154 8'" data(11) [153:0] $end + $var wire 154 ='" data(12) [153:0] $end + $var wire 154 B'" data(13) [153:0] $end + $var wire 154 G'" data(14) [153:0] $end + $var wire 154 L'" data(15) [153:0] $end + $var wire 154 i&" data(2) [153:0] $end + $var wire 154 n&" data(3) [153:0] $end + $var wire 154 s&" data(4) [153:0] $end + $var wire 154 x&" data(5) [153:0] $end + $var wire 154 }&" data(6) [153:0] $end + $var wire 154 $'" data(7) [153:0] $end + $var wire 154 )'" data(8) [153:0] $end + $var wire 154 .'" data(9) [153:0] $end + $scope module genblk2 $end + $var wire 1 W." bypass_r $end + $var wire 154 u-" curr_r [153:0] $end + $var wire 1 o|! empty_r $end + $var wire 1 w|! full_r $end + $var wire 154 M-" head_r [153:0] $end + $var wire 4 O." rd_ptr_next_r [3:0] $end + $var wire 4 G." rd_ptr_r [3:0] $end + $var wire 4 ?." wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 Cp" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 200 =u data_in [199:0] $end + $var wire 200 uu data_out [199:0] $end + $var wire 1 _"" empty $end + $var wire 1 g"" full $end + $var wire 1 )+ pop $end + $var wire 1 7j push $end + $var wire 1 #( reading $end + $var wire 1 [h" reset $end + $var wire 3 Y?" size [2:0] $end + $var wire 3 Y?" size_r [2:0] $end + $var wire 1 Ov writing $end + $scope module genblk3 $end + $var wire 200 a?" data(0) [199:0] $end + $var wire 200 h?" data(1) [199:0] $end + $var wire 200 o?" data(2) [199:0] $end + $var wire 200 v?" data(3) [199:0] $end + $scope module genblk2 $end + $var wire 1 QC" bypass_r $end + $var wire 200 _B" curr_r [199:0] $end + $var wire 1 _"" empty_r $end + $var wire 1 g"" full_r $end + $var wire 200 'B" head_r [199:0] $end + $var wire 2 IC" rd_ptr_next_r [1:0] $end + $var wire 2 AC" rd_ptr_r [1:0] $end + $var wire 2 9C" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 #p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 243 }m in [242:0] $end + $var wire 243 =5" out [242:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 243 =5" value [242:0] $end + $upscope $end + $scope module snp_req_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 io" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 55 7& data_in [54:0] $end + $var wire 55 gj data_out [54:0] $end + $var wire 1 _|! empty $end + $var wire 1 g|! full $end + $var wire 1 'b pop $end + $var wire 1 /n" push $end + $var wire 1 wj reading $end + $var wire 1 [h" reset $end + $var wire 5 )#" size [4:0] $end + $var wire 5 )#" size_r [4:0] $end + $var wire 1 G& writing $end + $scope module genblk3 $end + $var wire 55 1#" data(0) [54:0] $end + $var wire 55 3#" data(1) [54:0] $end + $var wire 55 E#" data(10) [54:0] $end + $var wire 55 G#" data(11) [54:0] $end + $var wire 55 I#" data(12) [54:0] $end + $var wire 55 K#" data(13) [54:0] $end + $var wire 55 M#" data(14) [54:0] $end + $var wire 55 O#" data(15) [54:0] $end + $var wire 55 5#" data(2) [54:0] $end + $var wire 55 7#" data(3) [54:0] $end + $var wire 55 9#" data(4) [54:0] $end + $var wire 55 ;#" data(5) [54:0] $end + $var wire 55 =#" data(6) [54:0] $end + $var wire 55 ?#" data(7) [54:0] $end + $var wire 55 A#" data(8) [54:0] $end + $var wire 55 C#" data(9) [54:0] $end + $scope module genblk2 $end + $var wire 1 O&" bypass_r $end + $var wire 55 '&" curr_r [54:0] $end + $var wire 1 _|! empty_r $end + $var wire 1 g|! full_r $end + $var wire 55 u%" head_r [54:0] $end + $var wire 4 G&" rd_ptr_next_r [3:0] $end + $var wire 4 ?&" rd_ptr_r [3:0] $end + $var wire 4 7&" wr_ptr_r [3:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module st_1e_2 $end + $var wire 32 3p" N [31:0] $end + $var wire 32 Wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 316 )s in [315:0] $end + $var wire 316 !7" out [315:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 316 !7" value [315:0] $end + $upscope $end + $scope module tag_data_access $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 128 {p data_write [127:0] $end + $var wire 1 yg dirty_st1e $end + $var wire 16 #h dirtyb_st1e [15:0] $end + $var wire 1 Sh fill_saw_dirty_st1e $end + $var wire 1 qg fill_sent $end + $var wire 1 'r force_core_miss $end + $var wire 1 #d force_request_miss_st1e $end + $var wire 1 =q invalidate_line $end + $var wire 1 [h is_snp_st1e $end + $var wire 4 Kh mem_byteen_st1e [3:0] $end + $var wire 1 Ch mem_rw_st1e $end + $var wire 1 qg miss_st1e $end + $var wire 1 sh mrvq_init_ready_state_st1e $end + $var wire 128 Cp qual_read_data_st1 [127:0] $end + $var wire 1 +p qual_read_dirty_st1 $end + $var wire 16 3p qual_read_dirtyb_st1 [15:0] $end + $var wire 20 ;p qual_read_tag_st1 [19:0] $end + $var wire 1 #p qual_read_valid_st1 $end + $var wire 128 ao read_data_st1c(0) [127:0] $end + $var wire 1 Io read_dirty_st1c(0) $end + $var wire 16 Qo read_dirtyb_st1c(0) [15:0] $end + $var wire 20 Yo read_tag_st1c(0) [19:0] $end + $var wire 1 Ao read_valid_st1c(0) $end + $var wire 6 _n readaddr_st10 [5:0] $end + $var wire 128 Ig readdata_st1e [127:0] $end + $var wire 20 ig readtag_st1e [19:0] $end + $var wire 32 Ag readword_st1e [31:0] $end + $var wire 1 }q real_miss $end + $var wire 1 Mq real_writefill $end + $var wire 1 mq req_invalid $end + $var wire 1 uq req_miss $end + $var wire 1 [h" reset $end + $var wire 1 eq should_write $end + $var wire 1 =q snoop_hit_no_pending $end + $var wire 1 ch snp_invalidate_st1e $end + $var wire 1 kh snp_to_mrvq_st1e $end + $var wire 1 Sd stall $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 1 Eq tags_match $end + $var wire 128 Ig use_read_data_st1e [127:0] $end + $var wire 1 kp use_read_dirty_st1e $end + $var wire 16 #h use_read_dirtyb_st1e [15:0] $end + $var wire 20 ig use_read_tag_st1e [19:0] $end + $var wire 1 cp use_read_valid_st1e $end + $var wire 128 {p use_write_data [127:0] $end + $var wire 16 sp use_write_enable [15:0] $end + $var wire 1 %i valid_req_st1e $end + $var wire 16 ]q we [15:0] $end + $var wire 2 9o wordsel_st1e [1:0] $end + $var wire 26 =i writeaddr_st1e [25:0] $end + $var wire 128 wn writedata_st1e [127:0] $end + $var wire 1 gn writefill_st1e $end + $var wire 6 _n writeladdr_st1e [5:0] $end + $var wire 20 Uq writetag_st1e [19:0] $end + $var wire 32 on writeword_st1e [31:0] $end + $scope module genblk4(0) $end + $var wire 1 /r normal_write $end + $upscope $end + $scope module genblk4(1) $end + $var wire 1 7r normal_write $end + $upscope $end + $scope module genblk4(2) $end + $var wire 1 ?r normal_write $end + $upscope $end + $scope module genblk4(3) $end + $var wire 1 Gr normal_write $end + $upscope $end + $scope module s0_1_c0 $end + $var wire 32 +p" N [31:0] $end + $var wire 32 wn" PASSTHRU [31:0] $end + $var wire 1 Sh" clk $end + $var wire 1 Io" flush $end + $var wire 166 Wr in [165:0] $end + $var wire 166 Wr out [165:0] $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall $end + $var wire 166 O6" value [165:0] $end + $upscope $end + $scope module tag_data_structure $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 64 }5" dirty [63:0] $end + $var wire 1 Or do_write $end + $var wire 1 qg fill_sent $end + $var wire 32 ?6" i [31:0] $end + $var wire 1 =q invalidate $end + $var wire 32 G6" j [31:0] $end + $var wire 6 _n read_addr [5:0] $end + $var wire 128 Cp read_data [127:0] $end + $var wire 1 +p read_dirty $end + $var wire 16 3p read_dirtyb [15:0] $end + $var wire 20 ;p read_tag [19:0] $end + $var wire 1 #p read_valid $end + $var wire 1 [h" reset $end + $var wire 1 Sd stall_bank_pipe $end + $var wire 20 Uq tag_index [19:0] $end + $var wire 64 /6" valid [63:0] $end + $var wire 6 _n write_addr [5:0] $end + $var wire 128 {p write_data [127:0] $end + $var wire 16 sp write_enable [15:0] $end + $var wire 1 Mq write_fill $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module genblk5(3) $end + $var wire 120 {h" curr_bank_core_req_addr [119:0] $end + $var wire 16 sh" curr_bank_core_req_byteen [15:0] $end + $var wire 128 =i" curr_bank_core_req_data [127:0] $end + $var wire 1 k.! curr_bank_core_req_ready $end + $var wire 4 kh" curr_bank_core_req_rw [3:0] $end + $var wire 42 ]i" curr_bank_core_req_tag [41:0] $end + $var wire 4 E! curr_bank_core_req_valid [3:0] $end + $var wire 32 A3 curr_bank_core_rsp_data [31:0] $end + $var wire 1 M! curr_bank_core_rsp_ready $end + $var wire 42 I3 curr_bank_core_rsp_tag [41:0] $end + $var wire 2 93 curr_bank_core_rsp_tid [1:0] $end + $var wire 1 K.! curr_bank_core_rsp_valid $end + $var wire 26 [.! curr_bank_dram_fill_req_addr [25:0] $end + $var wire 1 )-! curr_bank_dram_fill_req_ready $end + $var wire 1 Y3 curr_bank_dram_fill_req_valid $end + $var wire 26 ]m" curr_bank_dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" curr_bank_dram_fill_rsp_data [127:0] $end + $var wire 1 S.! curr_bank_dram_fill_rsp_ready $end + $var wire 1 7n" curr_bank_dram_fill_rsp_valid $end + $var wire 26 q3 curr_bank_dram_wb_req_addr [25:0] $end + $var wire 16 i3 curr_bank_dram_wb_req_byteen [15:0] $end + $var wire 128 y3 curr_bank_dram_wb_req_data [127:0] $end + $var wire 1 U! curr_bank_dram_wb_req_ready $end + $var wire 1 a3 curr_bank_dram_wb_req_valid $end + $var wire 26 mm" curr_bank_snp_req_addr [25:0] $end + $var wire 1 3l" curr_bank_snp_req_invalidate $end + $var wire 1 c.! curr_bank_snp_req_ready $end + $var wire 28 ;l" curr_bank_snp_req_tag [27:0] $end + $var wire 1 ?n" curr_bank_snp_req_valid $end + $var wire 1 ]! curr_bank_snp_rsp_ready $end + $var wire 28 C4 curr_bank_snp_rsp_tag [27:0] $end + $var wire 1 ;4 curr_bank_snp_rsp_valid $end + $scope module bank $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 _n" CACHE_SIZE [31:0] $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" CWBQ_SIZE [31:0] $end + $var wire 32 gn" DFPQ_SIZE [31:0] $end + $var wire 32 on" DFQQ_SIZE [31:0] $end + $var wire 32 wn" DRAM_ENABLE [31:0] $end + $var wire 32 on" DWBQ_SIZE [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 Wn" SNOOP_FORWARDING [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 gn" SNRQ_SIZE [31:0] $end + $var wire 32 wn" STAGE_1_CYCLES [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 32 wn" WRITE_ENABLE [31:0] $end + $var wire 26 oz addr_st1(0) [25:0] $end + $var wire 26 m} addr_st1e [25:0] $end + $var wire 26 [.! addr_st2 [25:0] $end + $var wire 1 Sh" clk $end + $var wire 120 {h" core_req_addr [119:0] $end + $var wire 16 sh" core_req_byteen [15:0] $end + $var wire 128 =i" core_req_data [127:0] $end + $var wire 1 k.! core_req_ready $end + $var wire 4 kh" core_req_rw [3:0] $end + $var wire 42 ]i" core_req_tag [41:0] $end + $var wire 4 E! core_req_valid [3:0] $end + $var wire 32 A3 core_rsp_data [31:0] $end + $var wire 1 M! core_rsp_ready $end + $var wire 42 I3 core_rsp_tag [41:0] $end + $var wire 2 93 core_rsp_tid [1:0] $end + $var wire 1 K.! core_rsp_valid $end + $var wire 32 uE" cwbq_data [31:0] $end + $var wire 1 IG" cwbq_empty $end + $var wire 1 QG" cwbq_full $end + $var wire 1 A+ cwbq_pop $end + $var wire 1 O~ cwbq_push $end + $var wire 1 kx cwbq_push_stall $end + $var wire 1 W~ cwbq_push_unqual $end + $var wire 42 5E" cwbq_tag [41:0] $end + $var wire 2 -E" cwbq_tid [1:0] $end + $var wire 26 !w dfpq_addr_st0 [25:0] $end + $var wire 1 iC" dfpq_empty $end + $var wire 128 )w dfpq_filldata_st0 [127:0] $end + $var wire 1 qC" dfpq_full $end + $var wire 1 wv dfpq_pop $end + $var wire 1 Ey dfpq_pop_unqual $end + $var wire 1 K| dirty_st1e $end + $var wire 1 GF" dirty_st2 $end + $var wire 16 S| dirtyb_st1e [15:0] $end + $var wire 16 OF" dirtyb_st2 [15:0] $end + $var wire 26 [.! dram_fill_req_addr [25:0] $end + $var wire 1 7~ dram_fill_req_fast $end + $var wire 1 )-! dram_fill_req_ready $end + $var wire 1 {x dram_fill_req_stall $end + $var wire 1 _~ dram_fill_req_unqual $end + $var wire 1 Y3 dram_fill_req_valid $end + $var wire 26 ]m" dram_fill_rsp_addr [25:0] $end + $var wire 128 Qk" dram_fill_rsp_data [127:0] $end + $var wire 1 S.! dram_fill_rsp_ready $end + $var wire 1 7n" dram_fill_rsp_valid $end + $var wire 26 q3 dram_wb_req_addr [25:0] $end + $var wire 16 i3 dram_wb_req_byteen [15:0] $end + $var wire 128 y3 dram_wb_req_data [127:0] $end + $var wire 1 +( dram_wb_req_fire $end + $var wire 1 U! dram_wb_req_ready $end + $var wire 1 a3 dram_wb_req_valid $end + $var wire 1 yG" dwbq_dual_valid_sel $end + $var wire 1 YG" dwbq_empty $end + $var wire 1 aG" dwbq_full $end + $var wire 1 o~ dwbq_is_dwb_in $end + $var wire 1 !!! dwbq_is_dwb_out $end + $var wire 1 w~ dwbq_is_snp_in $end + $var wire 1 )!! dwbq_is_snp_out $end + $var wire 1 I+ dwbq_pop $end + $var wire 1 g~ dwbq_push $end + $var wire 1 sx dwbq_push_stall $end + $var wire 1 1!! dwbq_push_unqual $end + $var wire 26 iG" dwbq_req_addr [25:0] $end + $var wire 1 %} fill_saw_dirty_st1e $end + $var wire 1 oF" fill_saw_dirty_st2 $end + $var wire 1 Sx force_request_miss_st1e $end + $var wire 1 =y going_to_write_st1(0) $end + $var wire 49 ){ inst_meta_st1(0) [48:0] $end + $var wire 49 WF" inst_meta_st2 [48:0] $end + $var wire 1 -y is_fill_in_pipe $end + $var wire 1 5y is_fill_st1(0) $end + $var wire 1 UE" is_fill_st2 $end + $var wire 1 i{ is_mrvq_st1(0) $end + $var wire 1 ]} is_mrvq_st1e $end + $var wire 1 ]} is_mrvq_st1e_st2 $end + $var wire 1 1G" is_mrvq_st2 $end + $var wire 1 Y{ is_snp_st1(0) $end + $var wire 1 -} is_snp_st1e $end + $var wire 1 wF" is_snp_st2 $end + $var wire 32 ao" j [31:0] $end + $var wire 4 {| mem_byteen_st1e [3:0] $end + $var wire 1 s| mem_rw_st1e $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 1 M} miss_add_because_miss $end + $var wire 1 )G" miss_add_because_pending $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 G~ miss_add_is_mrvq $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 1 7~ miss_add_unqual $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 1 C| miss_st1e $end + $var wire 1 ?F" miss_st2 $end + $var wire 26 KD" mrvq_addr_st0 [25:0] $end + $var wire 4 sD" mrvq_byteen_st0 [3:0] $end + $var wire 1 3D" mrvq_full $end + $var wire 1 '~ mrvq_init_ready_state_hazard_st0_st1 $end + $var wire 1 /~ mrvq_init_ready_state_hazard_st1e_st1 $end + $var wire 1 E} mrvq_init_ready_state_st1e $end + $var wire 1 }} mrvq_init_ready_state_st2 $end + $var wire 1 AG" mrvq_init_ready_state_unqual_st2 $end + $var wire 1 {D" mrvq_is_snp_st0 $end + $var wire 1 Cx mrvq_pending_hazard_st1e $end + $var wire 1 +x mrvq_pop $end + $var wire 1 3x mrvq_pop_unqual $end + $var wire 1 cx mrvq_push_stall $end + $var wire 1 e} mrvq_recover_ready_state_st1e $end + $var wire 1 9G" mrvq_recover_ready_state_st2 $end + $var wire 1 ;x mrvq_rw_st0 $end + $var wire 1 %E" mrvq_snp_invalidate_st0 $end + $var wire 1 ;D" mrvq_stop $end + $var wire 42 cD" mrvq_tag_st0 [41:0] $end + $var wire 2 CD" mrvq_tid_st0 [1:0] $end + $var wire 1 3x mrvq_valid_st0 $end + $var wire 32 [D" mrvq_writeword_st0 [31:0] $end + $var wire 2 SD" mrvq_wsel_st0 [1:0] $end + $var wire 26 ey qual_addr_st0 [25:0] $end + $var wire 1 Oz qual_going_to_write_st0 $end + $var wire 49 ?z qual_inst_meta_st0 [48:0] $end + $var wire 1 Ey qual_is_fill_st0 $end + $var wire 1 3x qual_is_mrvq_st0 $end + $var wire 1 Wz qual_is_snp_st0 $end + $var wire 1 _z qual_snp_invalidate_st0 $end + $var wire 1 ]y qual_valid_st0 $end + $var wire 1 u} qual_valid_st1e_2 $end + $var wire 128 }y qual_writedata_st0 [127:0] $end + $var wire 32 uy qual_writeword_st0 [31:0] $end + $var wire 2 my qual_wsel_st0 [1:0] $end + $var wire 128 y{ readdata_st1e [127:0] $end + $var wire 128 }E" readdata_st2 [127:0] $end + $var wire 20 ;| readtag_st1e [19:0] $end + $var wire 20 gF" readtag_st2 [19:0] $end + $var wire 32 q{ readword_st1e [31:0] $end + $var wire 32 uE" readword_st2 [31:0] $end + $var wire 1 [x recover_mrvq_state_st2 $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 My reqq_pop_unqual $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writeword_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 a{ snp_invalidate_st1(0) $end + $var wire 1 5} snp_invalidate_st1e $end + $var wire 1 !G" snp_invalidate_st2 $end + $var wire 26 mm" snp_req_addr [25:0] $end + $var wire 1 3l" snp_req_invalidate $end + $var wire 1 c.! snp_req_ready $end + $var wire 28 ;l" snp_req_tag [27:0] $end + $var wire 1 ?n" snp_req_valid $end + $var wire 1 3( snp_rsp_fire $end + $var wire 1 ]! snp_rsp_ready $end + $var wire 28 C4 snp_rsp_tag [27:0] $end + $var wire 1 ;4 snp_rsp_valid $end + $var wire 1 =} snp_to_mrvq_st1e $end + $var wire 1 )G" snp_to_mrvq_st2 $end + $var wire 26 _v snrq_addr_st0 [25:0] $end + $var wire 1 YC" snrq_empty $end + $var wire 1 aC" snrq_full $end + $var wire 1 gv snrq_invalidate_st0 $end + $var wire 1 Wv snrq_pop $end + $var wire 1 Uy snrq_pop_unqual $end + $var wire 28 ov snrq_tag_st0 [27:0] $end + $var wire 28 qG" snrq_tag_st2 [27:0] $end + $var wire 1 Kx st2_pending_hazard_st1e $end + $var wire 1 %y stall_bank_pipe $end + $var wire 42 [| tag_st1e [41:0] $end + $var wire 2 k| tid_st1e [1:0] $end + $var wire 1 gz valid_st1(0) $end + $var wire 1 U} valid_st1e $end + $var wire 1 ]E" valid_st2 $end + $var wire 128 9{ writedata_st1(0) [127:0] $end + $var wire 32 !{ writeword_st1(0) [31:0] $end + $var wire 32 mE" writeword_st2 [31:0] $end + $var wire 2 wz wsel_st1(0) [1:0] $end + $var wire 2 eE" wsel_st2 [1:0] $end + $scope module cache_miss_resrv $end + $var wire 32 Sp" BANK_ID [31:0] $end + $var wire 32 gn" BANK_LINE_SIZE [31:0] $end + $var wire 32 Wn" CACHE_ID [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 gn" MRVQ_SIZE [31:0] $end + $var wire 32 on" NUM_BANKS [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 1o" SNP_REQ_TAG_WIDTH [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 416 s`" addr_table [415:0] $end + $var wire 1 Sh" clk $end + $var wire 4 /b" dequeue_index [3:0] $end + $var wire 1 3x dequeue_possible $end + $var wire 4 ?b" enqueue_index [3:0] $end + $var wire 1 Ob" enqueue_possible $end + $var wire 26 m} fill_addr_st1 [25:0] $end + $var wire 4 7b" head_ptr [3:0] $end + $var wire 1 {*! increment_head $end + $var wire 1 9%! is_fill_st1 $end + $var wire 1 G~ is_mrvq $end + $var wire 16 K*! make_ready [15:0] $end + $var wire 16 S*! make_ready_push [15:0] $end + $var wire 85 k\" metadata_table(0) [84:0] $end + $var wire 85 n\" metadata_table(1) [84:0] $end + $var wire 85 +]" metadata_table(10) [84:0] $end + $var wire 85 .]" metadata_table(11) [84:0] $end + $var wire 85 1]" metadata_table(12) [84:0] $end + $var wire 85 4]" metadata_table(13) [84:0] $end + $var wire 85 7]" metadata_table(14) [84:0] $end + $var wire 85 :]" metadata_table(15) [84:0] $end + $var wire 85 q\" metadata_table(2) [84:0] $end + $var wire 85 t\" metadata_table(3) [84:0] $end + $var wire 85 w\" metadata_table(4) [84:0] $end + $var wire 85 z\" metadata_table(5) [84:0] $end + $var wire 85 }\" metadata_table(6) [84:0] $end + $var wire 85 "]" metadata_table(7) [84:0] $end + $var wire 85 %]" metadata_table(8) [84:0] $end + $var wire 85 (]" metadata_table(9) [84:0] $end + $var wire 1 ?~ miss_add $end + $var wire 26 [.! miss_add_addr [25:0] $end + $var wire 4 ME" miss_add_byteen [3:0] $end + $var wire 32 mE" miss_add_data [31:0] $end + $var wire 1 wF" miss_add_is_snp $end + $var wire 1 EE" miss_add_rw $end + $var wire 1 !G" miss_add_snp_invalidate $end + $var wire 42 5E" miss_add_tag [41:0] $end + $var wire 2 -E" miss_add_tid [1:0] $end + $var wire 2 eE" miss_add_wsel [1:0] $end + $var wire 26 KD" miss_resrv_addr_st0 [25:0] $end + $var wire 4 sD" miss_resrv_byteen_st0 [3:0] $end + $var wire 32 [D" miss_resrv_data_st0 [31:0] $end + $var wire 1 3D" miss_resrv_full $end + $var wire 1 {D" miss_resrv_is_snp_st0 $end + $var wire 1 +x miss_resrv_pop $end + $var wire 1 ;x miss_resrv_rw_st0 $end + $var wire 1 %E" miss_resrv_snp_invalidate_st0 $end + $var wire 1 ;D" miss_resrv_stop $end + $var wire 42 cD" miss_resrv_tag_st0 [41:0] $end + $var wire 2 CD" miss_resrv_tid_st0 [1:0] $end + $var wire 1 3x miss_resrv_valid_st0 $end + $var wire 2 SD" miss_resrv_wsel_st0 [1:0] $end + $var wire 1 }} mrvq_init_ready_state $end + $var wire 1 k*! mrvq_pop $end + $var wire 1 c*! mrvq_push $end + $var wire 1 Cx pending_hazard $end + $var wire 1 -+! qual_mrvq_init $end + $var wire 16 'b" ready_table [15:0] $end + $var wire 1 s*! recover_state $end + $var wire 1 [h" reset $end + $var wire 4 /b" schedule_ptr [3:0] $end + $var wire 5 Gb" size [4:0] $end + $var wire 4 ?b" tail_ptr [3:0] $end + $var wire 1 %+! update_ready $end + $var wire 16 [*! valid_address_match [15:0] $end + $var wire 16 }a" valid_table [15:0] $end + $upscope $end + $scope module core_req_arb $end + $var wire 32 )o" CORE_TAG_ID_BITS [31:0] $end + $var wire 32 !o" CORE_TAG_WIDTH [31:0] $end + $var wire 32 on" CREQ_SIZE [31:0] $end + $var wire 32 on" NUM_REQUESTS [31:0] $end + $var wire 32 on" WORD_SIZE [31:0] $end + $var wire 120 {h" bank_addr [119:0] $end + $var wire 16 sh" bank_byteen [15:0] $end + $var wire 4 kh" bank_rw [3:0] $end + $var wire 42 ]i" bank_tag [41:0] $end + $var wire 4 E! bank_valids [3:0] $end + $var wire 128 =i" bank_writedata [127:0] $end + $var wire 1 Sh" clk $end + $var wire 1 ST" o_empty $end + $var wire 1 -#! out_empty $end + $var wire 120 ;"! out_per_addr [119:0] $end + $var wire 16 3"! out_per_byteen [15:0] $end + $var wire 4 +"! out_per_rw [3:0] $end + $var wire 42 {"! out_per_tag [41:0] $end + $var wire 4 #"! out_per_valids [3:0] $end + $var wire 128 ["! out_per_writedata [127:0] $end + $var wire 1 5#! pop_qual $end + $var wire 1 Q+ push_qual $end + $var wire 120 qS" qual_addr [119:0] $end + $var wire 16 iS" qual_byteen [15:0] $end + $var wire 1 Yw qual_has_request $end + $var wire 2 aw qual_request_index [1:0] $end + $var wire 4 aS" qual_rw [3:0] $end + $var wire 42 #D" qual_tag [41:0] $end + $var wire 4 YS" qual_valids [3:0] $end + $var wire 128 3T" qual_writedata [127:0] $end + $var wire 4 =#! real_out_per_valids [3:0] $end + $var wire 1 Qw reqq_empty $end + $var wire 1 yC" reqq_full $end + $var wire 1 Iw reqq_pop $end + $var wire 1 9+ reqq_push $end + $var wire 30 yw reqq_req_addr_st0 [29:0] $end + $var wire 4 qw reqq_req_byteen_st0 [3:0] $end + $var wire 1 iw reqq_req_rw_st0 $end + $var wire 1 Yw reqq_req_st0 $end + $var wire 42 #D" reqq_req_tag_st0 [41:0] $end + $var wire 2 aw reqq_req_tid_st0 [1:0] $end + $var wire 32 #x reqq_req_writedata_st0 [31:0] $end + $var wire 1 [h" reset $end + $var wire 1 [T" use_empty $end + $var wire 120 qS" use_per_addr [119:0] $end + $var wire 16 iS" use_per_byteen [15:0] $end + $var wire 4 aS" use_per_rw [3:0] $end + $var wire 42 #D" use_per_tag [41:0] $end + $var wire 4 YS" use_per_valids [3:0] $end + $var wire 128 3T" use_per_writedata [127:0] $end + $scope module reqq_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 yo" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 314 %) data_in [313:0] $end + $var wire 314 E#! data_out [313:0] $end + $var wire 1 ST" empty $end + $var wire 1 yC" full $end + $var wire 1 5#! pop $end + $var wire 1 Q+ push $end + $var wire 1 7$! reading $end + $var wire 1 [h" reset $end + $var wire 3 cT" size [2:0] $end + $var wire 3 cT" size_r [2:0] $end + $var wire 1 u) writing $end + $scope module genblk3 $end + $var wire 314 kT" data(0) [313:0] $end + $var wire 314 uT" data(1) [313:0] $end + $var wire 314 !U" data(2) [313:0] $end + $var wire 314 +U" data(3) [313:0] $end + $scope module genblk2 $end + $var wire 1 /Z" bypass_r $end + $var wire 314 %Y" curr_r [313:0] $end + $var wire 1 ST" empty_r $end + $var wire 1 yC" full_r $end + $var wire 314 3X" head_r [313:0] $end + $var wire 2 'Z" rd_ptr_next_r [1:0] $end + $var wire 2 }Y" rd_ptr_r [1:0] $end + $var wire 2 uY" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module sel_bank $end + $var wire 32 on" N [31:0] $end + $var wire 1 Sh" clk $end + $var wire 2 aw grant_index [1:0] $end + $var wire 4 ?$! grant_onehot [3:0] $end + $var wire 1 Yw grant_valid $end + $var wire 4 YS" requests [3:0] $end + $var wire 1 [h" reset $end + $scope module genblk2 $end + $var wire 4 ?$! grant_onehot_r [3:0] $end + $scope module priority_encoder $end + $var wire 32 on" N [31:0] $end + $var wire 4 YS" data_in [3:0] $end + $var wire 2 aw data_out [1:0] $end + $var wire 32 G$! i [31:0] $end + $var wire 1 Yw valid_out $end + $upscope $end + $upscope $end + $upscope $end + $upscope $end + $scope module cwb_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 ;p" DATAW [31:0] $end + $var wire 32 on" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 76 5+! data_in [75:0] $end + $var wire 76 M+! data_out [75:0] $end + $var wire 1 IG" empty $end + $var wire 1 QG" full $end + $var wire 1 A+ pop $end + $var wire 1 O~ push $end + $var wire 1 }) reading $end + $var wire 1 [h" reset $end + $var wire 3 Wb" size [2:0] $end + $var wire 3 Wb" size_r [2:0] $end + $var wire 1 e+! writing $end + $scope module genblk3 $end + $var wire 76 _b" data(0) [75:0] $end + $var wire 76 bb" data(1) [75:0] $end + $var wire 76 eb" data(2) [75:0] $end + $var wire 76 hb" data(3) [75:0] $end + $scope module genblk2 $end + $var wire 1 Kd" bypass_r $end + $var wire 76 yc" curr_r [75:0] $end + $var wire 1 IG" empty_r $end + $var wire 1 QG" full_r $end + $var wire 76 ac" head_r [75:0] $end + $var wire 2 Cd" rd_ptr_next_r [1:0] $end + $var wire 2 ;d" rd_ptr_r [1:0] $end + $var wire 2 3d" wr_ptr_r [1:0] $end + $upscope $end + $upscope $end + $upscope $end + $scope module dfp_queue $end + $var wire 32 wn" BUFFERED_OUTPUT [31:0] $end + $var wire 32 qo" DATAW [31:0] $end + $var wire 32 gn" SIZE [31:0] $end + $var wire 1 Sh" clk $end + $var wire 154 S( data_in [153:0] $end + $var wire 154 Q!! data_out [153:0] $end + $var wire 1 iC" empty $end + $var wire 1 qC" full $end + $var wire 1 wv pop $end + $var wire 1 7n" push $end + $var wire 1 y!! reading $end + $var wire 1 [h" reset $end + $var wire 5 QK" size [4:0] $end + $var wire 5 QK" size_r [4:0] $end + $var wire 1 {( writing $end + $scope module genblk3 $end + $var wire 154 YK" data(0) [153:0] $end + $var wire 154 ^K" data(1) [153:0] $end + $var wire 154 -L" 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